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KA10: Updated for Coverity Errors.

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This commit is contained in:
Richard Cornwell 2017-03-14 20:18:47 -04:00
parent 03958cbf91
commit 7360bb87bb
15 changed files with 283 additions and 266 deletions
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12
PDP10/ka10_cp.c
View File

@ -92,7 +92,7 @@ UNIT cp_unit = {UDATA(cp_srv, UNIT_CDP, 0), 600 };
MTAB cp_mod[] = {
{MTAB_XTD | MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_card_set_fmt, &sim_card_show_fmt, NULL},
&sim_card_set_fmt, &sim_card_show_fmt, NULL},
{0}
};
@ -111,7 +111,7 @@ DEVICE cp_dev = {
*/
t_stat cp_devio(uint32 dev, uint64 *data) {
UNIT *uptr = &cp_unit;
UNIT *uptr = &cp_unit;
struct _card_data *dp;
switch(dev & 3) {
@ -132,7 +132,7 @@ t_stat cp_devio(uint32 dev, uint64 *data) {
uptr->u3 |= DATA_REQ;
set_interrupt(dev, uptr->u3);
}
if (*data & CLR_DATA_REQ)
if (*data & CLR_DATA_REQ)
uptr->u3 &= ~DATA_REQ;
if (*data & CLR_END_CARD)
uptr->u3 &= ~END_CARD;
@ -191,7 +191,7 @@ cp_srv(UNIT *uptr) {
}
sim_activate(uptr, uptr->wait);
return SCPE_OK;
}
}
uptr->u4 = 0;
uptr->u3 &= ~(PUNCH_ON|CARD_IN_PUNCH);
uptr->u3 |= END_CARD;
@ -204,7 +204,7 @@ cp_srv(UNIT *uptr) {
case SCPE_IOERR:
uptr->u3 |= EJECT_FAIL|TROUBLE;
break;
case SCPE_OK:
case SCPE_OK:
break;
}
if ((uptr->u3 & (TROUBLE|TROUBLE_EN)) == (TROUBLE|TROUBLE_EN))
@ -232,7 +232,7 @@ cp_attach(UNIT * uptr, CONST char *file)
t_stat
cp_detach(UNIT * uptr)
{
if (uptr->u3 & CARD_IN_PUNCH)
if (uptr->u3 & CARD_IN_PUNCH)
sim_punch_card(uptr, NULL);
return sim_card_detach(uptr);
}

5
PDP10/ka10_cpu.c
View File

@ -102,7 +102,7 @@
#define HIST_PC2 0x80000000
#define HIST_MIN 64
#define HIST_MAX 500000
#define TMR_RTC 1
#define TMR_RTC 0
#define UNIT_V_MSIZE (UNIT_V_UF + 0)
#if KI
@ -2242,6 +2242,7 @@ unasign:
AD = (CM(AR) + 1) & FMASK;
AR = BR;
BR = AD;
/* Fall through */
case 0130: /* UFA */
case 0140: /* FAD */
@ -3912,7 +3913,7 @@ fm_sel = small_user = user_addr_cmp = page_enable = 0;
for(i=0; i < 128; dev_irq[i++] = 0);
sim_brk_types = sim_brk_dflt = SWMASK ('E');
sim_rtcn_init_unit (&cpu_unit, cpu_unit.wait, TMR_RTC);
sim_activate(&cpu_unit, cpu_unit.wait);
sim_activate(&cpu_unit, 10000);
return SCPE_OK;
}

18
PDP10/ka10_cr.c
View File

@ -87,12 +87,12 @@ const char *cr_description(DEVICE *dptr);
DIB cr_dib = { CR_DEVNUM, 1, cr_devio, NULL};
UNIT cr_unit = {
UDATA(cr_srv, UNIT_CDR, 0), 300,
UDATA(cr_srv, UNIT_CDR, 0), 300,
};
MTAB cr_mod[] = {
{MTAB_XTD | MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_card_set_fmt, &sim_card_show_fmt, NULL},
&sim_card_set_fmt, &sim_card_show_fmt, NULL},
{0}
};
@ -112,7 +112,7 @@ t_stat cr_devio(uint32 dev, uint64 *data) {
UNIT *uptr = &cr_unit;
switch(dev & 3) {
case CONI:
if (uptr->flags & UNIT_ATT &&
if (uptr->flags & UNIT_ATT &&
(uptr->u3 & (READING|CARD_IN_READ|END_CARD)) == 0)
uptr->u3 |= RDY_READ;
*data = uptr->u3;
@ -132,9 +132,9 @@ t_stat cr_devio(uint32 dev, uint64 *data) {
uptr->u3 &= ~(PIA);
uptr->u3 |= *data & PIA;
uptr->u3 &= ~(*data & (CLR_DRDY|CLR_END_CARD|CLR_EOF|CLR_DATA_MISS));
if (*data & EN_TROUBLE)
if (*data & EN_TROUBLE)
uptr->u3 |= TROUBLE_EN;
if (*data & EN_READY)
if (*data & EN_READY)
uptr->u3 |= RDY_READ_EN;
if (*data & READ_CARD) {
uptr->u3 |= READING;
@ -142,12 +142,12 @@ t_stat cr_devio(uint32 dev, uint64 *data) {
uptr->u4 = 0;
sim_activate(uptr, uptr->wait);
}
if (uptr->flags & UNIT_ATT &&
if (uptr->flags & UNIT_ATT &&
(uptr->u3 & (READING|CARD_IN_READ|END_CARD)) == 0)
uptr->u3 |= RDY_READ;
if (uptr->u3 & RDY_READ_EN && uptr->u3 & RDY_READ)
set_interrupt(dev, uptr->u3);
if (uptr->u3 & TROUBLE_EN &&
if (uptr->u3 & TROUBLE_EN &&
(uptr->u3 & (END_CARD|END_FILE|DATA_MISS|TROUBLE)) != 0)
set_interrupt(dev, uptr->u3);
break;
@ -158,7 +158,7 @@ t_stat cr_devio(uint32 dev, uint64 *data) {
*data = uptr->u5;
sim_debug(DEBUG_DATAIO, &cr_dev, "CR: DATAI %012llo\n", *data);
uptr->u3 &= ~DATA_RDY;
} else
} else
*data = 0;
break;
case DATAO:
@ -189,7 +189,7 @@ cr_srv(UNIT *uptr) {
if (uptr->u3 & TROUBLE_EN)
set_interrupt(CR_DEVNUM, uptr->u3);
return SCPE_OK;
case SCPE_OK:
case SCPE_OK:
uptr->u3 |= CARD_IN_READ;
break;
}

2
PDP10/ka10_cty.c
View File

@ -96,7 +96,7 @@ t_stat cty_devio(uint32 dev, uint64 *data) {
cty_unit[0].u3 |= (res & (TEL_RDY | TEL_BSY | KEY_TST));
cty_unit[1].u3 &= ~((res >> 4) & (KEY_RDY | KEY_BSY));
cty_unit[1].u3 |= (res & (KEY_RDY | KEY_BSY));
if ((cty_unit[0].u3 & TEL_RDY) || (cty_unit[1].u3 & KEY_RDY))
if ((cty_unit[0].u3 & TEL_RDY) || (cty_unit[1].u3 & KEY_RDY))
set_interrupt(dev, cty_unit[0].u5);
else
clr_interrupt(dev);

32
PDP10/ka10_dc.c
View File

@ -33,7 +33,7 @@
#define NUM_DEVS_DC 0
#endif
#if (NUM_DEVS_DC > 0)
#if (NUM_DEVS_DC > 0)
#define DC_DEVNUM 0240
@ -107,7 +107,7 @@ const char *dc_description (DEVICE *dptr);
DIB dc_dib = { DC_DEVNUM, 1, &dc_devio, NULL };
UNIT dc_unit = {
UDATA (&dc_svc, TT_MODE_7B+UNIT_IDLE+UNIT_ATTABLE, 0), KBD_POLL_WAIT
UDATA (&dc_svc, TT_MODE_7B+UNIT_IDLE+UNIT_ATTABLE, 0), KBD_POLL_WAIT
};
REG dc_reg[] = {
@ -173,7 +173,7 @@ t_stat dc_devio(uint32 dev, uint64 *data) {
/* Set PI */
uptr->STATUS &= ~PI_CHN;
uptr->STATUS |= PI_CHN & *data;
if (*data & RST_SCN)
if (*data & RST_SCN)
dc_l_count = 0;
if (*data & DTR_SET)
uptr->STATUS |= DTR_SET;
@ -200,17 +200,17 @@ t_stat dc_devio(uint32 dev, uint64 *data) {
break;
case DATAO:
if (*data & (LFLAG << 18))
if (*data & (LFLAG << 18))
ln = (*data >> 18) & 077;
else
else
ln = dc_l_count;
if (ln >= dc_modem) {
if (*data & CAUSE_PI)
if (ln >= dc_modem) {
if (*data & CAUSE_PI)
dc_l_status |= (1LL << ln);
else
dc_l_status &= ~(1LL << ln);
ln -= dc_modem;
sim_debug(DEBUG_DETAIL, &dc_dev, "DC line modem %d %03o\n",
sim_debug(DEBUG_DETAIL, &dc_dev, "DC line modem %d %03o\n",
ln, (uint32)(*data & 0777));
if ((*data & OFF_HOOK) == 0) {
uint32 mask = ~(1 << ln);
@ -258,11 +258,11 @@ t_stat dc_devio(uint32 dev, uint64 *data) {
dc_l_status &= ~(1LL << ln);
ln = ln - dc_modem;
lp = &dc_ldsc[ln];
if (dc_enable & (1 << ln))
if (dc_enable & (1 << ln))
*data |= FLAG|OFF_HOOK;
if (rx_conn & (1 << ln) && lp->conn)
if (rx_conn & (1 << ln) && lp->conn)
*data |= FLAG|CTS;
if (dc_ring & (1 << ln))
if (dc_ring & (1 << ln))
*data |= FLAG|RES_DET;
} else if (ln < dc_desc.lines) {
/* Nothing happens if no recieve data, which is transmit ready */
@ -302,7 +302,7 @@ int32 ln;
return SCPE_OK;
sim_clock_coschedule(uptr, tmxr_poll); /* continue poll */
ln = tmxr_poll_conn (&dc_desc); /* look for connect */
if (ln >= 0) { /* got one? rcv enb*/
if (ln >= 0) { /* got one? rcv enb*/
dc_ldsc[ln].rcve = 1;
dc_ring |= (1 << ln);
dc_l_status |= (1LL << (ln + dc_modem)); /* Flag modem line */
@ -326,7 +326,7 @@ int32 ln;
}
/* If any pending status request, raise the PI signal */
if (dc_l_status)
if (dc_l_status)
set_interrupt(DC_DEVNUM, uptr->STATUS);
return SCPE_OK;
}
@ -347,7 +347,7 @@ t_stat dc_doscan (UNIT *uptr) {
} else {
/* Must be data line */
lmask = 1 << dc_l_count;
if (rx_rdy & lmask)
if (rx_rdy & lmask)
uptr->STATUS |= RCV_PI;
if (tx_enable & lmask)
uptr->STATUS |= XMT_PI;
@ -425,7 +425,7 @@ t_stat dc_setnl (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return r;
if (newln > dc_modem)
return SCPE_ARG;
if ((newln == 0) || (newln > DC10_MLINES) || (newln % 8) != 0)
if ((newln == 0) || (newln >= DC10_MLINES) || (newln % 8) != 0)
return SCPE_ARG;
if (newln < dc_desc.lines) {
for (i = newln, t = 0; i < dc_desc.lines; i++)
@ -515,7 +515,7 @@ t_stat dc_detach (UNIT *uptr)
int32 i;
t_stat reason;
reason = tmxr_detach (&dc_desc, uptr);
for (i = 0; i < dc_desc.lines; i++)
for (i = 0; i < dc_desc.lines; i++)
dc_ldsc[i].rcve = 0;
sim_cancel (uptr);
return reason;

2
PDP10/ka10_defs.h
View File

@ -15,7 +15,7 @@
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

34
PDP10/ka10_dk.c
View File

@ -73,7 +73,7 @@ DIB dk_dib[] = {
{ DK_DEVNUM, 1, &dk_devio, NULL },
{ DK_DEVNUM + 4, 1, &dk_devio, NULL}};
UNIT dk_unit[] = {
UNIT dk_unit[] = {
{UDATA (&dk_svc, UNIT_IDLE, TIM_TPS) },
#if (NUM_DEVS_DK > 1)
{UDATA (&dk_svc, UNIT_IDLE, TIM_TPS) },
@ -94,7 +94,7 @@ t_stat dk_devio(uint32 dev, uint64 *data) {
UNIT *uptr = &dk_unit[unit];
int32 t;
if (unit < 0 || unit > NUM_DEVS_DK)
if (unit < 0 || unit >= NUM_DEVS_DK)
return SCPE_OK;
switch (dev & 3) {
case CONI:
@ -120,28 +120,28 @@ t_stat dk_devio(uint32 dev, uint64 *data) {
}
}
if (*data & CLK_SET_EN)
if (*data & CLK_SET_EN)
uptr->STAT_REG |= CLK_EN;
if (*data & CLK_CLR_EN)
if (*data & CLK_CLR_EN)
uptr->STAT_REG &= ~CLK_EN;
if (*data & CLK_SET_OVF)
if (*data & CLK_SET_OVF)
uptr->STAT_REG |= CLK_OVF;
if (*data & CLK_CLR_OVF)
if (*data & CLK_CLR_OVF)
uptr->STAT_REG &= ~CLK_OVF;
if (*data & CLK_SET_FLG)
if (*data & CLK_SET_FLG)
uptr->STAT_REG |= CLK_FLG;
if (*data & CLK_CLR_FLG)
if (*data & CLK_CLR_FLG)
uptr->STAT_REG &= ~CLK_FLG;
if (*data & CLK_SET_PI)
if (*data & CLK_SET_PI)
uptr->STAT_REG |= CLK_PI;
if (*data & CLK_CLR_PI)
if (*data & CLK_CLR_PI)
uptr->STAT_REG &= ~CLK_PI;
if ((uptr->STAT_REG & CLK_EN) != 0 &&
(uptr->STAT_REG & (CLK_FLG|CLK_OVF))) {
set_interrupt(dev, uptr->STAT_REG & 7);
}
if (uptr->STAT_REG & CLK_EN) {
if (!sim_is_active(uptr)) {
t = sim_rtcn_calb (uptr->capac, TMR_DK + unit); /* calibrate */
@ -160,14 +160,14 @@ t_stat dk_devio(uint32 dev, uint64 *data) {
uptr->INT_REG = (uint32)(*data & RMASK);
if (uptr->STAT_REG & CLK_EN) {
if (uptr->INT_REG == uptr->CLK_REG)
if (uptr->INT_REG == uptr->CLK_REG)
uptr->STAT_REG |= CLK_FLG;
set_interrupt(dev, uptr->STAT_REG & 7);
}
sim_debug(DEBUG_DATAIO, &dk_dev, "DK %03o DATO %012llo PC=%06o\n",
dev, *data, PC);
break;
case DATAI:
*data = (uint64)(uptr->CLK_REG);
sim_debug(DEBUG_DATAIO, &dk_dev, "DK %03o DATI %012llo PC=%06o\n",
@ -179,14 +179,14 @@ t_stat dk_devio(uint32 dev, uint64 *data) {
}
/* Bump counter by 1 */
void dk_count (UNIT *uptr)
void dk_count (UNIT *uptr)
{
int dev;
uptr->CLK_REG++;
if (uptr->CLK_REG & (~RMASK))
if (uptr->CLK_REG & (~RMASK))
uptr->STAT_REG |= CLK_OVF;
uptr->CLK_REG &= RMASK;
if (uptr->INT_REG == uptr->CLK_REG)
if (uptr->INT_REG == uptr->CLK_REG)
uptr->STAT_REG |= CLK_FLG;
if (uptr->STAT_REG & (CLK_FLG|CLK_OVF)) {
dev = ((uptr - dk_unit) << 2) + DK_DEVNUM;

64
PDP10/ka10_dp.c
View File

@ -61,13 +61,13 @@
/* CONI/CONO Flags */
#define SUF_ERR 0000000000100LL
#define SUF_ERR 0000000000100LL
#define SEC_ERR 0000000000200LL
#define ILL_CMD 0000000000400LL
#define ILL_WR 0000000001000LL
#define NOT_RDY 0000000002000LL /* Clear CXR */
#define PRT_ERR 0000000004000LL /* 14-17 Clear CCPE, DSPE, DISK WDPE, CDPE */
#define NXM_ERR 0000000010000LL
#define NXM_ERR 0000000010000LL
#define SLW_CHN 0000000020000LL
#define SRC_ERR 0000000040000LL
#define PWR_FAIL_10 0000000100000LL
@ -169,7 +169,7 @@ t_stat dp_reset(DEVICE *);
t_stat dp_attach(UNIT *, CONST char *);
t_stat dp_detach(UNIT *);
t_stat dp_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat dp_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
t_stat dp_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
const char *cptr);
const char *dp_description (DEVICE *dptr);
@ -332,7 +332,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
int tmp;
static int sect_count;
if (ctlr < 0 || ctlr > NUM_DEVS_DP)
if (ctlr < 0 || ctlr >= NUM_DEVS_DP)
return SCPE_OK;
dptr = dp_devs[ctlr];
@ -344,7 +344,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
#if KI_22BIT
*data |= B22_FLAG;
#endif
sim_debug(DEBUG_CONI, dptr, "DP %03o CONI %012llo %d PC=%o\n", dev,
sim_debug(DEBUG_CONI, dptr, "DP %03o CONI %012llo %d PC=%o\n", dev,
*data, ctlr, PC);
break;
@ -359,7 +359,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
}
/* Clear flags */
uptr->STATUS &= ~(*data & CLRMSK);
if (*data & PRT_ERR)
if (*data & PRT_ERR)
uptr->STATUS &= ~(CLRMSK2);
if (*data & CCW_COMP) {
df10_writecw(df10);
@ -377,7 +377,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
}
uptr++;
}
if (tmp)
if (tmp)
df10->status &= ~PI_ENABLE;
else
df10_setirq(df10);
@ -389,7 +389,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
case DATAI:
res = (uint64)(unit) << 33;
res |= WR_HD_LK; /* Can't write headers. */
if (GET_DTYPE(uptr->flags))
if (GET_DTYPE(uptr->flags))
res |= SEL_RP03;
if (uptr->flags & UNIT_DIS) {
res |= NO_DRIVE;
@ -397,15 +397,15 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
res |= DRV_ONLINE;
cyl = uptr->CUR_CYL;
res |= ((uint64)(cyl & 0377)) << 25;
if (cyl & 0400)
if (cyl & 0400)
res |= SEL_CYL256;
if (sect_count > 20)
sect_count = 0;
res |= SEL_SEC & (uint64)(sect_count << 13);
sect_count++;
if ((uptr->UFLAGS & SEEK_STATE) == 0)
if ((uptr->UFLAGS & SEEK_STATE) == 0)
res |= ON_CYL;
if (uptr->flags & UNIT_WPRT)
if (uptr->flags & UNIT_WPRT)
res |= RD_ONLY;
}
uptr = &dp_unit[ctlr * NUM_UNITS_DP];
@ -414,13 +414,13 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
res |= 0400>>unit;
uptr++;
}
sim_debug(DEBUG_DATAIO, dptr, "DP %03o DATI %012llo %d PC=%o F=%o %o\n",
sim_debug(DEBUG_DATAIO, dptr, "DP %03o DATI %012llo %d PC=%o F=%o %o\n",
dev, res, ctlr, PC, uptr->UFLAGS, sect_count);
*data = res;
break;
case DATAO:
sim_debug(DEBUG_DATAIO, dptr, "DP %03o DATO %012llo, %d PC=%o\n",
sim_debug(DEBUG_DATAIO, dptr, "DP %03o DATO %012llo, %d PC=%o\n",
dev, *data, ctlr, PC);
if (df10->status & BUSY) {
uptr->STATUS |= ILL_CMD;
@ -459,7 +459,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
df10_setirq(df10);
return SCPE_OK;
}
uptr->UFLAGS = ((*data & (SURFACE|SECTOR)) >> 3) | (cyl << 20)
uptr->UFLAGS = ((*data & (SURFACE|SECTOR)) >> 3) | (cyl << 20)
| (tmp << 3) | ctlr;
uptr->DATAPTR = 0; /* Set no data */
CLR_BUF(uptr);
@ -477,10 +477,12 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
df10_setirq(df10);
return SCPE_OK;
case RC:
case RC:
cyl = 0;
uptr->STATUS |= NOT_RDY;
case SK:
/* Fall through */
case SK:
if ((uptr->flags & UNIT_ATT) == 0) {
uptr->STATUS |= NOT_RDY;
return SCPE_OK;
@ -493,10 +495,12 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
uptr->UFLAGS &= ~DONE;
uptr = &dp_unit[ctlr * NUM_UNITS_DP];
for(unit = 0; unit < NUM_UNITS_DP; unit++) {
if (*data & (0400 >> unit))
if (*data & (0400 >> unit))
uptr->UFLAGS &= ~(SEEK_DONE);
uptr++;
}
/* Fall through */
case NO:
tmp = 0;
uptr = &dp_unit[ctlr * NUM_UNITS_DP];
@ -514,11 +518,11 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
}
sim_activate(uptr, 150);
}
return SCPE_OK;
return SCPE_OK;
}
t_stat dp_svc (UNIT *uptr)
t_stat dp_svc (UNIT *uptr)
{
int dtype = GET_DTYPE(uptr->flags);
int ctlr = uptr->UFLAGS & 03;
@ -538,7 +542,7 @@ t_stat dp_svc (UNIT *uptr)
case RD:
/* Cylinder, Surface, Sector all ok */
if (BUF_EMPTY(uptr)) {
sim_debug(DEBUG_DETAIL, dptr,
sim_debug(DEBUG_DETAIL, dptr,
"DP %d cmd=%o cyl=%d (%o) sect=%d surf=%d %d\n",
ctlr, uptr->UFLAGS, cyl, cyl, sect, surf,uptr->CUR_CYL);
uptr->STATUS |= SRC_DONE;
@ -547,7 +551,7 @@ t_stat dp_svc (UNIT *uptr)
uptr->STATUS &= ~BUSY;
df10_finish_op(df10, 0);
return SCPE_OK;
}
}
if (sect >= dp_drv_tab[dtype].sect) {
uptr->UFLAGS |= DONE;
uptr->STATUS &= ~BUSY;
@ -576,7 +580,7 @@ t_stat dp_svc (UNIT *uptr)
}
if (cmd != WR) {
/* Read the block */
int da = ((cyl * dp_drv_tab[dtype].surf + surf)
int da = ((cyl * dp_drv_tab[dtype].surf + surf)
* dp_drv_tab[dtype].sect + sect) * RP_NUMWD;
sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
wc = sim_fread (&dp_buf[ctlr][0], sizeof(uint64), RP_NUMWD,
@ -618,7 +622,7 @@ t_stat dp_svc (UNIT *uptr)
df10->buf = dp_buf[ctlr][uptr->DATAPTR];
r = df10_write(df10);
break;
}
}
sim_debug(DEBUG_DATA, dptr, "Xfer %d %012llo\n",
uptr->DATAPTR, df10->buf);
uptr->DATAPTR++;
@ -629,7 +633,7 @@ t_stat dp_svc (UNIT *uptr)
/* write block the block */
for (; uptr->DATAPTR < RP_NUMWD; uptr->DATAPTR++)
dp_buf[ctlr][uptr->DATAPTR] = 0;
sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
(void)sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
wc = sim_fwrite(&dp_buf[ctlr][0],sizeof(uint64), RP_NUMWD,
uptr->fileref);
uptr->STATUS |= SRC_DONE;
@ -658,14 +662,14 @@ t_stat dp_svc (UNIT *uptr)
uptr->UFLAGS |= DONE;
return SCPE_OK;
}
break;
break;
case CL:
case WH: /* Should never see these */
case NO:
return SCPE_OK;
case RC:
case SK:
case RC:
case SK:
if(uptr->UFLAGS & SEEK_STATE) {
diff = cyl - uptr->CUR_CYL;
diffs = (diff < 0) ? -1 : 1;
@ -755,10 +759,10 @@ dp_boot(int32 unit_num, DEVICE * dptr)
addr = (MEMSIZE - 512) & RMASK;
for (sect = 4; sect <= 7; sect++) {
sim_fseek(uptr->fileref, (sect * RP_NUMWD) * sizeof(uint64), SEEK_SET);
sim_fread (&dp_buf[0][0], sizeof(uint64), RP_NUMWD, uptr->fileref);
(void)sim_fseek(uptr->fileref, (sect * RP_NUMWD) * sizeof(uint64), SEEK_SET);
(void)sim_fread (&dp_buf[0][0], sizeof(uint64), RP_NUMWD, uptr->fileref);
ptr = 0;
for(wc = RP_NUMWD; wc > 0; wc--)
for(wc = RP_NUMWD; wc > 0; wc--)
M[addr++] = dp_buf[0][ptr++];
}
PC = (MEMSIZE - 512) & RMASK;

102
PDP10/ka10_dt.c
View File

@ -81,7 +81,7 @@
#define NUM_DEVS_DT 0
#endif
#if (NUM_DEVS_DT > 0)
#if (NUM_DEVS_DT > 0)
#define DT_DEVNUM 0320
#define DT_NUMDR 8 /* #drives */
#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
@ -235,7 +235,7 @@
#define DTC_V_WORD 8 /* Shift for word count */
#define DTC_M_WORD 0177 /* 128 words per block */
#define DTC_V_BLK 16 /* Shift for Block number */
#define DTC_M_BLK 0777 /* Block mask */
#define DTC_M_BLK 01777 /* Block mask */
/* Logging */
@ -329,7 +329,7 @@ REG dt_reg[] = {
MTAB dt_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_8FMT + UNIT_11FMT, 0, "18b", NULL, NULL },
{ UNIT_8FMT + UNIT_11FMT, UNIT_8FMT, "12b", NULL, NULL },
{ UNIT_8FMT + UNIT_11FMT, UNIT_11FMT, "16b", NULL, NULL },
@ -388,7 +388,7 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
if (*data & DTC_SEL) {
dtsa |= *data & 07000;
i = DTC_GETUNI(dtsa);
if (i <= DT_NUMDR && !sim_is_active(&dt_unit[i]))
if (i < DT_NUMDR && !sim_is_active(&dt_unit[i]))
sim_activate(&dt_unit[i], 1000);
if (dt_unit[i].u4 & DTC_MOT) {
switch (dt_unit[i].u5 & 7) {
@ -417,13 +417,13 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
}
if (*data & (DTC_FWDRV|DTC_RVDRV|DTC_STSTOP)) {
i = DTC_GETUNI(dtsa);
if (i > DT_NUMDR)
if (i >= DT_NUMDR)
break;
if (*data & DTC_STSTOP) {
if ((dt_unit[i].u4 & (DTC_MOT)) != 0) {
dt_unit[i].u3 |= DTC_FNC_STOP;
}
} else {
} else {
/* Start the unit if not already running */
dt_unit[i].u3 &= ~DTC_FNC_STOP;
if ((dt_unit[i].u4 & (DTC_MOT)) == 0) {
@ -433,15 +433,15 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
sim_activate(&dt_unit[i], 10000);
}
switch(*data & (DTC_FWDRV|DTC_RVDRV)) {
case DTC_FWDRV:
case DTC_FWDRV:
if (dt_unit[i].u4 & DTC_REV)
dt_unit[i].u3 |= DTC_FNC_REV;
break;
case DTC_RVDRV:
case DTC_RVDRV:
if ((dt_unit[i].u4 & DTC_REV) == 0)
dt_unit[i].u3 |= DTC_FNC_REV;
break;
case DTC_FWDRV|DTC_RVDRV:
case DTC_FWDRV|DTC_RVDRV:
dt_unit[i].u3 |= DTC_FNC_REV;
break;
}
@ -481,12 +481,12 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
if (*data & DTS_STOP_ALL) {
/* Stop all other drives */
for (i = 0; i < DT_NUMDR; i++) {
if (i != DTC_GETUNI(dtsa) &&
(dt_unit[i].u4 & DTC_MOT) != 0)
if (i != DTC_GETUNI(dtsa) &&
(dt_unit[i].u4 & DTC_MOT) != 0)
dt_unit[i].u3 |= DTC_FNC_STOP;
}
}
if (*data & DTS_FUNC_STOP)
if (*data & DTS_FUNC_STOP)
dtsb |= DTB_STOP;
dtsb = (uint64)((*data & (DTS_PAR_ERR|DTS_DATA_MISS|DTS_JOB_DONE| \
DTS_ILL_OP|DTS_END_ZONE|DTS_BLK_MISS)) << 18);
@ -521,7 +521,7 @@ void dt_getword(t_int64 *data, int req) {
set_interrupt(dev|4, dtsa >> 3);
}
}
void dt_putword(t_int64 *data) {
int dev = dt_dib.dev_num;
clr_interrupt(dev|4);
@ -548,14 +548,14 @@ t_stat dt_svc (UNIT *uptr)
int blk;
int off;
/*
* Check if in motion or stopping.
* Check if in motion or stopping.
*/
if (uptr->u4 & DTC_MOT) {
/* Check if stoping */
if (uptr->u3 & DTC_FNC_STOP) {
/* Stop delay */
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o stopping\n", u);
sim_activate(uptr, 40000);
sim_activate(uptr, 40000);
uptr->u3 &= ~DTC_FNC_STOP;
uptr->u4 &= ~(DTC_MOT);
blk = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
@ -568,26 +568,26 @@ if (uptr->u4 & DTC_MOT) {
blk--;
}
} else {
if (blk <= 01100)
if (blk <= 01100)
blk++;
}
uptr->u5 |= (blk << DTC_V_BLK);
return SCPE_OK;
}
if (uptr->u3 & DTC_FNC_REV) {
sim_activate(uptr, 40000);
sim_activate(uptr, 40000);
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reversing\n", u);
uptr->u3 &= ~DTC_FNC_REV;
uptr->u4 ^= DTC_REV;
return SCPE_OK;
}
if (DTC_GETUNI(dtsa) == u) {
dtsb |= DTB_SPD;
dtsb &= ~(DTB_DLY|DTB_IDL);
}
/* Moving in reverse direction */
if (uptr->u4 & DTC_REV) {
/* Moving in reverse direction */
if (uptr->u4 & DTC_REV) {
if (DTC_GETUNI(dtsa) == u) {
dtsb |= DTB_REV;
dtsa &=~ DTC_FWDRV;
@ -598,19 +598,19 @@ if (uptr->u4 & DTC_MOT) {
/* Set stop */
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev forward end\n", u);
uptr->u3 |= DTC_FNC_STOP;
uptr->u6 = 0;
uptr->u6 = 0;
dtsb |= DTB_END;
dtsb &= ~DTB_IDL;
if (dtsb & DTB_ENDENB)
if (dtsb & DTB_ENDENB)
set_interrupt(DT_DEVNUM, dtsa);
sim_activate(uptr, 10000);
sim_activate(uptr, 10000);
break;
case DTC_FBLK: /* In forward block number */
sim_activate(uptr,30000);
sim_activate(uptr,30000);
word = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
word--;
if (word == 0)
if (word == 0)
uptr->u5 = DTC_FEND;
else
uptr->u5 = DTC_RBLK|(word << DTC_V_BLK);
@ -628,7 +628,7 @@ if (uptr->u4 & DTC_MOT) {
case FNC_READ:
uptr->u3 &= 077077;
dtsb |= DTB_DONE;
if (dtsb & DTB_JOBENB)
if (dtsb & DTB_JOBENB)
set_interrupt(DT_DEVNUM, dtsa);
dtsb &= ~DTB_STOP;
break;
@ -650,7 +650,7 @@ if (uptr->u4 & DTC_MOT) {
case DTC_FCHK: /* In forward checksum */
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev forward check\n", u);
sim_activate(uptr,30000);
sim_activate(uptr,30000);
word = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
uptr->u5 = DTC_FBLK|(word << DTC_V_BLK);
dtsb &= ~(DTB_DAT|DTB_FIN);
@ -689,12 +689,12 @@ if (uptr->u4 & DTC_MOT) {
if ((dtsb & DTB_STOP) == 0)
dt_putword(&data);
break;
case FNC_WRIT:
case FNC_WALL:
if ((dtsb & DTB_STOP) == 0)
dt_getword(&data, (word != 0));
else
else
data = dtdb;
fbuf[off] = (data >> 18) & RMASK;
fbuf[off+1] = data & RMASK;
@ -705,12 +705,12 @@ if (uptr->u4 & DTC_MOT) {
dtsb &= ~DTB_DAT;
dtsb |= DTB_FIN;
}
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev data word %o:%o %012llo %d %06o %06o\n", u, blk, word, data, off,
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev data word %o:%o %012llo %d %06o %06o\n", u, blk, word, data, off,
fbuf[off], fbuf[off+1]);
break;
case DTC_RCHK: /* In reverse checksum */
sim_activate(uptr,30000);
sim_activate(uptr,30000);
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev reverse check\n", u);
word = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
uptr->u5 = DTC_BLOCK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD);
@ -733,7 +733,7 @@ if (uptr->u4 & DTC_MOT) {
case FNC_SRCH:
dtsb |= DTB_DONE;
dtsb &= ~DTB_STOP;
if (dtsb & DTB_JOBENB)
if (dtsb & DTB_JOBENB)
set_interrupt(DT_DEVNUM, dtsa);
break;
case FNC_WMRK:
@ -746,7 +746,7 @@ if (uptr->u4 & DTC_MOT) {
break;
case DTC_RBLK: /* In reverse block number */
sim_activate(uptr,30000);
sim_activate(uptr,30000);
word = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
data = (t_uint64)word;
uptr->u5 = DTC_RCHK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD);
@ -777,7 +777,7 @@ if (uptr->u4 & DTC_MOT) {
break;
case DTC_REND: /* In final endzone */
sim_activate(uptr, 10000);
sim_activate(uptr, 10000);
word = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
word--;
uptr->u5 = DTC_RBLK|(word << DTC_V_BLK);
@ -792,15 +792,15 @@ if (uptr->u4 & DTC_MOT) {
/* Moving in forward direction */
switch (uptr->u5 & 7) {
case DTC_FEND: /* Tape in endzone */
sim_activate(uptr, 100000);
sim_activate(uptr, 100000);
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o forward end\n", u);
uptr->u5 = DTC_FBLK; /* Move to first block */
uptr->u6 = 0;
uptr->u6 = 0;
dtsb &= ~DTB_IDL;
break;
case DTC_FBLK: /* In forward block number */
sim_activate(uptr,30000);
sim_activate(uptr,30000);
dtsb &= ~DTB_END;
dtsb |= DTB_BLKRD;
word = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
@ -831,7 +831,7 @@ if (uptr->u4 & DTC_MOT) {
break;
case DTC_FCHK: /* In forward checksum */
sim_activate(uptr,30000);
sim_activate(uptr,30000);
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o forward check\n", u);
dtsb &= ~DTB_BLKRD;
uptr->u5 &= ~7;
@ -849,7 +849,7 @@ if (uptr->u4 & DTC_MOT) {
case FNC_SRCH:
dtsb |= DTB_DONE;
dtsb &= ~DTB_STOP;
if (dtsb & DTB_JOBENB)
if (dtsb & DTB_JOBENB)
set_interrupt(DT_DEVNUM, dtsa);
break;
case FNC_WMRK:
@ -897,7 +897,7 @@ if (uptr->u4 & DTC_MOT) {
case FNC_WRIT:
if ((dtsb & DTB_STOP) == 0)
dt_getword(&data, (word != DTC_M_WORD));
else
else
data = dtdb;
fbuf[off] = (data >> 18) & RMASK;
fbuf[off+1] = data & RMASK;
@ -911,12 +911,12 @@ if (uptr->u4 & DTC_MOT) {
dtsb &= ~DTB_DAT;
dtsb |= DTB_FIN;
}
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o data word %o:%o %012llo %d %06o %06o\n", u, blk, word, data, off,
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o data word %o:%o %012llo %d %06o %06o\n", u, blk, word, data, off,
fbuf[off], fbuf[off+1]);
break;
case DTC_RCHK: /* In reverse checksum */
sim_activate(uptr,30000);
sim_activate(uptr,30000);
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse check\n", u);
uptr->u5 &= ~(DTC_M_WORD << DTC_V_WORD) | 7;
uptr->u5 |= DTC_RBLK; /* Move to end of block */
@ -925,7 +925,7 @@ if (uptr->u4 & DTC_MOT) {
break;
case DTC_RBLK: /* In reverse block number */
sim_activate(uptr,30000);
sim_activate(uptr,30000);
dtsb &= ~(DTB_CHK);
dtsb |= DTB_IDL;
if (DTC_GETUNI(dtsa) == u) {
@ -952,7 +952,7 @@ if (uptr->u4 & DTC_MOT) {
case FNC_WMRK:
uptr->u3 &= 077077;
dtsb |= DTB_DONE;
if (dtsb & DTB_JOBENB)
if (dtsb & DTB_JOBENB)
set_interrupt(DT_DEVNUM, dtsa);
dtsb &= ~DTB_STOP;
break;
@ -968,18 +968,18 @@ if (uptr->u4 & DTC_MOT) {
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse end\n", u);
dtsb &= ~DTB_IDL;
dtsb |= DTB_END;
if (dtsb & DTB_ENDENB)
if (dtsb & DTB_ENDENB)
set_interrupt(DT_DEVNUM, dtsa);
sim_activate(uptr, 100000);
sim_activate(uptr, 100000);
break;
}
}
/* Check if starting */
} else if (uptr->u3 & DTC_FNC_START) {
/* Start up delay */
sim_activate(uptr, 40000);
sim_activate(uptr, 40000);
uptr->u3 &= ~(0700 | DTC_FNC_START);
if (DTC_GETUNI(dtsa) == u)
if (DTC_GETUNI(dtsa) == u)
uptr->u3 |= dtsa & 0700; /* Copy command */
uptr->u4 |= DTC_MOT;
if (uptr->u3 & DTC_FNC_REV) {
@ -1013,18 +1013,18 @@ dt_boot(int32 unit_num, DEVICE * dptr)
addr = (addr + 1) & RMASK;
word = ((t_uint64)fbuf[off++]) << 18;
word |= (t_uint64)fbuf[off++];
if (addr < 020)
if (addr < 020)
FM[addr] = word;
else
M[addr] = word;
}
if (addr < 020)
if (addr < 020)
FM[addr] = word;
else
M[addr] = word;
uptr->u5 = (1 << DTC_V_BLK) | DTC_BLOCK;
uptr->u4 = DTC_MOT;
sim_activate(uptr,30000);
sim_activate(uptr,30000);
PC = word & RMASK;
return SCPE_OK;
}

16
PDP10/ka10_lp.c
View File

@ -32,7 +32,7 @@
#define NUM_DEVS_LP 0
#endif
#if (NUM_DEVS_LP > 0)
#if (NUM_DEVS_LP > 0)
#define LP_DEVNUM 0126
#define STATUS u3
@ -57,7 +57,7 @@ t_stat lpt_svc (UNIT *uptr);
t_stat lpt_reset (DEVICE *dptr);
t_stat lpt_attach (UNIT *uptr, CONST char *cptr);
t_stat lpt_detach (UNIT *uptr);
t_stat lpt_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
t_stat lpt_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
const char *cptr);
const char *lpt_description (DEVICE *dptr);
int32 lpt_stopioe;
@ -106,7 +106,7 @@ t_stat lpt_devio(uint32 dev, uint64 *data) {
*data = uptr->STATUS;
if ((uptr->flags & UNIT_UC) == 0)
*data |= C96;
if ((uptr->flags & UNIT_ATT) == 0)
if ((uptr->flags & UNIT_ATT) == 0)
*data |= ERR_FLG;
sim_debug(DEBUG_CONI, &lpt_dev, "LP CONI %012llo PC=%06o\n", *data, PC);
break;
@ -120,7 +120,7 @@ t_stat lpt_devio(uint32 dev, uint64 *data) {
uptr->CHL = 0;
uptr->STATUS |= BUSY_FLG;
sim_activate (&lpt_unit, lpt_unit.wait);
}
}
if ((uptr->flags & UNIT_ATT) == 0) {
set_interrupt(dev, (uptr->STATUS >> 3));
}
@ -137,7 +137,7 @@ t_stat lpt_devio(uint32 dev, uint64 *data) {
clr_interrupt(dev);
sim_activate (&lpt_unit, lpt_unit.wait);
}
sim_debug(DEBUG_DATAIO, &lpt_dev, "LP DATO %012llo, %06o %06o PC=%06o\n",
sim_debug(DEBUG_DATAIO, &lpt_dev, "LP DATO %012llo, %06o %06o PC=%06o\n",
*data, uptr->CHL, uptr->CHR, PC);
break;
case DATAI:
@ -152,7 +152,7 @@ t_stat lpt_devio(uint32 dev, uint64 *data) {
t_stat lpt_output(UNIT *uptr, char c) {
if (c == 0)
return SCPE_OK;
if (uptr->flags & UNIT_UC)
if (uptr->flags & UNIT_UC)
c = toupper(c);
fputc (c, uptr->fileref); /* print char */
uptr->pos = ftell (uptr->fileref);
@ -165,7 +165,7 @@ t_stat lpt_output(UNIT *uptr, char c) {
}
return SCPE_OK;
}
t_stat lpt_svc (UNIT *uptr)
{
t_stat r;
@ -174,7 +174,7 @@ t_stat lpt_svc (UNIT *uptr)
uptr->STATUS |= ERR_FLG;
return SCPE_OK;
}
c = (uptr->CHL >> 14) & 0177;
if ((r = lpt_output(uptr, c)) != SCPE_OK)
return r;

86
PDP10/ka10_mt.c
View File

@ -41,7 +41,7 @@
#define NUM_DEVS_MT 0
#endif
#if (NUM_DEVS_MT > 0)
#if (NUM_DEVS_MT > 0)
#define BUF_EMPTY(u) (u->hwmark == 0xFFFFFFFF)
#define CLR_BUF(u) u->hwmark = 0xFFFFFFFF
@ -99,7 +99,7 @@
#define DATA_PIA 000000007 /* 0 */
#define FLAG_PIA 000000070 /* 3 */
#define DENS_200 000000000
#define DENS_200 000000000
#define DENS_556 000000100
#define DENS_800 000000200
#define DENS_MSK 000000300 /* 6 */
@ -199,14 +199,14 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
uint64 res;
DEVICE *dptr = &mt_dev;
UNIT *uptr = &mt_unit[unit];
switch(dev & 07) {
case CONI:
res = (uint64)(pia & (NEXT_UNIT_ENAB|FLAG_PIA|DATA_PIA));
res |= (uint64)(uptr->u3 & 077300);
res |= ((uint64)unit) << 15;
res |= ((uint64)next_unit) << 18;
if (dptr->flags & MTDF_TYPEB)
if (dptr->flags & MTDF_TYPEB)
res |= 7LL; /* Force DATA PIA to 7 on type B */
*data = res;
sim_debug(DEBUG_CONI, dptr, "MT CONI %03o status %06o %o %o PC=%06o\n",
@ -243,7 +243,7 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
int cmd = (uptr->u3 & FUNCTION) >> 9;
uptr->u3 &= ~(MT_BRFUL|MT_BUFFUL);
switch(cmd & 07) {
case NOP_IDLE:
case NOP_CLR:
case REWIND:
case WTM:
break;
@ -257,10 +257,14 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
status |= IDLE_UNIT|ILL_OPR|EOF_FLAG;
break;
}
/* Fall through */
case CMP:
CLR_BUF(uptr);
uptr->u5 = 0;
uptr->u6 = 0;
/* Fall through */
case SPC_REV:
case SPC_FWD:
if ((dptr->flags & MTDF_TYPEB) == 0) {
@ -315,7 +319,7 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
if ((uptr->flags & MTUF_WLK) != 0)
res |= WRITE_LOCK;
#if KI_22BIT
if (dptr->flags & MTDF_TYPEB)
if (dptr->flags & MTDF_TYPEB)
res |= B22_FLAG;
#endif
*data = res;
@ -330,7 +334,7 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
}
if (*data & 2) {
hold_reg ^= mt_df10.buf;
}
}
sim_debug(DEBUG_CONO, dptr, "MT CONO %03o control %o %o %012llo %012llo\n",
dev, uptr->u3, unit, hold_reg, mt_df10.buf);
break;
@ -341,7 +345,7 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
case DATAO|04:
/* Set Initial CCW */
if (dptr->flags & MTDF_TYPEB)
if (dptr->flags & MTDF_TYPEB)
df10_setup(&mt_df10, (uint32) *data);
else
mt_df10.buf ^= hold_reg;
@ -354,9 +358,9 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
/* Wrapper to handle reading of hold register or via DF10 */
void mt_df10_read(DEVICE *dptr, UNIT *uptr) {
if (dptr->flags & MTDF_TYPEB) {
if (!df10_read(&mt_df10)) {
if (!df10_read(&mt_df10)) {
uptr->u3 |= MT_STOP;
return;
return;
}
} else {
if (uptr->u3 & MT_BUFFUL) {
@ -412,11 +416,11 @@ t_stat mt_error(UNIT * uptr, t_stat r, DEVICE * dptr)
switch (r) {
case MTSE_OK: /* no error */
break;
case MTSE_TMK: /* tape mark */
status |= EOF_FLAG;
break;
case MTSE_WRP: /* write protected */
status |= WRITE_LOCK;
break;
@ -424,7 +428,7 @@ t_stat mt_error(UNIT * uptr, t_stat r, DEVICE * dptr)
case MTSE_UNATT: /* unattached */
status |= TRAN_HUNG;
break;
case MTSE_IOERR: /* IO error */
case MTSE_FMT: /* invalid format */
status |= ILL_OPR;
@ -513,14 +517,14 @@ t_stat mt_srv(UNIT * uptr)
case READ:
case READ_NOEOR:
if (uptr->u3 & MT_STOP) {
if ((uint32)uptr->u6 < uptr->hwmark)
if ((uint32)uptr->u6 < uptr->hwmark)
status |= RLC_ERR;
return mt_error(uptr, MTSE_OK, dptr);
}
if (BUF_EMPTY(uptr)) {
uptr->u3 |= MT_MOTION;
status &= ~(IDLE_UNIT|BOT_FLAG|EOF_FLAG|EOT_FLAG|PARITY_ERR);
if ((r = sim_tape_rdrecf(uptr, &mt_buffer[0], &reclen,
if ((r = sim_tape_rdrecf(uptr, &mt_buffer[0], &reclen,
BUFFSIZE)) != MTSE_OK) {
sim_debug(DEBUG_DETAIL, dptr, "MT%o read error %d\n", unit, r);
uptr->u3 &= ~MT_MOTION;
@ -537,17 +541,17 @@ t_stat mt_srv(UNIT * uptr)
if (uptr->flags & MTUF_7TRK) {
cc = 6 * (5 - uptr->u5);
ch = mt_buffer[uptr->u6];
if ((((uptr->u3 & ODD_PARITY) ? 0x40 : 0) ^
if ((((uptr->u3 & ODD_PARITY) ? 0x40 : 0) ^
parity_table[ch & 0x3f]) != 0) {
status |= PARITY_ERR;
}
mt_df10.buf |= (uint64)(ch & 0x3f) << cc;
} else {
if ((uptr->u3 & ODD_PARITY) == 0)
if ((uptr->u3 & ODD_PARITY) == 0)
status |= PARITY_ERR;
cc = (8 * (3 - uptr->u5)) + 4;
ch = mt_buffer[uptr->u6];
if (cc < 0)
if (cc < 0)
mt_df10.buf |= (uint64)(ch & 0x3f);
else
mt_df10.buf |= (uint64)(ch & 0xff) << cc;
@ -556,7 +560,7 @@ t_stat mt_srv(UNIT * uptr)
uptr->u5++;
status &= ~CHAR_COUNT;
status |= (uint64)(uptr->u5) << 18;
if (uptr->u5 == cc_max)
if (uptr->u5 == cc_max)
mt_df10_write(dptr, uptr);
} else {
if ((cmd & 010) == 0) {
@ -573,14 +577,14 @@ t_stat mt_srv(UNIT * uptr)
case CMP:
case CMP_NOEOR:
if (uptr->u3 & MT_STOP) {
if ((uint32)uptr->u6 < uptr->hwmark)
if ((uint32)uptr->u6 < uptr->hwmark)
status |= RLC_ERR;
return mt_error(uptr, MTSE_OK, dptr);
}
if (BUF_EMPTY(uptr)) {
uptr->u3 |= MT_MOTION;
status &= ~(IDLE_UNIT|BOT_FLAG|EOF_FLAG|EOT_FLAG|PARITY_ERR);
if ((r = sim_tape_rdrecf(uptr, &mt_buffer[0], &reclen,
if ((r = sim_tape_rdrecf(uptr, &mt_buffer[0], &reclen,
BUFFSIZE)) != MTSE_OK) {
sim_debug(DEBUG_DETAIL, dptr, "MT%o read error %d\n", unit, r);
uptr->u3 &= ~MT_MOTION;
@ -598,18 +602,18 @@ t_stat mt_srv(UNIT * uptr)
return SCPE_OK;
}
if (uptr->u6 >= (int32)uptr->hwmark) {
if (cmd == CMP_NOEOR)
if (cmd == CMP_NOEOR)
CLR_BUF(uptr);
else
uptr->u3 |= MT_STOP;
} else if ((uptr->u3 & MT_BRFUL) == 0) {
/* Write out first character. */
mt_df10_read(dptr, uptr);
}
}
if ((uptr->u3 & MT_BRFUL) != 0) {
if (uptr->flags & MTUF_7TRK) {
ch = mt_buffer[uptr->u6];
if ((((uptr->u3 & ODD_PARITY) ? 0x40 : 0) ^
if ((((uptr->u3 & ODD_PARITY) ? 0x40 : 0) ^
parity_table[ch & 0x3f]) != (ch & 0x40)) {
status |= PARITY_ERR;
}
@ -617,11 +621,11 @@ t_stat mt_srv(UNIT * uptr)
cc = 6 * (5 - uptr->u5);
ch = (mt_df10.buf >> cc) & 0x3f;
} else {
if ((uptr->u3 & ODD_PARITY) == 0)
if ((uptr->u3 & ODD_PARITY) == 0)
status |= PARITY_ERR;
/* Write next char out */
cc = (8 * (3 - uptr->u5)) + 4;
if (cc < 0)
if (cc < 0)
ch = mt_df10.buf & 0x3f;
else
ch = (mt_df10.buf >> cc) & 0xff;
@ -660,18 +664,18 @@ t_stat mt_srv(UNIT * uptr)
uptr->u6 = 0;
break;
}
if ((uptr->u3 & MT_BRFUL) == 0)
if ((uptr->u3 & MT_BRFUL) == 0)
mt_df10_read(dptr, uptr);
if ((uptr->u3 & MT_BRFUL) != 0) {
if (uptr->flags & MTUF_7TRK) {
cc = 6 * (5 - uptr->u5);
ch = (mt_df10.buf >> cc) & 0x3f;
ch |= ((uptr->u3 & ODD_PARITY) ? 0x40 : 0) ^
ch |= ((uptr->u3 & ODD_PARITY) ? 0x40 : 0) ^
parity_table[ch & 0x3f];
} else {
/* Write next char out */
cc = (8 * (3 - uptr->u5)) + 4;
if (cc < 0)
if (cc < 0)
ch = mt_df10.buf & 0x3f;
else
ch = (mt_df10.buf >> cc) & 0xff;
@ -701,7 +705,7 @@ t_stat mt_srv(UNIT * uptr)
break;
case WTM:
if ((uptr->flags & MTUF_WLK) != 0)
if ((uptr->flags & MTUF_WLK) != 0)
return mt_error(uptr, MTSE_WRP, dptr);
uptr->u3 &= ~MT_MOTION;
status &= ~(IDLE_UNIT|BOT_FLAG|EOT_FLAG);
@ -709,7 +713,7 @@ t_stat mt_srv(UNIT * uptr)
return mt_error(uptr, sim_tape_wrtmk(uptr), dptr);
case ERG:
if ((uptr->flags & MTUF_WLK) != 0)
if ((uptr->flags & MTUF_WLK) != 0)
return mt_error(uptr, MTSE_WRP, dptr);
uptr->u3 &= ~MT_MOTION;
status &= ~(IDLE_UNIT|BOT_FLAG|EOT_FLAG);
@ -726,7 +730,7 @@ t_stat mt_srv(UNIT * uptr)
/* Always skip at least one record */
if ((cmd & 7) == SPC_FWD)
r = sim_tape_sprecf(uptr, &reclen);
else
else
r = sim_tape_sprecr(uptr, &reclen);
switch (r) {
case MTSE_OK: /* no error */
@ -758,17 +762,17 @@ t_stat mt_srv(UNIT * uptr)
void mt_read_word(UNIT *uptr) {
int i, cc, ch;
mt_df10.buf = 0;
for(i = 0; i <= 4; i++) {
cc = (8 * (3 - i)) + 4;
ch = mt_buffer[uptr->u6];
if (cc < 0)
if (cc < 0)
mt_df10.buf |= (uint64)(ch & 0x3f);
else
mt_df10.buf |= (uint64)(ch & 0xff) << cc;
uptr->u6++;
}
}
}
/* Boot from given device */
@ -807,12 +811,12 @@ mt_boot(int32 unit_num, DEVICE * dptr)
uptr->hwmark = reclen;
}
mt_read_word(uptr);
if (addr < 020)
if (addr < 020)
FM[addr] = mt_df10.buf;
else
M[addr] = mt_df10.buf;
}
if (addr < 020)
if (addr < 020)
FM[addr] = mt_df10.buf;
else
M[addr] = mt_df10.buf;
@ -827,16 +831,16 @@ mt_boot(int32 unit_num, DEVICE * dptr)
return SCPE_OK;
}
t_stat set_mta (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
t_stat set_mta (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
DEVICE *dptr;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL)
return SCPE_IERR;
dptr->flags &= ~MTDF_TYPEB;
if (*cptr == 'B')
if (*cptr == 'B')
dptr->flags |= val;
else if (*cptr != 'A')
else if (*cptr != 'A')
return SCPE_ARG;
return SCPE_OK;
}
@ -868,7 +872,7 @@ mt_reset(DEVICE * dptr)
UNIT *uptr = &mt_unit[i];
if (MT_DENS(uptr->dynflags) == MT_DENS_NONE)
uptr->dynflags = MT_200_VALID | MT_556_VALID |
uptr->dynflags = MT_200_VALID | MT_556_VALID |
MT_800_VALID | (MT_DENS_800 << UNIT_V_DF_TAPE);
uptr->u3 = 0;
sim_cancel(uptr);

26
PDP10/ka10_pt.c
View File

@ -30,7 +30,7 @@
#define NUM_DEVS_PT 0
#endif
#if (NUM_DEVS_PT > 0)
#if (NUM_DEVS_PT > 0)
#define PP_DEVNUM 0100
#define PR_DEVNUM 0104
@ -51,10 +51,10 @@ t_stat ptp_svc (UNIT *uptr);
t_stat ptp_reset (DEVICE *dptr);
t_stat ptp_attach (UNIT *uptr, CONST char *cptr);
t_stat ptp_detach (UNIT *uptr);
t_stat ptp_help (FILE *st, DEVICE *dptr, UNIT *uptr,
t_stat ptp_help (FILE *st, DEVICE *dptr, UNIT *uptr,
int32 flag, const char *cptr);
const char *ptp_description (DEVICE *dptr);
t_stat ptr_devio(uint32 dev, uint64 *data);
t_stat ptr_svc (UNIT *uptr);
t_stat ptr_boot(int32 unit_num, DEVICE * dptr);
@ -127,13 +127,13 @@ t_stat ptp_devio(uint32 dev, uint64 *data) {
case CONO:
clr_interrupt(dev);
uptr->STATUS = (PI_DONE|DONE_FLG|BUSY_FLG|BIN_FLG) & *data;
if ((uptr->flags & UNIT_ATT) == 0)
if ((uptr->flags & UNIT_ATT) == 0)
uptr->STATUS |= NO_TAPE_PP;
if (uptr->STATUS & BUSY_FLG) {
uptr->CHR = 0;
sim_activate (&ptp_unit, ptp_unit.wait);
}
if (uptr->STATUS & DONE_FLG)
if (uptr->STATUS & DONE_FLG)
set_interrupt(dev, uptr->STATUS);
sim_debug(DEBUG_CONO, &ptp_dev, "PP: CONO %012llo\n\r", *data);
break;
@ -226,14 +226,14 @@ t_stat ptr_devio(uint32 dev, uint64 *data) {
case CONO:
clr_interrupt(dev);
uptr->STATUS = (PI_DONE|DONE_FLG|BUSY_FLG|BIN_FLG) & *data;
if ((uptr->flags & UNIT_ATT))
if ((uptr->flags & UNIT_ATT))
uptr->STATUS |= TAPE_PR;
if (uptr->STATUS & BUSY_FLG) {
uptr->CHR = 0;
uptr->CHL = 0;
sim_activate (&ptr_unit, ptr_unit.wait);
}
if (uptr->STATUS & DONE_FLG)
if (uptr->STATUS & DONE_FLG)
set_interrupt(dev, uptr->STATUS);
sim_debug(DEBUG_CONO, &ptr_dev, "PT: CONO %012llo\n\r", *data);
break;
@ -285,7 +285,7 @@ t_stat ptr_svc (UNIT *uptr)
} else {
word |= (uint64)(temp);
count--;
}
}
}
uptr->CHL = (word >> 18) & RMASK;
uptr->CHR = word & RMASK;
@ -296,16 +296,16 @@ uint64
ptr_read_word(UNIT *uptr) {
int i, ch;
uint64 word = 0;
for(i = 0; i < 6;) {
if ((ch = getc (uptr->fileref)) == EOF)
if ((ch = getc (uptr->fileref)) == EOF)
return word;
if (ch & 0200) {
word <<= 6;
word |= (uint64)(ch & 077);
i++;
}
}
}
return word;
}
@ -327,12 +327,12 @@ ptr_boot(int32 unit_num, DEVICE * dptr)
wc = (wc + 1) & RMASK;
addr = (addr + 1) & RMASK;
word = ptr_read_word(uptr);
if (addr < 020)
if (addr < 020)
FM[addr] = word;
else
M[addr] = word;
}
if (addr < 020)
if (addr < 020)
FM[addr] = word;
else
M[addr] = word;

36
PDP10/ka10_rc.c
View File

@ -59,11 +59,11 @@
#define EPAR 0000000000001LL
#define SEC_SEL 0000000001400LL /* Read */
#define SECT_CNT 0000000000377LL /* Read */
#define PI 0000007
#define WCW 0000040
#define SEC_SCTR 0600000
#define RST_MSK 0000000177710LL /* CONO reset bits */
#define B22_FLAG 0040000000000LL /* 22 bit controller. */
#define MAINT_SEG 0010000000000LL
@ -200,7 +200,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
int cyl;
int dtype;
if (ctlr < 0 || ctlr > NUM_DEVS_RC)
if (ctlr < 0 || ctlr >= NUM_DEVS_RC)
return SCPE_OK;
dptr = rc_devs[ctlr];
@ -239,7 +239,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
df10_writecw(df10);
} else
df10->status &= ~CCW_COMP;
sim_debug(DEBUG_CONO, dptr, "HK %03o CONO %06o PC=%o %06o\n", dev,
sim_debug(DEBUG_CONO, dptr, "HK %03o CONO %06o PC=%o %06o\n", dev,
(uint32)*data, PC, df10->status);
break;
case DATAI:
@ -280,7 +280,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
tmp = (uint32)(*data >> 15) & ~07;
cyl = (tmp >> 10) & 0777;
if (((cyl & 017) > 9) || (((cyl >> 4) & 017) > 9)) {
sim_debug(DEBUG_DETAIL, dptr, "HK %d non-bcd cyl %02x\n",
sim_debug(DEBUG_DETAIL, dptr, "HK %d non-bcd cyl %02x\n",
ctlr, cyl);
df10_finish_op(df10, TRK_SEL_E);
return SCPE_OK;
@ -289,7 +289,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
((cyl & 0x100) ? 100 : 0);
dtype = GET_DTYPE(uptr->flags);
if (cyl >= rc_drv_tab[dtype].cyl) {
sim_debug(DEBUG_DETAIL, dptr, "HK %d invalid cyl %d %d\n",
sim_debug(DEBUG_DETAIL, dptr, "HK %d invalid cyl %d %d\n",
ctlr, cyl, rc_drv_tab[dtype].cyl);
df10_finish_op(df10, TRK_SEL_E);
return SCPE_OK;
@ -304,7 +304,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
uptr->UFLAGS = tmp | ((*data & WRITE) != 0) | (ctlr << 1);
uptr->DATAPTR = -1; /* Set no data */
if ((*data & WRITE) != 0)
df10_read(df10);
(void)df10_read(df10);
sim_debug(DEBUG_DETAIL, dptr, "HK %d cyl %o\n", ctlr, uptr->UFLAGS);
sim_activate(uptr, 100);
break;
@ -313,7 +313,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
}
t_stat rc_svc (UNIT *uptr)
t_stat rc_svc (UNIT *uptr)
{
int dtype = GET_DTYPE(uptr->flags);
int ctlr = (uptr->UFLAGS >> 1) & 03;
@ -332,7 +332,7 @@ t_stat rc_svc (UNIT *uptr)
cyl = (((cyl >> 4) & 017) * 10) + (cyl & 017) +
((cyl & 0x100) ? 100 : 0);
if (cyl >= rc_drv_tab[dtype].cyl) {
sim_debug(DEBUG_DETAIL, dptr, "HK %d invalid cyl %d %d %o\n",
sim_debug(DEBUG_DETAIL, dptr, "HK %d invalid cyl %d %d %o\n",
ctlr, cyl, rc_drv_tab[dtype].cyl, uptr->UFLAGS);
df10_finish_op(df10, TRK_SEL_E);
return SCPE_OK;
@ -346,7 +346,7 @@ t_stat rc_svc (UNIT *uptr)
}
seg = (((seg >> 4) & 07) * 10) + (seg & 017);
if (seg >= rc_drv_tab[dtype].seg) {
sim_debug(DEBUG_DETAIL, dptr, "HK %d invalid sec %d %d %o\n",
sim_debug(DEBUG_DETAIL, dptr, "HK %d invalid sec %d %d %o\n",
ctlr, seg, rc_drv_tab[dtype].seg, uptr->UFLAGS);
df10_finish_op(df10, S_ERROR);
return SCPE_OK;
@ -357,9 +357,9 @@ t_stat rc_svc (UNIT *uptr)
int da;
da = ((cyl * rc_drv_tab[dtype].seg) + seg) * seg_size;
err = sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
wc = sim_fread (&rc_buf[ctlr][0], sizeof(uint64),
wc = sim_fread (&rc_buf[ctlr][0], sizeof(uint64),
seg_size, uptr->fileref);
sim_debug(DEBUG_DETAIL, dptr, "HK %d Read %d %d %d %x\n",
sim_debug(DEBUG_DETAIL, dptr, "HK %d Read %d %d %d %x\n",
ctlr, da, cyl, seg, uptr->UFLAGS << 1 );
for (; wc < seg_size; wc++)
rc_buf[ctlr][wc] = 0;
@ -373,7 +373,7 @@ t_stat rc_svc (UNIT *uptr)
} else {
df10->buf = rc_buf[ctlr][uptr->DATAPTR];
r = df10_write(df10);
}
}
sim_debug(DEBUG_DATA, dptr, "Xfer %d %012llo %06o %06o\n", uptr->DATAPTR, df10->buf,
df10->wcr, df10->cda);
@ -395,7 +395,7 @@ t_stat rc_svc (UNIT *uptr)
sim_debug(DEBUG_DETAIL, dptr, "HK %d Write %d %d %d %x %d\n",
ctlr, da, cyl, seg, uptr->UFLAGS << 1, uptr->DATAPTR );
err = sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
wc = sim_fwrite(&rc_buf[ctlr][0],sizeof(uint64),
wc = sim_fwrite(&rc_buf[ctlr][0],sizeof(uint64),
seg_size, uptr->fileref);
}
uptr->DATAPTR = -1;
@ -403,7 +403,7 @@ t_stat rc_svc (UNIT *uptr)
if (seg >= rc_drv_tab[dtype].seg) {
seg = 0;
cyl++;
if (cyl >= rc_drv_tab[dtype].cyl)
if (cyl >= rc_drv_tab[dtype].cyl)
cyl = 0;
}
/* Convert seg back to bcd */
@ -416,7 +416,7 @@ t_stat rc_svc (UNIT *uptr)
wr = 0x100;
cyl -= 100;
}
tmp = (cyl % 10);
tmp = (cyl % 10);
cyl /= 10;
cyl <<= 4;
cyl += wr + tmp;
@ -482,8 +482,8 @@ rc_boot(int32 unit_num, DEVICE * dptr)
wps = rc_drv_tab[dtype].wd_seg;
for (sect = 4; sect <= 7; sect++) {
seg = (sect * 128) / wps;
fseek(uptr->fileref, (seg * wps) * sizeof(uint64), SEEK_SET);
fxread (&rc_buf[0][0], sizeof(uint64), wps, uptr->fileref);
(void)sim_fseek(uptr->fileref, (seg * wps) * sizeof(uint64), SEEK_SET);
(void)sim_fread (&rc_buf[0][0], sizeof(uint64), wps, uptr->fileref);
ptr = 0;
for(wc = wps; wc > 0; wc--) {
M[addr++] = rc_buf[0][ptr++];

68
PDP10/ka10_rp.c
View File

@ -99,7 +99,7 @@
#define CR_REG 0770000000000 /* Register number */
#define LOAD_REG 0004000000000 /* Load register */
#define CR_MAINT_MODE 0000100000000 /* Maint mode... not implemented */
#define CR_DRIVE 0000007000000
#define CR_DRIVE 0000007000000
#define CR_GEN_EVD 0000000400000 /* Enable Parity */
#define CR_DXES 0000000200000 /* Disable DXES errors */
#define CR_INAD 0000000077600
@ -108,7 +108,7 @@
#define CR_GO 0000000000001
#define IRQ_VECT 0000000000177 /* Interupt vector */
#define IRQ_KI10 0000002000000
#define IRQ_KI10 0000002000000
#define IRQ_KA10 0000001000000
/* u3 low */
@ -304,7 +304,7 @@ t_stat rp_reset(DEVICE *);
t_stat rp_attach(UNIT *, CONST char *);
t_stat rp_detach(UNIT *);
t_stat rp_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat rp_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
t_stat rp_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
const char *cptr);
const char *rp_description (DEVICE *dptr);
@ -480,7 +480,7 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
#if KI_22BIT
*data |= B22_FLAG;
#endif
sim_debug(DEBUG_CONI, dptr, "RP %03o CONI %06o PC=%o %o\n",
sim_debug(DEBUG_CONI, dptr, "RP %03o CONI %06o PC=%o %o\n",
dev, (uint32)*data, PC, rp_attn[ctlr]);
return SCPE_OK;
@ -513,7 +513,7 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
*data |= ((t_uint64)(rp_drive[ctlr])) << 18;
} else if (rp_reg[ctlr] == 044) {
*data = (t_uint64)rp_ivect[ctlr];
if (rp_imode[ctlr])
if (rp_imode[ctlr])
*data |= IRQ_KI10;
else
*data |= IRQ_KA10;
@ -524,7 +524,7 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
*data |= ((t_uint64)(rp_drive[ctlr])) << 18;
}
*data |= ((t_uint64)(rp_reg[ctlr])) << 30;
sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATI %012llo, %d %d PC=%06o\n",
sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATI %012llo, %d %d PC=%06o\n",
dev, *data, ctlr, rp_drive[ctlr], PC);
return SCPE_OK;
@ -548,10 +548,10 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
/* Start command */
df10_setup(df10, (uint32)(*data >> 6));
rp_write(ctlr, rp_drive[ctlr], 0, (uint32)(*data & 077));
sim_debug(DEBUG_DATAIO, dptr,
sim_debug(DEBUG_DATAIO, dptr,
"RP %03o command %012llo, %d[%d] PC=%06o %06o\n",
dev, *data, ctlr, rp_drive[ctlr], PC, df10->status);
} else if (rp_reg[ctlr] == 044) {
} else if (rp_reg[ctlr] == 044) {
/* Set KI10 Irq vector */
rp_ivect[ctlr] = (int)(*data & IRQ_VECT);
rp_imode[ctlr] = (*data & IRQ_KI10) != 0;
@ -569,13 +569,13 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
return SCPE_OK;
}
rp_drive[ctlr] = (int)(*data >> 18) & 07;
rp_write(ctlr, rp_drive[ctlr], rp_reg[ctlr] & 037,
rp_write(ctlr, rp_drive[ctlr], rp_reg[ctlr] & 037,
(int)(*data & 0777777));
}
} else {
if (rp_reg[ctlr] <= 040) {
rp_drive[ctlr] = (int)(*data >> 18) & 07;
}
}
}
return SCPE_OK;
}
@ -588,7 +588,7 @@ rp_devirq(uint32 dev, int addr) {
int drive;
for (drive = 0; drive < NUM_DEVS_RP; drive++) {
if (rp_dib[drive].dev_num == (dev & 0774))
if (rp_dib[drive].dev_num == (dev & 0774))
return (rp_imode[drive] ? rp_ivect[drive] : addr);
}
return addr;
@ -604,7 +604,7 @@ rp_write(int ctlr, int unit, int reg, uint32 data) {
switch(reg) {
case 000: /* control */
sim_debug(DEBUG_DETAIL, dptr, "RPA%o %d Status=%06o\n", unit, ctlr, uptr->u3);
if (uptr->flags & UNIT_WLK)
if (uptr->flags & UNIT_WLK)
uptr->u3 |= DS_WRL;
df10->status &= ~(1 << df10->ccw_comp);
if ((data & 01) != 0 && (uptr->u3 & DS_DRY) != 0) {
@ -618,14 +618,20 @@ rp_write(int ctlr, int unit, int reg, uint32 data) {
uptr->u4 = 0;
if ((uptr->flags & UNIT_ATT) != 0)
uptr->u3 |= DS_VV;
/* Fall through */
case FNC_RECAL: /* recalibrate */
uptr->u4 &= ~0177777;
/* Fall through */
case FNC_SEARCH: /* search */
case FNC_SEEK: /* seek */
case FNC_RETURN: /* return to center */
case FNC_OFFSET: /* offset */
case FNC_UNLOAD: /* unload */
uptr->u3 &= ~DS_OFF;
/* Fall through */
case FNC_WCHK: /* write check */
case FNC_WRITE: /* write */
case FNC_WRITEH: /* write w/ headers */
@ -639,7 +645,7 @@ rp_write(int ctlr, int unit, int reg, uint32 data) {
uptr->u3 &= ~(DS_ATA|CR_GO);
rp_attn[ctlr] &= ~(1<<unit);
clr_interrupt(rp_dib[ctlr].dev_num);
if ((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0)
if ((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0)
df10_setirq(df10);
break;
case FNC_RELEASE: /* port release */
@ -681,7 +687,7 @@ rp_write(int ctlr, int unit, int reg, uint32 data) {
}
clr_interrupt(rp_dib[ctlr].dev_num);
if (((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0) ||
(df10->status & PI_ENABLE))
(df10->status & PI_ENABLE))
df10_setirq(df10);
break;
case 005: /* sector/track */
@ -724,9 +730,9 @@ rp_read(int ctlr, int unit, int reg) {
case 000: /* control */
df10 = &rp_df10[ctlr];
temp = uptr->u3 & 076;
if (uptr->flags & UNIT_ATT)
if (uptr->flags & UNIT_ATT)
temp |= CS1_DVA;
if (df10->status & BUSY || uptr->u3 & CR_GO)
if (df10->status & BUSY || uptr->u3 & CR_GO)
temp |= CS1_GO;
break;
case 001: /* status */
@ -773,7 +779,7 @@ rp_read(int ctlr, int unit, int reg) {
}
t_stat rp_svc (UNIT *uptr)
t_stat rp_svc (UNIT *uptr)
{
int dtype = GET_DTYPE(uptr->flags);
int ctlr;
@ -840,8 +846,10 @@ t_stat rp_svc (UNIT *uptr)
break;
case FNC_UNLOAD: /* unload */
rp_detach(uptr);
/* Fall through */
case FNC_OFFSET: /* offset */
uptr->u3 |= DS_OFF;
/* Fall through */
case FNC_RETURN: /* return to center */
case FNC_PRESET: /* read-in preset */
case FNC_RECAL: /* recalibrate */
@ -857,7 +865,7 @@ t_stat rp_svc (UNIT *uptr)
case FNC_SEARCH: /* search */
if (GET_SC(uptr->u4) > rp_drv_tab[dtype].sect ||
GET_SF(uptr->u4) > rp_drv_tab[dtype].surf)
GET_SF(uptr->u4) > rp_drv_tab[dtype].surf)
uptr->u3 |= (ER1_IAE << 16)|DS_ERR;
rp_attn[ctlr] |= 1<<unit;
uptr->u3 |= DS_DRY|DS_ATA;
@ -885,13 +893,13 @@ t_stat rp_svc (UNIT *uptr)
df10_setirq(df);
return SCPE_OK;
}
sim_debug(DEBUG_DETAIL, dptr, "RPA%o read (%d,%d,%d)\n", unit, cyl,
sim_debug(DEBUG_DETAIL, dptr, "RPA%o read (%d,%d,%d)\n", unit, cyl,
GET_SC(uptr->u4), GET_SF(uptr->u4));
da = GET_DA(uptr->u4, dtype) * RP_NUMWD;
sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
(void)sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
wc = sim_fread (&rp_buf[ctlr][0], sizeof(uint64), RP_NUMWD,
uptr->fileref);
while (wc < RP_NUMWD)
while (wc < RP_NUMWD)
rp_buf[ctlr][wc++] = 0;
uptr->hwmark = RP_NUMWD;
}
@ -944,13 +952,13 @@ t_stat rp_svc (UNIT *uptr)
rp_buf[ctlr][uptr->u6++] = df->buf;
sim_debug(DEBUG_DATA, dptr, "RPA%o write word %d %012llo\n", unit, uptr->u6, df->buf);
if (r == 0 || uptr->u6 == RP_NUMWD) {
while (uptr->u6 < RP_NUMWD)
while (uptr->u6 < RP_NUMWD)
rp_buf[ctlr][uptr->u6++] = 0;
sim_debug(DEBUG_DETAIL, dptr, "RPA%o write (%d,%d,%d)\n", unit, cyl,
sim_debug(DEBUG_DETAIL, dptr, "RPA%o write (%d,%d,%d)\n", unit, cyl,
GET_SC(uptr->u4), GET_SF(uptr->u4));
da = GET_DA(uptr->u4, dtype) * RP_NUMWD;
sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
sim_fwrite (&rp_buf[ctlr][0], sizeof(uint64), RP_NUMWD,
(void)sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET);
(void)sim_fwrite (&rp_buf[ctlr][0], sizeof(uint64), RP_NUMWD,
uptr->fileref);
uptr->u6 = 0;
if (r) {
@ -979,7 +987,7 @@ t_stat rp_svc (UNIT *uptr)
return SCPE_OK;
}
break;
}
}
return SCPE_OK;
}
@ -1021,12 +1029,12 @@ rp_boot(int32 unit_num, DEVICE * rptr)
uint32 ptr;
int wc;
sim_fseek(uptr->fileref, 0, SEEK_SET);
sim_fread (&rp_buf[0][0], sizeof(uint64), RP_NUMWD, uptr->fileref);
(void)sim_fseek(uptr->fileref, 0, SEEK_SET);
(void)sim_fread (&rp_buf[0][0], sizeof(uint64), RP_NUMWD, uptr->fileref);
addr = rp_buf[0][0] & RMASK;
wc = (rp_buf[0][0] >> 18) & RMASK;
ptr = 1;
for(; wc > 0; wc--)
for(; wc > 0; wc--)
M[addr++] = rp_buf[0][ptr++];
addr = rp_buf[0][ptr++] & RMASK;
M[addr] = rp_buf[0][ptr];
@ -1055,7 +1063,7 @@ t_stat rp_attach (UNIT *uptr, CONST char *cptr)
uptr->u4 = 0;
uptr->u3 &= ~DS_VV;
uptr->u3 |= DS_DPR|DS_MOL|DS_DRY;
if (uptr->flags & UNIT_WLK)
if (uptr->flags & UNIT_WLK)
uptr->u3 |= DS_WRL;
rp_df10[ctlr].status |= PI_ENABLE;
set_interrupt(dib->dev_num, rp_df10[ctlr].status);

46
PDP10/ka10_sys.c
View File

@ -57,7 +57,7 @@ REG *sim_PC = &cpu_reg[0];
int32 sim_emax = 1;
DEVICE *sim_devices[] = {
DEVICE *sim_devices[] = {
&cpu_dev,
#if PDP6 | KA | KI
&cty_dev,
@ -204,7 +204,7 @@ uint32 pa;
int32 op, i, ldrc;
data = getrimw (fileref); /* get first word */
if ((data < 0) || ((data & AMASK) != 0)) /* error? SA != 0? */
if ((data & AMASK) != 0) /* error? SA != 0? */
return SCPE_FMT;
ldrc = 1 + (RMASK ^ ((int32) ((data >> 18) & RMASK))); /* get loader count */
if (ldrc == 016) /* 16? RIM10B */
@ -257,11 +257,11 @@ return SCPE_OK;
}
int get_word(FILE *fileref, uint64 *word)
int get_word(FILE *fileref, uint64 *word)
{
char cbuf[5];
if (sim_fread(cbuf, 1, 5, fileref) != 5)
if (sim_fread(cbuf, 1, 5, fileref) != 5)
return 1;
*word = ((uint64)(cbuf[0]) << 29) |
((uint64)(cbuf[1]) << 22) |
@ -351,7 +351,7 @@ uint32 ma;
ndir = entvec = 0; /* no dir, entvec */
cont = 1;
do {
wc = fxread (&data, sizeof (uint64), 1, fileref); /* read blk hdr */
wc = sim_fread (&data, sizeof (uint64), 1, fileref);/* read blk hdr */
if (wc == 0) /* error? */
return SCPE_FMT;
bsz = (int32) ((data & RMASK) - 1); /* get count */
@ -363,19 +363,19 @@ do {
case EXE_DIR: /* directory */
if (ndir) /* got one */
return SCPE_FMT;
ndir = fxread (dirbuf, sizeof (uint64), bsz, fileref);
ndir = sim_fread (dirbuf, sizeof (uint64), bsz, fileref);
if (ndir < bsz) /* error */
return SCPE_FMT;
break;
case EXE_PDV: /* ??? */
fseek (fileref, bsz * sizeof (uint64), SEEK_CUR);
(void)sim_fseek (fileref, bsz * sizeof (uint64), SEEK_CUR);
break;
case EXE_VEC: /* entry vec */
if (bsz != 2) /* must be 2 wds */
return SCPE_FMT;
entvec = fxread (entbuf, sizeof (uint64), bsz, fileref);
entvec = sim_fread (entbuf, sizeof (uint64), bsz, fileref);
if (entvec < 2) /* error? */
return SCPE_FMT;
cont = 0; /* stop */
@ -398,8 +398,8 @@ for (i = 0; i < ndir; i = i + 2) { /* loop thru dir */
rpt = (int32) ((dirbuf[i + 1] >> 27) + 1); /* repeat count */
for (j = 0; j < rpt; j++, mpage++) { /* loop thru rpts */
if (fpage) { /* file pages? */
fseek (fileref, (fpage << PAG_V_PN) * sizeof (uint64), SEEK_SET);
wc = fxread (pagbuf, sizeof (uint64), PAG_SIZE, fileref);
(void)sim_fseek (fileref, (fpage << PAG_V_PN) * sizeof (uint64), SEEK_SET);
wc = sim_fread (pagbuf, sizeof (uint64), PAG_SIZE, fileref);
if (wc < PAG_SIZE)
return SCPE_FMT;
fpage++;
@ -479,7 +479,7 @@ return SCPE_FMT;
static const uint64 masks[] = {
0777000000000, 0777740000000,
0700340000000, 0777777777777
};
};
static const char *opcode[] = {
"PORTAL", "JRSTF", "HALT", /* AC defines op */
@ -497,7 +497,7 @@ static const char *opcode[] = {
"MUUO60", "MUUO61", "MUUO62", "MUUO63", "MUUO64", "MUUO65", "MUUO66", "MUUO67",
"MUUO70", "MUUO71", "MUUO72", "MUUO73", "MUUO74", "MUUO75", "MUUO76", "MUUO77",
"UJEN", "MUUO101", "MUUO102", "JSYS", "MUUO104", "MUUO105", "MUUO106",
"UJEN", "MUUO101", "MUUO102", "JSYS", "MUUO104", "MUUO105", "MUUO106",
"DFAD", "DFSB", "DFMP", "DFDV", "DADD", "DSUB", "DMUL", "DDIV",
"DMOVE", "DMOVN", "FIX", "EXTEND", "DMOVEM", "DMOVNM", "FIXR", "FLTR",
"UFA", "DFN", "FSC", "ADJBP", "ILDB", "LDB", "IDPB", "DPB",
@ -510,8 +510,8 @@ static const char *opcode[] = {
"MOVN", "MOVNI", "MOVNM", "MOVNS", "MOVM", "MOVMI", "MOVMM", "MOVMS",
"IMUL", "IMULI", "IMULM", "IMULB", "MUL", "MULI", "MULM", "MULB",
"IDIV", "IDIVI", "IDIVM", "IDIVB", "DIV", "DIVI", "DIVM", "DIVB",
"ASH", "ROT", "LSH", "JFFO", "ASHC", "ROTC", "LSHC",
"EXCH", "BLT", "AOBJP", "AOBJN", "JRST", "JFCL", "XCT", "MAP",
"ASH", "ROT", "LSH", "JFFO", "ASHC", "ROTC", "LSHC",
"EXCH", "BLT", "AOBJP", "AOBJN", "JRST", "JFCL", "XCT", "MAP",
"PUSHJ", "PUSH", "POP", "POPJ", "JSR", "JSP", "JSA", "JRA",
"ADD", "ADDI", "ADDM", "ADDB", "SUB", "SUBI", "SUBM", "SUBB",
@ -524,16 +524,16 @@ static const char *opcode[] = {
"SOJ", "SOJL", "SOJE", "SOJLE", "SOJA", "SOJGE", "SOJN", "SOJG",
"SOS", "SOSL", "SOSE", "SOSLE", "SOSA", "SOSGE", "SOSN", "SOSG",
"SETZ", "SETZI", "SETZM", "SETZB", "AND", "ANDI", "ANDM", "ANDB",
"SETZ", "SETZI", "SETZM", "SETZB", "AND", "ANDI", "ANDM", "ANDB",
"ANDCA", "ANDCAI", "ANDCAM", "ANDCAB", "SETM", "SETMI", "SETMM", "SETMB",
"ANDCM", "ANDCMI", "ANDCMM", "ANDCMB", "SETA", "SETAI", "SETAM", "SETAB",
"XOR", "XORI", "XORM", "XORB", "IOR", "IORI", "IORM", "IORB",
"ANDCB", "ANDCBI", "ANDCBM", "ANDCBB", "EQV", "EQVI", "EQVM", "EQVB",
"XOR", "XORI", "XORM", "XORB", "IOR", "IORI", "IORM", "IORB",
"ANDCB", "ANDCBI", "ANDCBM", "ANDCBB", "EQV", "EQVI", "EQVM", "EQVB",
"SETCA", "SETCAI", "SETCAM", "SETCAB", "ORCA", "ORCAI", "ORCAM", "ORCAB",
"SETCM", "SETCMI", "SETCMM", "SETCMB", "ORCM", "ORCMI", "ORCMM", "ORCMB",
"ORCB", "ORCBI", "ORCBM", "ORCBB", "SETO", "SETOI", "SETOM", "SETOB",
"HLL", "HLLI", "HLLM", "HLLS", "HRL", "HRLI", "HRLM", "HRLS",
"HLL", "HLLI", "HLLM", "HLLS", "HRL", "HRLI", "HRLM", "HRLS",
"HLLZ", "HLLZI", "HLLZM", "HLLZS", "HRLZ", "HRLZI", "HRLZM", "HRLZS",
"HLLO", "HLLOI", "HLLOM", "HLLOS", "HRLO", "HRLOI", "HRLOM", "HRLOS",
"HLLE", "HLLEI", "HLLEM", "HLLES", "HRLE", "HRLEI", "HRLEM", "HRLES",
@ -609,7 +609,7 @@ static const t_int64 opc_val[] = {
0230000000000+I_AC, 0231000000000+I_AC, 0232000000000+I_AC, 0233000000000+I_AC,
0234000000000+I_AC, 0235000000000+I_AC, 0236000000000+I_AC, 0237000000000+I_AC,
0240000000000+I_AC, 0241000000000+I_AC, 0242000000000+I_AC, 0243000000000+I_AC,
0244000000000+I_AC, 0245000000000+I_AC, 0246000000000+I_AC,
0244000000000+I_AC, 0245000000000+I_AC, 0246000000000+I_AC,
0250000000000+I_AC, 0251000000000+I_AC, 0252000000000+I_AC, 0253000000000+I_AC,
0254000000000+I_AC, 0255000000000+I_AC, 0256000000000+I_AC, 0257000000000+I_AC,
0260000000000+I_AC, 0261000000000+I_AC, 0262000000000+I_AC, 0263000000000+I_AC,
@ -687,7 +687,7 @@ static const t_int64 opc_val[] = {
0700000000000+I_IO, 0700040000000+I_IO, 0700100000000+I_IO, 0700140000000+I_IO,
0700200000000+I_IO, 0700240000000+I_IO, 0700300000000+I_IO, 0700340000000+I_IO,
-1
};
@ -730,7 +730,7 @@ if (sw & SWMASK ('C')) { /* character? */
for (i = 30; i >= 0; i = i - 6) {
c = (int32) ((inst >> i) & 077);
fprintf (of, "%c", SIXTOASC (c));
}
}
return SCPE_OK;
}
if (sw & SWMASK ('P')) { /* packed? */
@ -801,7 +801,7 @@ const char *tptr;
if (*cptr == '@') {
ind = INST_IND;
cptr++;
}
}
if (*cptr == '+')
cptr++;
else if (*cptr == '-') {