mirror of
https://github.com/rcornwell/sims.git
synced 2026-04-29 13:13:50 +00:00
ICL1900: Updated tape driver to load E4BM.
This commit is contained in:
@@ -1086,9 +1086,11 @@ DISPLAYD = display
|
||||
#
|
||||
# Emulator source files and compile time options
|
||||
#
|
||||
ICL1900D = ./
|
||||
ICL1900 = ${ICL1900D}icl1900_cpu.c ${ICL1900D}icl1900_sys.c ${ICL1900D}icl1900_stdio.c \
|
||||
${ICL1900D}icl1900_cty.c
|
||||
ICL1900D = .
|
||||
ICL1900 = ${ICL1900D}/icl1900_cpu.c ${ICL1900D}/icl1900_sys.c ${ICL1900D}/icl1900_stdio.c \
|
||||
${ICL1900D}/icl1900_cty.c ${ICL1900D}/icl1900_tr.c ${ICL1900D}/icl1900_tp.c \
|
||||
${ICL1900D}/icl1900_mta.c
|
||||
|
||||
ICL1900_OPT = -I.. -DUSE_SIM_CARD
|
||||
|
||||
#
|
||||
|
||||
@@ -441,6 +441,8 @@ sim_instr(void)
|
||||
|
||||
intr:
|
||||
if (!exe_mode && (SR64 | SR65) != 0) {
|
||||
if (CPU_TYPE < TYPE_C1 && !exe_mode)
|
||||
RC += RD;
|
||||
exe_mode = 1;
|
||||
loading = 0;
|
||||
/* Store registers */
|
||||
@@ -2160,38 +2162,46 @@ fexp:
|
||||
case 0172: /* Exit from executive */
|
||||
case 0173: /* Load Datum limit and G */
|
||||
if (exe_mode) {
|
||||
#if 0 /* Type A & B */ /* For non extended address processors. */
|
||||
Mem_read(RB, &RA, 0);
|
||||
RG = RA & 077;
|
||||
RD = RA & 077700;
|
||||
RL = (RA >> 9) & 077700;
|
||||
#else
|
||||
Mem_read(RB, &RA, 0); /* Read datum */
|
||||
RD = RA & (M22 & ~077);
|
||||
RG = (RA & 17) << 3;
|
||||
Mem_read(RB+1, &RA, 0); /* Read Limit */
|
||||
RL = RA & (M22 & ~077);
|
||||
RG |= (RA & 07);
|
||||
Mode = RA & 077;
|
||||
if (CPU_TYPE < TYPE_C1) {
|
||||
/* For non extended address processors. */
|
||||
Mem_read(RB, &RA, 0);
|
||||
RG = RA & 077;
|
||||
RD = RA & 077700;
|
||||
RL = (RA >> 9) & 077700;
|
||||
} else {
|
||||
Mem_read(RB, &RA, 0); /* Read datum */
|
||||
RD = RA & (M22 & ~077);
|
||||
RG = (RA & 17) << 3;
|
||||
Mem_read(RB+1, &RA, 0); /* Read Limit */
|
||||
RL = RA & (M22 & ~077);
|
||||
RG |= (RA & 07);
|
||||
Mode = RA & 077;
|
||||
}
|
||||
adrmask = (Mode & AM22) ? M22 : M15;
|
||||
//fprintf(stderr, "Load C=%08o limit: %08o D:=%08o %02o\n\r", RC, RL, RD, Mode);
|
||||
#endif
|
||||
if (RF & 1) /* Check if 172 or 173 order code */
|
||||
if (RF & 1) /* Check if 172 or 173 order code */
|
||||
break;
|
||||
/* Restore floating point ACC from D12/D13 */
|
||||
for (n = 0; n < 8; n++) /* Restore user mode registers */
|
||||
/* Restore registers */
|
||||
for (n = 0; n < 8; n++) /* Restore user mode registers */
|
||||
Mem_read(RD+n, &XR[n], 0);
|
||||
Mem_read(RD+9, &RA, 0); /* Read ZStatus and mode */
|
||||
Zero = 0;
|
||||
if ((Mode & AM22) && (RA & B3))
|
||||
Zero = 1;
|
||||
Mem_read(RD+9, &RA, 0); /* Read ZStatus and mode */
|
||||
Mem_read(RD+8, &RC, 0); /* Restore C register */
|
||||
//fprintf(stderr, "Load PC: %08o D:=%08o z=%08o\n\r", RC, RD, RA);
|
||||
if ((Mode & AM22) == 0 && (RA & B3))
|
||||
Zero = 1;
|
||||
BV = (RC & B0) != 0;
|
||||
BCarry = (RC & B1) != 0;
|
||||
Zero = 0;
|
||||
/* Type A & B */
|
||||
if (CPU_TYPE < TYPE_C1) {
|
||||
if (RC & B8)
|
||||
Zero = 1;
|
||||
RC &= M15;
|
||||
RC -= RD;
|
||||
} else {
|
||||
if (RA & B3)
|
||||
Zero = 1;
|
||||
}
|
||||
RC &= adrmask;
|
||||
/* Restore floating point ACC from D12/D13 */
|
||||
Mem_read(RD+12, &faccl, 0); /* Restore F.P.U. */
|
||||
Mem_read(RD+13, &facch, 0); /* Restore F.P.U. */
|
||||
exe_mode = 0;
|
||||
@@ -2201,7 +2211,7 @@ fexp:
|
||||
case 0174: /* Send control character to peripheral */
|
||||
if (exe_mode) {
|
||||
chan_send_cmd(RB, RA & 077, &RT);
|
||||
fprintf(stderr, "CMD %04o %04o %08o\n\r", RT, RB, RA);
|
||||
//fprintf(stderr, "CMD %04o %04o %08o\n\r", RT, RB, RA);
|
||||
m = (m == 0) ? 3 : (XR[m] >> 22) & 3;
|
||||
m = 6 * (3 - m);
|
||||
RT = (RT & 077) << m;
|
||||
@@ -2230,6 +2240,8 @@ voluntary:
|
||||
reason = SCPE_STOP;
|
||||
break;
|
||||
}
|
||||
if (CPU_TYPE < TYPE_C1 && !exe_mode)
|
||||
RC += RD;
|
||||
exe_mode = 1;
|
||||
/* Store registers */
|
||||
Mem_write(RD+13, &facch, 0); /* Save F.P.U. */
|
||||
@@ -2245,10 +2257,9 @@ voluntary:
|
||||
RA |= B0;
|
||||
if (BCarry)
|
||||
RA |= B1;
|
||||
#if 0 /* Type A & B */
|
||||
if (Mode & 1)
|
||||
/* Type A & B */
|
||||
if (CPU_TYPE < TYPE_C1 && Zero)
|
||||
RA |= B8;
|
||||
#endif
|
||||
Mem_write(RD+8, &RA, 0);
|
||||
for (n = 0; n < 8; n++)
|
||||
Mem_write(RD+n, &XR[n], 0);
|
||||
|
||||
@@ -88,15 +88,15 @@
|
||||
#define TERMINATE 000000001 /* Transfer complete */
|
||||
#define OPAT 000000002 /* Operator attention */
|
||||
#define PARITY 000000004 /* Parity error */
|
||||
#define SHORT_BLK 000000010 /* Short tape block */
|
||||
#define SHRTBLK 000000010 /* Short tape block */
|
||||
#define ACCEPT 000000020 /* Ready for command */
|
||||
#define BUSY 000000040 /* Device busy */
|
||||
#define CBUSY 000000100 /* Controller Busy */
|
||||
#define WPROT 000001000 /* Write protect */
|
||||
#define EOT 000004000 /* Hit end of tape */
|
||||
#define MARK 000004000 /* Tape Mark sensed */
|
||||
#define OFFLINE 000040000 /* Device offline */
|
||||
#define LONGBLK 000100000 /* Long block */
|
||||
#define MARK 000400000 /* Tape mark sensed */
|
||||
#define EOT 000400000 /* End of Tape sensed */
|
||||
#define DENS 014000000
|
||||
#define CHAR 060000000 /* Count of character read */
|
||||
|
||||
@@ -246,6 +246,7 @@ t_stat mta_svc (UNIT *uptr)
|
||||
uptr->STATUS &= ~BUSY;
|
||||
mta_busy = 0;
|
||||
chan_set_done(dev);
|
||||
return SCPE_OK;
|
||||
}
|
||||
uptr->hwmark = reclen;
|
||||
sim_debug(DEBUG_DETAIL, dptr, "Block %d chars\n", reclen);
|
||||
@@ -291,10 +292,11 @@ t_stat mta_svc (UNIT *uptr)
|
||||
uptr->CMD -= 1 << 16;
|
||||
if ((uptr->CMD & (M15 << 16)) == 0 || uptr->POS >= uptr->hwmark) {
|
||||
/* Done with transfer */
|
||||
sim_debug(DEBUG_DETAIL, dptr, "unit=%d %08o left %08o\n", unit, uptr->ADDR, uptr->CMD >> 16);
|
||||
if ((uptr->CMD & (M15 << 16)) == 0 && uptr->POS < uptr->hwmark)
|
||||
uptr->STATUS |= LONGBLK;
|
||||
uptr->STATUS |= SHRTBLK;
|
||||
if ((uptr->CMD & (M15 << 16)) != 0 && uptr->POS >= uptr->hwmark)
|
||||
uptr->STATUS |= SHORT_BLK;
|
||||
uptr->STATUS |= LONGBLK;
|
||||
uptr->STATUS |= TERMINATE;
|
||||
uptr->STATUS &= ~BUSY;
|
||||
M[64 + dev] = uptr->ADDR; /* Get transfer address */
|
||||
@@ -386,6 +388,7 @@ t_stat mta_svc (UNIT *uptr)
|
||||
uptr->STATUS &= ~BUSY;
|
||||
mta_busy = 0;
|
||||
chan_set_done(dev);
|
||||
return SCPE_OK;
|
||||
}
|
||||
uptr->POS = reclen;
|
||||
uptr->ADDR += uptr->CMD >> 16;
|
||||
@@ -432,11 +435,12 @@ t_stat mta_svc (UNIT *uptr)
|
||||
uptr->ADDR &= M15;
|
||||
uptr->CMD -= 1 << 16;
|
||||
if ((uptr->CMD & (M15 << 16)) == 0 || uptr->POS == 0) {
|
||||
sim_debug(DEBUG_DETAIL, dptr, "unit=%d %08o left %08o\n", unit, uptr->ADDR, uptr->CMD >> 16);
|
||||
/* Done with transfer */
|
||||
if ((uptr->CMD & (M15 << 16)) == 0 && uptr->POS != 0)
|
||||
uptr->STATUS |= LONGBLK;
|
||||
uptr->STATUS |= SHRTBLK;
|
||||
if ((uptr->CMD & (M15 << 16)) != 0 && uptr->POS == 0)
|
||||
uptr->STATUS |= SHORT_BLK;
|
||||
uptr->STATUS |= LONGBLK;
|
||||
uptr->STATUS |= TERMINATE;
|
||||
uptr->STATUS &= ~BUSY;
|
||||
M[64 + dev] = uptr->ADDR; /* Get transfer address */
|
||||
@@ -477,6 +481,7 @@ t_stat mta_svc (UNIT *uptr)
|
||||
break;
|
||||
case 2:
|
||||
uptr->STATUS &= ~BUSY;
|
||||
uptr->STATUS |= TERMINATE;
|
||||
mta_busy = 0;
|
||||
chan_set_done(dev);
|
||||
}
|
||||
@@ -506,6 +511,7 @@ t_stat mta_svc (UNIT *uptr)
|
||||
break;
|
||||
case 2:
|
||||
uptr->STATUS &= ~BUSY;
|
||||
// uptr->STATUS |= TERMINATE|MARK;
|
||||
mta_busy = 0;
|
||||
chan_set_done(dev);
|
||||
}
|
||||
@@ -513,22 +519,23 @@ t_stat mta_svc (UNIT *uptr)
|
||||
|
||||
case MT_WTM:
|
||||
if (uptr->POS == 0) {
|
||||
if (sim_tape_wrp(uptr)) {
|
||||
uptr->STATUS |= WPROT;
|
||||
uptr->STATUS &= ~BUSY;
|
||||
mta_busy = 0;
|
||||
uptr->STATUS &= FMASK;
|
||||
chan_set_done(dev);
|
||||
break;
|
||||
}
|
||||
uptr->POS ++;
|
||||
sim_activate(uptr, 500);
|
||||
if (sim_tape_wrp(uptr)) {
|
||||
uptr->STATUS |= WPROT;
|
||||
uptr->STATUS &= ~BUSY;
|
||||
mta_busy = 0;
|
||||
uptr->STATUS &= FMASK;
|
||||
chan_set_done(dev);
|
||||
break;
|
||||
}
|
||||
uptr->POS ++;
|
||||
sim_activate(uptr, 500);
|
||||
} else {
|
||||
sim_debug(DEBUG_DETAIL, dptr, "Write Mark unit=%d\n", unit);
|
||||
r = sim_tape_wrtmk(uptr);
|
||||
sim_debug(DEBUG_DETAIL, dptr, "Write Mark unit=%d\n", unit);
|
||||
r = sim_tape_wrtmk(uptr);
|
||||
if (r != MTSE_OK)
|
||||
uptr->STATUS |= OPAT;
|
||||
uptr->STATUS |= OPAT;
|
||||
uptr->STATUS &= ~BUSY;
|
||||
uptr->STATUS |= TERMINATE;
|
||||
mta_busy = 0;
|
||||
chan_set_done(dev);
|
||||
}
|
||||
@@ -560,6 +567,7 @@ t_stat mta_svc (UNIT *uptr)
|
||||
break;
|
||||
case 2:
|
||||
uptr->STATUS &= ~BUSY;
|
||||
uptr->STATUS |= TERMINATE|MARK;
|
||||
mta_busy = 0;
|
||||
chan_set_done(dev);
|
||||
}
|
||||
|
||||
@@ -159,12 +159,12 @@ int read_tape(FILE *f, int *len) {
|
||||
sz |= (xlen[3] & 0xff);
|
||||
sz &= 0xffffffff;
|
||||
|
||||
printf("Rec = %d %o\n", sz, sz/3);
|
||||
/* Check for EOF */
|
||||
if (sz == 0xffffffff) {
|
||||
*len = -1;
|
||||
return 1;
|
||||
}
|
||||
fprintf(stderr, "Rec = %d\n", sz);
|
||||
// /* Check for EOF */
|
||||
// if (sz == 0) {
|
||||
// *len = -1;
|
||||
@@ -201,8 +201,8 @@ void write_mark(FILE *f) {
|
||||
if (p7b) {
|
||||
fputc(BCD_TM|TAPE_IRG, f);
|
||||
} else {
|
||||
static uint32 tape_mark = 0;
|
||||
fwrite(&tape_mark, sizeof(uint32), 1, f);
|
||||
static unsigned char xlen[4] = {0, 0, 0, 0};
|
||||
fwrite(&xlen, sizeof(unsigned char), 4, f);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -288,7 +288,10 @@ int main(int argc, char *argv[]) {
|
||||
// putchar(xlat[*p++ & 077]);
|
||||
// putchar('\n');
|
||||
// } else
|
||||
write_block(otape, sz, buffer);
|
||||
for (i = 0; i < sz; i+=3)
|
||||
printf("%08o ", (buffer[i] << 16) | (buffer[i+1] << 8) | buffer[i+2]);
|
||||
printf("\n");
|
||||
write_block(otape, sz, buffer);
|
||||
}
|
||||
}
|
||||
fclose(tape);
|
||||
|
||||
Reference in New Issue
Block a user