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https://github.com/rcornwell/sims.git
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SEL32: Correct status after mt advance record command.
SEL32: Do not clear inch address on controller reset instruction. SEL32: Update mkvmtape processing for MPX3.X SDT tapes. SEL32: Do not reset base mode bit on LPSD(CM) instructions. SEL32: Test for wait mode to inhibit history filling with wait instructions.
This commit is contained in:
AZBevier
parent
3d0410aef9
commit
9cb28572df
@ -246,13 +246,15 @@ t_stat set_inch(UNIT *uptr, uint32 inch_addr) {
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CHANP *pchp = 0; /* for channel prog ptr */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"set_inch chan %04x inch addr %06x\n", chan, inch_addr);
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"set_inch chan %04x inch addr %06x dibp %p\n", chan, inch_addr, dibp);
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/* must be valid DIB pointer */
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if (dibp == NULL)
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return SCPE_MEM; /* return memory error */
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pchp = dibp->chan_prg; /* get parent channel prog ptr */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"set_inch chan %04x inch addr %06x pchp %p\n", chan, inch_addr, pchp);
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/* must be valid channel pointer */
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if (pchp == NULL)
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return SCPE_MEM; /* return memory error */
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@ -268,6 +270,8 @@ t_stat set_inch(UNIT *uptr, uint32 inch_addr) {
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chp++; /* next unit channel */
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}
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sim_debug(DEBUG_XIO, &cpu_dev,
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"set_inch chan %04x inch addr %06x chp %p\n", chan, inch_addr, chp);
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/* now go through all the sub addresses for the channel and set inch addr */
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for (i=0; i<256; i++) {
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chsa = chan | i; /* merge sa to real channel */
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@ -562,7 +566,7 @@ loop:
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chp->chan_caw += 8; /* point to to next IOCD */
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chp->ccw_count = word2 & 0xffff; /* get 16 bit byte count from IOCD WD 2*/
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chp->chan_byte = BUFF_BUSY; /* busy & no bytes transferred yet */
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sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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//sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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chp->ccw_flags = (word2 >> 16) & 0xffff; /* get flags from bits 0-7 of WD 2 of IOCD */
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if (chp->ccw_flags & FLAG_PCI) { /* do we have prog controlled int? */
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chp->chan_status |= STATUS_PCI; /* set PCI flag in status */
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@ -754,7 +758,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte BUFF_CHNEND chp %p chan_byte %04
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if (chp->ccw_flags & FLAG_SKIP) {
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chp->ccw_count--; /* decrement skip count */
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chp->chan_byte = BUFF_BUSY; /* busy, but no data */
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte1 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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//sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte1 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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if ((chp->ccw_cmd & 0xff) == CMD_RDBWD)
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chp->ccw_addr--; /* backward */
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else
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@ -821,7 +825,7 @@ void chan_end(uint16 chsa, uint16 flags) {
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chsa, flags, chp->chan_status, chp->ccw_cmd);
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chp->chan_byte = BUFF_BUSY; /* we are empty & still busy now */
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_end BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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//sim_debug(DEBUG_EXP, &cpu_dev, "chan_end BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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chp->chan_status |= STATUS_CEND; /* set channel end */
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chp->chan_status |= ((uint16)flags); /* add in the callers flags */
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@ -864,7 +868,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "chan_end BUFF_BUSY chp %p chan_byte %04x\n", chp
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/* test for device or controller end */
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if (chp->chan_status & (STATUS_DEND|STATUS_CEND)) {
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chp->chan_byte = BUFF_BUSY; /* we are empty & still busy now */
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_end2 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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//sim_debug(DEBUG_EXP, &cpu_dev, "chan_end2 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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while ((chp->ccw_flags & FLAG_DC)) { /* handle data chaining */
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if (load_ccw(chp, 1)) /* continue channel program */
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break; /* error */
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@ -874,7 +878,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "chan_end2 BUFF_BUSY chp %p chan_byte %04x\n", ch
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}
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}
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chp->chan_byte = BUFF_BUSY; /* we are empty & still busy now */
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_end3 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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//sim_debug(DEBUG_EXP, &cpu_dev, "chan_end3 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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sim_debug(DEBUG_XIO, &cpu_dev,
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"chan_end FIFO #%1x IOCL done chsa %04x ccw_flags %04x status %04x\n",
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FIFO_Num(chsa), chsa, chp->ccw_flags, chp->chan_status);
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@ -1063,6 +1067,10 @@ nothere:
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return SCPE_OK; /* not found, CC3 */
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}
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sim_debug(DEBUG_EXP, &cpu_dev,
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"checkxio chsa %04x flags UNIT_ATTABLE %1x UNIT_ATT %1x\n",
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chsa, (uptr->flags & UNIT_ATTABLE)?1:0, (uptr->flags & UNIT_ATT)?1:0);
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#ifndef TEST_ETHERNET
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/* check for the device being defined and attached in simh */
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if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) {
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sim_debug(DEBUG_EXP, &cpu_dev,
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@ -1070,6 +1078,7 @@ nothere:
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*status = CC3BIT; /* not attached, so error CC3 */
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return SCPE_OK; /* not found, CC3 */
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}
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#endif
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inta = find_int_lev(chsa&0x7f00); /* Interrupt Level for channel */
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chan_icb = find_int_icb(chsa&0x7f00); /* Interrupt level context block address */
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@ -1196,8 +1205,8 @@ t_stat startxio(uint16 chsa, uint32 *status) {
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incha = chp->chan_inch_addr; /* get inch address */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"startxio do normal chsa %04x iocla %06x IOCD1 %08x IOCD2 %08x\n",
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chsa, iocla, RMW(iocla), RMW(iocla+4));
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"startxio do normal chsa %04x iocla %06x incha %06x IOCD1 %08x IOCD2 %08x\n",
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chsa, iocla, incha, RMW(iocla), RMW(iocla+4));
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iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */
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// incha = chp->chan_inch_addr; /* get inch address */
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@ -1309,7 +1318,7 @@ t_stat testxio(uint16 chsa, uint32 *status) { /* test XIO */
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chsa, chp->ccw_cmd, chp->ccw_flags, RMW(iocla), RMW(iocla+4), iocla);
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sim_debug(DEBUG_XIO, &cpu_dev,
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"testxio test2 chsa %04x ICBincha %08x SW1 %08x SW2 %08x\n",
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"testxio test2 chsa %04x ICB incha %08x SW1 %08x SW2 %08x\n",
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chsa, incha, RMW(incha), RMW(incha+4));
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/* the channel is not busy, see if any status to post */
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@ -1547,7 +1556,7 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
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chp->chan_status &= ~STATUS_PCI; /* remove PCI status bit */
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chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */
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chp->chan_byte = BUFF_BUSY; /* wait for post_csw to be done */
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sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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//sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* show I/O complete */
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/* post the channel status */
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@ -1626,7 +1635,9 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
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/* reset the FIFO pointers */
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dibp->chan_fifo_in = 0;
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dibp->chan_fifo_out = 0;
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#ifdef NOT4CONTROLLER
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chp->chan_inch_addr = 0; /* remove inch status buffer address */
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#endif
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lev = find_int_lev(chan); /* get our int level */
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INTS[lev] &= ~INTS_ACT; /* clear level active */
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SPAD[lev+0x80] &= ~SINT_ACT; /* clear spad too */
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@ -1887,7 +1898,9 @@ sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan BUFF_DONE chp %p chan_byte %04x\n", ch
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/* cannot make anyone active if ints are blocked */
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if (CPUSTATUS & 0x80) { /* interrupts blocked? */
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sim_debug(DEBUG_IRQ, &cpu_dev, "scan_chan INTS blocked!\n");
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sim_debug(DEBUG_DETAIL, &cpu_dev,
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// sim_debug(DEBUG_IRQ, &cpu_dev,
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"scan_chan INTS blocked!\n");
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goto tryme; /* needed for MPX */
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//718 return 0; /* yes, done */
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}
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@ -1902,8 +1915,8 @@ sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan BUFF_DONE chp %p chan_byte %04x\n", ch
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if (SPAD[i+0x80] == 0xefffffff) /* not initialize? */
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continue; /* skip this one */
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if ((INTS[i]&INTS_ACT) || (SPAD[i+0x80]&SINT_ACT)) { /* look for level active */
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// sim_debug(DEBUG_DETAIL, &cpu_dev,
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sim_debug(DEBUG_IRQ, &cpu_dev,
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sim_debug(DEBUG_DETAIL, &cpu_dev,
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// sim_debug(DEBUG_IRQ, &cpu_dev,
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"scan_chan INTS ACT irq %02x SPAD %08x INTS %08x\n",
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i, SPAD[i+0x80], INTS[i]);
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return 0; /* this level active, so stop looking */
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@ -2153,28 +2166,36 @@ t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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int i; /* temp */
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int chsa; /* dev addr */
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// fprintf(stderr, "Set dev entry DEVICE ptr %s\r\n", cptr);
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if (cptr == NULL) /* is there a UNIT name specified */
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return SCPE_ARG; /* no, arg error */
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if (uptr == NULL) /* is there a UNIT pointer */
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return SCPE_IERR; /* no, arg error */
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dptr = get_dev(uptr); /* find the device from unit pointer */
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if (dptr == NULL) /* device not found, so error */
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if (dptr == NULL) { /* device not found, so error */
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fprintf(stderr, "Set dev no DEVICE ptr %s\r\n", cptr);
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return SCPE_IERR; /* error */
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}
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dibp = (DIB *)dptr->ctxt; /* get dib pointer from device struct */
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if (dibp == NULL) /* we need a DIB */
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if (dibp == NULL) { /* we need a DIB */
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fprintf(stderr, "Set dev no DIB ptr %s\r\n", GET_UADDR(tuptr->u3), chsa);
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return SCPE_IERR; /* no DIB, so error */
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}
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// fprintf(stderr, "Set dev new addr %s\r\n", cptr);
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chan = get_uint(cptr, 16, 0xffff, &r); /* get new device address */
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if (r != SCPE_OK) /* need good number */
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return r; /* number error, return error */
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chan &= 0x7f00; /* clean channel address */
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dibp->chan_addr = chan; /* set new parent channel addr */
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// fprintf(stderr, "Set dev new addr %s chan %02x\r\n", cptr, chan);
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/* change all the unit addresses with the new channel, but keep sub address */
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/* Clear out existing entries for all units on this device */
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tuptr = dptr->units; /* get pointer to units defined for this device */
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// fprintf(stderr, "Set dev new addr %s chan %02x units %02x\r\n", cptr, chan, dibp->numunits);
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/* loop through all units for this device */
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for (i = 0; i < dibp->numunits; i++) {
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@ -2101,6 +2101,14 @@ wait_loop:
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goto skipi; /* skip int test */
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}
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}
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/* see if in wait instruction */
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if (wait4int) { /* keep waiting */
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/* tell simh we will be waiting */
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// sim_idle(TMR_RTC, 1); /* wait for clock tick */
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sim_idle(0, 1); /* wait for clock tick */
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/*722*/ irq_pend = 1; /* start scanning interrupts again */
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goto wait_loop; /* continue waiting */
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}
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/* Check for external interrupt here */
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/* see if we have an attention request from console */
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@ -5389,6 +5397,14 @@ doovr2:
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PSD2 = (M[(t>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
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M[(t>>2)+4] = IR&0xFFF; /* store call number */
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#ifdef DO_DYNAMIC_DEBUG
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if ((temp2 == 0) && ((IR&0xFFF) == 0xa11))
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/* start debugging */
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cpu_dev.dctrl |= (DEBUG_INST | DEBUG_TRAP | DEBUG_EXP | DEBUG_IRQ);
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#endif
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sim_debug(DEBUG_IRQ, &cpu_dev,
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"SVC #%02x call #%03x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
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temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
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/* set the mode bits and CCs from the new PSD */
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CC = PSD1 & 0x78000000; /* extract bits 1-4 from PSD1 */
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modes = PSD1 & 0x87000000; /* extract bits 0, 5, 6, 7 from PSD 1 */
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@ -5978,6 +5994,7 @@ doovr2:
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TRAPSTATUS |= BIT18; /* set bit 18 of trap status */
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goto newpsd; /* memory read error or map fault */
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}
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//bad /* 723 */ temp &= ~0x02000000; /* reset base reg bit 6 */
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bc = CPUSTATUS; /* save the CPU STATUS */
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TPSD[0] = PSD1; /* save the PSD for the instruction */
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TPSD[1] = PSD2;
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@ -600,7 +600,7 @@ t_stat disk_srv(UNIT *uptr)
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| (buf[i-1]<<8) | (buf[i]);
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}
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}
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/* now call set_inch() function to write and test inch bybber addresses */
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/* now call set_inch() function to write and test inch buffer addresses */
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i = set_inch(uptr, mema); /* new address */
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#ifdef NOTYET
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if ((i == SCPE_MEM) || (i == SCPE_ARG)) { /* any error */
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@ -74,7 +74,7 @@
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#define MT_MDEN_6250 0x02 /* =0 Use mode from bit one for NRZI/PE */
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#define MT_MDEN_6250 0x02 /* =1 6250 BPI GCR mode 9 track only */
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#define MT_MDEN_SCATGR 0x01 /* =1 HSTP scatter/gather mode */
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#define MT_MDEN_MSK 0xc0 /* Density mask */
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#define MT_MDEN_MSK 0x42 /* Density mask */
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#define MT_CTL_MSK 0x38 /* Mask for control flags */
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#define MT_CTL_NOP 0x00 /* Nop control mode */
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@ -510,6 +510,8 @@ t_stat mt_srv(UNIT *uptr)
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{
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uint16 addr = GET_UADDR(uptr->CMD);
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DEVICE *dptr = get_dev(uptr);
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// DIB *dibp = (DIB *)dptr->ctxt; /* get DIB address */
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// CHANP *chp = (CHANP *)dibp->chan_prg; /* get pointer to channel program */
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int unit = (uptr - dptr->units);
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int cmd = uptr->CMD & MT_CMDMSK;
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int bufnum = GET_DEV_BUF(dptr->flags);
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@ -662,7 +664,12 @@ t_stat mt_srv(UNIT *uptr)
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uptr->SNS &= ~(SNS_LOAD|SNS_EOT); /* reset BOT & EOT */
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uptr->POS = 0; /* reset buffer position */
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uptr->hwmark = reclen; /* set buffer chars read in */
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sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv READ fill buffer complete count %04x\n", reclen);
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// sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv READ fill buffer complete count %04x\n", reclen);
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sim_debug(DEBUG_CMD, &mta_dev, "mt_srv READ fill buffer complete count %04x\n", reclen);
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sim_debug(DEBUG_CMD, &mta_dev,
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"mt_srv READ MemBuf %06x cnt %04x %02x%02x%02x%02x\n",
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chp->ccw_addr, chp->ccw_count,
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mt_buffer[0][0], mt_buffer[0][1], mt_buffer[0][2], mt_buffer[0][3]);
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}
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/* get a char from the buffer */
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ch = mt_buffer[bufnum][uptr->POS++];
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@ -710,7 +717,7 @@ t_stat mt_srv(UNIT *uptr)
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reclen = uptr->hwmark; /* set record length */
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ch = mt_buffer[bufnum][0]; /* get the first byte read */
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sim_debug(DEBUG_CMD, &mta_dev,
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"Write mode data done unit %02x chars %04x char %02x\n", unit, reclen, ch);
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"Write mode data done unit %02x chars %02x mode %02x\n", unit, reclen, ch);
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/* put mode bits into byte 2 of SNS */
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uptr->SNS = (uptr->SNS & 0xffff00ff) | (ch << 8);
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uptr->POS = 0; /* no bytes anymore */
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@ -720,7 +727,7 @@ t_stat mt_srv(UNIT *uptr)
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}
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} else {
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mt_buffer[bufnum][uptr->POS++] = ch; /* save the character read in */
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sim_debug(DEBUG_CMD, &mta_dev, "Write mode data in unit %02x POS %04x ch %02x\n",
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sim_debug(DEBUG_CMD, &mta_dev, "Write mode data in unit %02x POS %04x mode %02x\n",
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unit, uptr->POS, ch);
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uptr->hwmark = uptr->POS; /* set high water mark */
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sim_activate(uptr, 40); /* wait time */
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@ -849,10 +856,14 @@ t_stat mt_srv(UNIT *uptr)
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sim_debug(DEBUG_CMD, &mta_dev, "Backspace rec unit %02x POS %04x\n",
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unit, uptr->POS);
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r = sim_tape_sprecr(uptr, &reclen);
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/* We don't set EOF on BSR */
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if (r == MTSE_TMK) {
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/* SEL requires Unit Except & EOF on EOF */
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if (r == MTSE_TMK) { /* test for EOF */
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uptr->POS++;
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sim_debug(DEBUG_CMD, &mta_dev, "MARK\n");
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sim_debug(DEBUG_CMD, &mta_dev, "BSR MARK\n");
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sim_activate(uptr, 50);
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/* SEL requires Unit Except & BOT on BOT */
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} else if (r == MTSE_BOT) {
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uptr->POS+= 2;
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sim_activate(uptr, 50);
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} else {
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sim_debug(DEBUG_CMD, &mta_dev, "Backspace reclen %04x\n", reclen);
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@ -864,9 +875,16 @@ t_stat mt_srv(UNIT *uptr)
|
||||
mt_busy[bufnum] &= ~1;
|
||||
chan_end(addr, SNS_CHNEND|SNS_DEVEND);
|
||||
break;
|
||||
case 3:
|
||||
case 3: /* EOF */
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
mt_busy[bufnum] &= ~1;
|
||||
uptr->SNS |= SNS_FMRKDT; /* file mark detected */
|
||||
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
|
||||
break;
|
||||
case 4: /* BOT */
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
mt_busy[bufnum] &= ~1;
|
||||
uptr->SNS |= SNS_LOAD; /* set BOT detected */
|
||||
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
|
||||
break;
|
||||
}
|
||||
@ -887,10 +905,11 @@ t_stat mt_srv(UNIT *uptr)
|
||||
break;
|
||||
case 1:
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "Backspace file unit=%02x\n", unit);
|
||||
uptr->SNS &= ~(SNS_LOAD|SNS_EOT|SNS_FMRKDT); /* reset BOT, EOT, EOF */
|
||||
r = sim_tape_sprecr(uptr, &reclen);
|
||||
if (r == MTSE_TMK) {
|
||||
uptr->POS++;
|
||||
sim_debug(DEBUG_DETAIL, &mta_dev, "MARK\n");
|
||||
sim_debug(DEBUG_DETAIL, &mta_dev, "BSF MARK\n");
|
||||
sim_activate(uptr, 50);
|
||||
} else if (r == MTSE_BOT) {
|
||||
uptr->POS+= 2;
|
||||
@ -901,12 +920,14 @@ t_stat mt_srv(UNIT *uptr)
|
||||
break;
|
||||
case 2: /* File Mark */
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
uptr->SNS |= SNS_FMRKDT; /* file mark detected */
|
||||
mt_busy[bufnum] &= ~1;
|
||||
chan_end(addr, SNS_DEVEND);
|
||||
break;
|
||||
case 3: /* BOT */
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
mt_busy[bufnum] &= ~1;
|
||||
uptr->SNS |= SNS_LOAD; /* set BOT */
|
||||
chan_end(addr, SNS_DEVEND);
|
||||
break;
|
||||
}
|
||||
@ -922,6 +943,7 @@ t_stat mt_srv(UNIT *uptr)
|
||||
case 1:
|
||||
uptr->POS++;
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "Skip rec unit=%02x ", unit);
|
||||
uptr->SNS &= ~(SNS_LOAD|SNS_EOT|SNS_FMRKDT); /* reset BOT, EOT, EOF */
|
||||
r = sim_tape_sprecf(uptr, &reclen);
|
||||
if (r == MTSE_TMK) {
|
||||
uptr->POS = 3;
|
||||
@ -931,6 +953,7 @@ t_stat mt_srv(UNIT *uptr)
|
||||
} else if (r == MTSE_EOM) {
|
||||
uptr->POS = 4;
|
||||
uptr->SNS |= SNS_EOT; /* set EOT status */
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "FSR EOT\n");
|
||||
sim_activate(uptr, 50);
|
||||
} else {
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "FSR skipped %04x byte record\n",
|
||||
@ -947,13 +970,13 @@ t_stat mt_srv(UNIT *uptr)
|
||||
case 3:
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
mt_busy[bufnum] &= ~1;
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "Skip record at EOF\n");
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "Skip record now at EOF\n");
|
||||
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
|
||||
break;
|
||||
case 4:
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
mt_busy[bufnum] &= ~1;
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "Skip record at EOT\n");
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "Skip record now at EOT\n");
|
||||
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
|
||||
break;
|
||||
}
|
||||
@ -969,6 +992,7 @@ t_stat mt_srv(UNIT *uptr)
|
||||
break;
|
||||
case 1:
|
||||
sim_debug(DEBUG_CMD, &mta_dev, "Skip file unit=%02x\n", unit);
|
||||
uptr->SNS &= ~(SNS_LOAD|SNS_EOT|SNS_FMRKDT); /* reset BOT, EOT, EOF */
|
||||
r = sim_tape_sprecf(uptr, &reclen);
|
||||
if (r == MTSE_TMK) {
|
||||
uptr->POS++;
|
||||
@ -988,14 +1012,12 @@ t_stat mt_srv(UNIT *uptr)
|
||||
case 2:
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
mt_busy[bufnum] &= ~1;
|
||||
uptr->SNS &= ~SNS_LOAD; /* reset BOT */
|
||||
sim_debug(DEBUG_CMD, &mta_dev,
|
||||
"Skip file done sense %08x unit %02x\n", uptr->SNS, unit);
|
||||
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
|
||||
break;
|
||||
case 3:
|
||||
uptr->CMD &= ~(MT_CMDMSK);
|
||||
uptr->SNS &= ~SNS_LOAD; /* reset BOT */
|
||||
uptr->SNS |= SNS_EOT; /* set EOT status */
|
||||
mt_busy[bufnum] &= ~1;
|
||||
sim_debug(DEBUG_CMD, &mta_dev,
|
||||
|
||||
@ -33,14 +33,14 @@
|
||||
/* memory access macros */
|
||||
/* The RMW and WMW macros are used to read/write memory words */
|
||||
/* RMW(addr) or WMW(addr, data) where addr is a byte alligned word address */
|
||||
#define RMB(a) ((M[(a)>>2]>>(8*(7-(a&3))))&0xff) /* read memory addressed byte */
|
||||
#define RMB(a) ((M[(a)>>2]>>(8*(3-(a&3))))&0xff) /* read memory addressed byte */
|
||||
#define RMH(a) ((a)&2?(M[(a)>>2]&RMASK):(M[(a)>>2]>>16)&RMASK) /* read memory addressed halfword */
|
||||
#define RMW(a) (M[((a)&MASK24)>>2]) /* read memory addressed word */
|
||||
#define WMW(a,d) (M[((a)&MASK24)>>2]=d) /* write memory addressed word */
|
||||
/* write halfword to memory address */
|
||||
#define WMH(a,d) ((a)&2?(M[(a)>>2]=(M[(a)>>2]&LMASK)|((d)&RMASK)):(M[(a)>>2]=(M[(a)>>2]&RMASK)|((d)<<16)))
|
||||
/* write byte to memory */
|
||||
#define WMB(a,d) (M[(a)>>2]=(((M[(a)>>2])&(~(0xff<<(8*(7-(a&3))))))|((d&0xff)<<(8*(7-(a&3))))))
|
||||
#define WMB(a,d) (M[(a)>>2]=(((M[(a)>>2])&(~(0xff<<(8*(3-(a&3))))))|((d&0xff)<<(8*(3-(a&3))))))
|
||||
|
||||
#define BLKSIZE 768 /* MPX file sector size */
|
||||
u_int32_t dir[32]; /* directory name */
|
||||
@ -258,7 +258,7 @@ char *argv[];
|
||||
break;
|
||||
case 'A':
|
||||
case 'a':
|
||||
if (option & DOBOOT) { /* error if boor specified with append command */
|
||||
if (option & DOBOOT) { /* error if boot specified with append command */
|
||||
fprintf(stderr, "Error: -a cannot be specified with -b option\n");
|
||||
goto error1; /* we are done here */
|
||||
}
|
||||
@ -424,7 +424,7 @@ getout:
|
||||
if (option & DOBOOT) {
|
||||
int32_t w2, n1, n2, nw, hc, blks;
|
||||
fnp = bootp; /* get file name pointer */
|
||||
#ifdef USE_FILENAME
|
||||
#ifndef USE_FILENAME
|
||||
memset((char *)data, 0, 0x800); /* zero data storage */
|
||||
if ((fp = fopen(bootp, "r")) == NULL) {
|
||||
fprintf(stderr, "error: can't open boot file %s\n", bootp);
|
||||
@ -442,7 +442,8 @@ printf("bootfile %s is %x (%d) bytes\n", bootp, word, word);
|
||||
w2 = fread((char *)data, 1, word, fp); /* read the boot file */
|
||||
#else
|
||||
/* go cut the boot code from the volmgr load module */
|
||||
w2 = readboot("volmgr", (char *)data, 0x1c9a0, 0x1d144);
|
||||
// w2 = readboot("volmgr", (char *)data, 0x1c9a0, 0x1d144);
|
||||
w2 = readboot("volmgr", (char *)data, 0x1c9a0, 0x1d140);
|
||||
#endif
|
||||
/* we have data to write */
|
||||
hc = (w2 + 1) & ~1; /* make byte count even */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user