mirror of
https://github.com/rcornwell/sims.git
synced 2026-03-01 09:31:07 +00:00
IBM360: Checking for MVC and friends, 64Bit MXR.
This commit is contained in:
Richard Cornwell
@@ -980,6 +980,7 @@ sim_instr(void)
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t_uint64 src1L;
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t_uint64 src2L;
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t_uint64 destL;
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t_uint64 dest2L;
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#endif
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uint16 ops[3];
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//double a, b, c;
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@@ -2057,6 +2058,22 @@ save_dbl:
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case OP_LM:
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reg &= 0xf;
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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temp = reg1;
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/* Find last location. */
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addr2 = addr1;
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for (;;) {
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if (temp == reg)
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break;
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temp++;
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temp &= 0xf;
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addr2 += 4;
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}
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/* If we can acces this, we will fault on first */
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if (TransAddr(addr2, &src1))
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goto supress;
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}
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for (;;) {
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if (ReadFull(addr1, ®s[reg1]))
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goto supress;
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@@ -2270,6 +2287,17 @@ save_dbl:
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case OP_MVN:
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case OP_MVZ:
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case OP_MVC:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr1+reg, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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if (TransAddr(addr2+reg, &src1))
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goto supress;
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}
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do {
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if (ReadByte(addr2, &src1))
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break;
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@@ -2296,6 +2324,17 @@ save_dbl:
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case OP_CLC:
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cc = 0;
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr1+reg, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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if (TransAddr(addr2+reg, &src1))
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goto supress;
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}
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do {
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if (ReadByte(addr1, &src1))
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break;
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@@ -2313,6 +2352,17 @@ save_dbl:
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break;
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case OP_TR:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr1+reg, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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if (TransAddr(addr2+256, &src1))
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goto supress;
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}
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do {
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if (ReadByte(addr1, &src1))
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break;
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@@ -2327,6 +2377,17 @@ save_dbl:
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case OP_TRT:
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cc = 0;
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr1+reg, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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if (TransAddr(addr2+256, &src1))
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goto supress;
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}
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do {
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if (ReadByte(addr1, &src1))
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break;
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@@ -2347,6 +2408,13 @@ save_dbl:
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break;
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case OP_PACK:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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}
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reg &= 0xf;
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addr2 += reg;
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addr1 += reg1;
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@@ -2387,6 +2455,13 @@ save_dbl:
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break;
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case OP_UNPK:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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}
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reg &= 0xf;
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addr2 += reg;
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addr1 += reg1;
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@@ -2426,6 +2501,13 @@ save_dbl:
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/* Move with offset, packed odd shift */
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case OP_MVO:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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}
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reg &= 0xf;
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addr2 += reg;
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addr1 += reg1;
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@@ -3151,7 +3233,7 @@ save_dbl:
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goto supress;
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cc = 0;
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} else {
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regs[reg1] = dest;
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regs[reg1] = src2;
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per_mod |= 1 << reg1;
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cc = 1;
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}
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@@ -3179,8 +3261,8 @@ save_dbl:
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goto supress;
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cc = 0;
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} else {
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regs[reg1] = dest;
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regs[reg1|1] = desth;
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regs[reg1] = src2;
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regs[reg1|1] = src2h;
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per_mod |= 3 << reg1;
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cc = 1;
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}
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@@ -5082,11 +5164,119 @@ fpnorm:
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storepsw(OPPSW, IRC_OPR);
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goto supress;
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}
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if ((reg & 0xBB) != 0) {
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if ((reg1 & 0xBB) != 0) {
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storepsw(OPPSW, IRC_SPEC);
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goto supress;
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}
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//fprintf(stderr, "FP * DP \n\r");
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// a = cnvt_float(src1, src1h);
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// b = cnvt_float(src2, src2h);
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//fprintf(stderr, "FP * Op=%0x src1=%08x %08x, src2=%08x %08x %.12e %.12e %.12e\n\r", op, src1, src1h, src2, src2h, a, b, a*b);
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/* Extract numbers and adjust */
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e1 = (src1 & EMASK) >> 24;
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e2 = (src2 & EMASK) >> 24;
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fill = 0;
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if ((src1 & MSIGN) != (src2 & MSIGN))
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fill = 1;
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src1 &= MMASK;
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#ifdef USE_64BIT
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src1L = (((t_uint64)(src1)) << 36) | (((t_uint64)fpregs[reg1|1]) << 4);
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src2L = (((t_uint64)(fpregs[reg1|2] & MMASK) << 36)) |
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(((t_uint64)fpregs[reg1|3]) << 4);
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/* Normalize first operand */
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if (src1L != 0) {
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while ((src1L & NMASKL) == 0) {
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src1L <<= 4;
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src1L |= (src2L >> 56) & 0xf0;
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src2L <<= 4;
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e1 --;
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}
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}
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src1L &= UMASKL;
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src2L &= UMASKL;
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/* Normalize second operand. */
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fpregs[reg1|3] = fpregs[reg|3];
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fpregs[reg1|2] = (fpregs[reg|2] & MMASK) | ((fpregs[reg|1] & 0xff) << 24);
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fpregs[reg1|1] = (fpregs[reg|1] >> 8) | ((fpregs[reg] & 0xff) << 24);
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fpregs[reg1] = (fpregs[reg] & MMASK) >> 8;
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/* Save second operand in result */
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temp = fpregs[reg1] | fpregs[reg1|1] | fpregs[reg1|2] | fpregs[reg1|3];
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if (temp != 0) {
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while ((fpregs[reg1] & 0x00f000) == 0) {
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fpregs[reg1] = (fpregs[reg1] << 4) | ((fpregs[reg1|1] >> 28) & 0xf);
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fpregs[reg1|1] = (fpregs[reg1|1] << 4) | ((fpregs[reg1|2] >> 28) & 0xf);
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fpregs[reg1|2] = (fpregs[reg1|2] << 4) | ((fpregs[reg1|3] >> 28) & 0xf);
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fpregs[reg1|3] <<= 4;
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e2 --;
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}
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}
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/* Compute exponent */
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e1 = e1 + e2 - 64;
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/* Do multiply */
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destL = 0;
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dest2L = 0;
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for (temp = 0; temp < 112; temp++) {
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//fprintf(stderr, "FP *s src1=%016llx, src2=%016llx dest=%016llx %d\n\r", src1L, src2L, destL, temp);
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/* Add if we need too */
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if (fpregs[reg1|3] & 1) {
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destL += src1L;
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dest2L += src2L;
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if (dest2L & CMASKL)
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destL += 0x10;
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dest2L &= UMASKL;
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}
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/* Shift right by one */
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dest2L >>= 1;
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destL >>= 1;
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if (destL & 0x8) {
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dest2L |= 0x0800000000000000LL;
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}
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fpregs[reg1|3] >>= 1;
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if (fpregs[reg1|2] & 1)
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fpregs[reg1|3] |= MSIGN;
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fpregs[reg1|2] >>= 1;
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if (fpregs[reg1|1] & 1)
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fpregs[reg1|2] |= MSIGN;
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fpregs[reg1|1] >>= 1;
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if (fpregs[reg1] & 1)
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fpregs[reg1|1] |= MSIGN;
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}
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//fprintf(stderr, "FP *r res=%016llx %x\n\r", destL, e1);
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/* If overflow, shift right 4 bits */
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if (destL & EMASKL) {
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src1L >>= 4;
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src1L |= (destL & 0xF) << 60;
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destL >>= 4;
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e1 ++;
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if (e1 >= 128) {
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storepsw(OPPSW, IRC_EXPOVR);
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//fprintf(stderr, "FP ov\n\r");
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}
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}
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//fprintf(stderr, "FP *f res=%016llx %x\n\r", destL, e1);
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dest = (uint32)((dest2L >> 36) & MMASK);
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desth = (uint32)((dest2L >> 4) & FMASK);
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src1 = (uint32)((destL >> 36) & MMASK);
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src1h = (uint32)((destL >> 4) & MMASK);
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#else
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#endif
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if (e1) {
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dest |= (e1 << 24) & EMASK;
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src1 |= ((e1 - 14) << 24) & EMASK;
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if (fill) {
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dest |= MSIGN;
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src1 |= MSIGN;
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}
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}
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fpregs[reg1|3] = src1h;
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fpregs[reg1|2] = src1;
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fpregs[reg1|1] = desth;
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fpregs[reg1] = dest;
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//fprintf(stderr, "FP * res=%08x %08x %d %.12e\n\r", dest, desth, cc, cnvt_float(dest,desth));
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break;
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default: /* Unknown op code */
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@@ -571,6 +571,7 @@ if (sw & SWMASK ('C')) {
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sval[l++] = num;
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fprint_val(of, num, 16, 16, PV_RZRO);
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fputc(' ', of);
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l = i;
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for(; i < 6; i+=2)
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fputs(" ", of);
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fputc(' ', of);
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