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ICL1900: Minor changes to make card reader and line printer work.

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This commit is contained in:
Richard Cornwell 2018-09-11 00:18:16 -04:00
parent 688fb9b86c
commit ad61bbcf45
10 changed files with 206 additions and 46 deletions
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7
ICL1900/icl1900_cp.c
View File

@ -32,7 +32,7 @@
#define NUM_DEVS_CDP 0
#endif
#define UNIT_V_TYPE (UNIT_V_UF + 0)
#define UNIT_V_TYPE (UNIT_V_UF + 8)
#define UNIT_TYPE (0xf << UNIT_V_TYPE)
#define GET_TYPE(x) ((UNIT_TYPE & (x)) >> UNIT_V_TYPE)
#define SET_TYPE(x) (UNIT_TYPE & ((x) << UNIT_V_TYPE))
@ -56,7 +56,8 @@
#define T1920_1 0
#define T1920_2 1
#define UNIT_CDP(x) UNIT_ADDR(x)|SET_TYPE(T1920_2)|UNIT_ATTABLE|UNIT_DISABLE
#define UNIT_CDP(x) UNIT_ADDR(x)|SET_TYPE(T1920_2)|UNIT_ATTABLE|UNIT_DISABLE| \
MODE_029
void cdp_cmd (int dev, uint32 cmd, uint32 *resp);
@ -264,7 +265,7 @@ t_stat cdp_svc (UNIT *uptr)
if (eor) {
break;
}
image[i] = sim_bcd_to_hol(ch);
image[i] = mem_to_hol[ch];
}
switch(sim_punch_card(uptr, image)) {
case CDSE_EMPTY:

8
ICL1900/icl1900_cpu.c
View File

@ -454,7 +454,7 @@ intr:
RA = 0; /* Build ZSTAT */
if (cpu_flags & SV) {
Mem_read(RD+9, &RA, 0);
RA &= 077777;
RA &= M15;
RA |= ((Mode|DATUM) << 16);
if (Mode & DATUM)
RA |= 1 << 16;
@ -463,7 +463,7 @@ intr:
} else {
if (CPU_TYPE >= TYPE_C1) {
Mem_read(RD+9, &RA, 0);
RA &= 077777;
RA &= M15;
if (Zero)
RA |= B3;
if (OPIP | PIP)
@ -2234,7 +2234,7 @@ fexp:
case 0174: /* Send control character to peripheral */
if (exe_mode) {
chan_send_cmd(RB, RA & 07777, &RT);
//fprintf(stderr, "CMD C=%08o %04o %04o %08o\n\r", RC, RT, RB, RA);
fprintf(stderr, "CMD C=%08o %04o %04o %08o\n\r", RC, RT, RB, RA);
m = (m == 0) ? 3 : (XR[m] >> 22) & 3;
m = 6 * (3 - m);
RT = (RT & 077) << m;
@ -2276,7 +2276,7 @@ voluntary:
Mem_write(RD+12, &faccl, 0);
if (CPU_TYPE >= TYPE_C1) {
Mem_read(RD+9, &RA, 0);
RA &= 077777;
RA &= M15;
/* Build ZSTAT and ASTAT */
if (Zero)
RA |= B3;

81
ICL1900/icl1900_cr.c
View File

@ -32,7 +32,7 @@
#define NUM_DEVS_CDR 0
#endif
#define UNIT_V_TYPE (UNIT_V_UF + 0)
#define UNIT_V_TYPE (UNIT_V_UF + 8)
#define UNIT_TYPE (0xf << UNIT_V_TYPE)
#define GET_TYPE(x) ((UNIT_TYPE & (x)) >> UNIT_V_TYPE)
#define SET_TYPE(x) (UNIT_TYPE & ((x) << UNIT_V_TYPE))
@ -45,12 +45,12 @@
#define TERMINATE 0000001
#define STOPPED 0000060
#define STOPPED 0000030
#define OPAT 0000002
#define ERROR 0000004
#define IMAGE 0000010
#define DISC 0010
#define BUSY 0020
#define DISC 0040
#if (NUM_DEVS_CDR > 0)
@ -61,7 +61,7 @@
#define T1912_2 3
#define UNIT_CDR(x) UNIT_ADDR(x)|SET_TYPE(T1912_2)|UNIT_ATTABLE|\
UNIT_DISABLE|UNIT_RO
UNIT_DISABLE|UNIT_RO|MODE_029
void cdr_cmd (int dev, uint32 cmd, uint32 *resp);
@ -69,6 +69,9 @@ void cdr_nsi_cmd (int dev, uint32 cmd);
void cdr_nsi_status (int dev, uint32 *resp);
t_stat cdr_svc (UNIT *uptr);
t_stat cdr_boot (int32 unit_num, DEVICE * dptr);
t_stat cdr_reset (DEVICE *dptr);
t_stat cdr_attach(UNIT * uptr, CONST char *file);
t_stat cdr_detach(UNIT * uptr);
t_stat cdr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
CONST char *cdr_description (DEVICE *dptr);
@ -94,8 +97,8 @@ MTAB cdr_mod[] = {
DEVICE cdr_dev = {
"CR", cdr_unit, NULL, cdr_mod,
NUM_DEVS_CDR, 8, 22, 1, 8, 22,
NULL, NULL, NULL, &cdr_boot, &sim_card_attach, &sim_card_detach,
&cdr_dib, DEV_DISABLE | DEV_CARD | DEV_DEBUG, 0, dev_debug,
NULL, NULL, &cdr_reset, &cdr_boot, &cdr_attach, &cdr_detach,
&cdr_dib, DEV_DISABLE | DEV_CARD | DEV_DEBUG, 0, card_debug,
NULL, NULL, &cdr_help, NULL, NULL, &cdr_description
};
@ -134,17 +137,20 @@ void cdr_cmd(int dev, uint32 cmd, uint32 *resp) {
if ((uptr->flags & UNIT_ATT) == 0)
return;
if (cmd == 020) { /* Send Q */
*resp = uptr->STATUS & 01; /* Terminate */
if ((uptr->flags & UNIT_ATT) != 0 || uptr->STATUS & 07700)
*resp = uptr->STATUS & TERMINATE; /* Terminate */
if ((uptr->flags & UNIT_ATT) != 0 || uptr->STATUS & 016)
*resp |= 040;
if ((uptr->STATUS & BUSY) == 0)
*resp |= STOPPED;
sim_debug(DEBUG_STATUS, &cdr_dev, "STATUS: %02o %02o\n", cmd, *resp);
uptr->STATUS &= ~TERMINATE;
chan_clr_done(dev);
} else if (cmd == 024) { /* Send P */
*resp = uptr->STATUS & 016; /* IMAGE, ERROR, OPAT */
if ((uptr->flags & UNIT_ATT) != 0)
*resp |= 1;
uptr->STATUS &= (IMAGE|BUSY|DISC);
chan_clr_done(dev);
sim_debug(DEBUG_STATUS, &cdr_dev, "STATUS: %02o %02o\n", cmd, *resp);
} else if (cmd == 031 || cmd == 033 || cmd == 037 ) {
if ((uptr->flags & UNIT_ATT) == 0)
return;
@ -152,15 +158,16 @@ void cdr_cmd(int dev, uint32 cmd, uint32 *resp) {
*resp = 3;
return;
}
sim_debug(DEBUG_CMD, &cdr_dev, "CMD: %02o %08o\n", cmd, uptr->STATUS);
uptr->STATUS = BUSY;
uptr->STATUS = BUSY;
if (cmd & 02)
uptr->STATUS |= IMAGE;
sim_activate(uptr, uptr->wait);
chan_clr_done(dev);
sim_debug(DEBUG_CMD, &cdr_dev, "CMD: %02o %08o\n", cmd, uptr->STATUS);
*resp = 5;
} else if (cmd == 036) { /* Disconnect */
uptr->STATUS |= DISC;
sim_debug(DEBUG_CMD, &cdr_dev, "CMD: %02o %08o\n", cmd, uptr->STATUS);
*resp = 5;
}
}
@ -195,6 +202,7 @@ void cdr_nsi_cmd(int dev, uint32 cmd) {
if (cmd & 02) {
if (uptr->STATUS & BUSY)
uptr->STATUS |= DISC;
sim_debug(DEBUG_CMD, &cdr_dev, "STOP: %02o %08o\n", cmd, uptr->STATUS);
return;
}
@ -207,6 +215,7 @@ void cdr_nsi_cmd(int dev, uint32 cmd) {
uptr->STATUS = BUSY;
sim_activate(uptr, uptr->wait);
chan_clr_done(dev);
sim_debug(DEBUG_CMD, &cdr_dev, "START: %02o %08o\n", cmd, uptr->STATUS);
}
}
@ -245,8 +254,10 @@ void cdr_nsi_status(int dev, uint32 *resp) {
*resp |= 040;
uptr->STATUS &= BUSY|DISC|IMAGE;
chan_clr_done(dev);
sim_debug(DEBUG_STATUS, &cdr_dev, "STATUS: %02o\n", *resp);
}
t_stat cdr_svc (UNIT *uptr)
{
uint16 image[80];
@ -266,13 +277,19 @@ t_stat cdr_svc (UNIT *uptr)
if ((uptr->STATUS & BUSY) == 0)
return SCPE_OK;
switch(sim_read_card(uptr, image)) {
switch(i = sim_read_card(uptr, image)) {
default:
case CDSE_EMPTY:
case CDSE_EOF:
sim_card_detach(uptr);
sim_debug(DEBUG_DATA, &cdr_dev, "EOF: %d\n", i);
break;
case CDSE_ERROR:
uptr->STATUS |= OPAT;
sim_debug(DEBUG_DATA, &cdr_dev, "Error: %d\n", i);
break;
case CDSE_OK:
sim_debug(DEBUG_DATA, &cdr_dev, "ok: %d\n", i);
for (i = 0; i < 80; i++) {
if (uptr->STATUS & IMAGE) {
ch = (image[i] >> 6) & 077;
@ -281,12 +298,14 @@ t_stat cdr_svc (UNIT *uptr)
break;
ch = image[i] & 077;
} else {
ch = sim_hol_to_bcd(image[i]);
if (ch == 0x7f) {
ch = hol_to_mem[image[i]];
sim_debug(DEBUG_DATA, &cdr_dev, "col: %04x %02o '%c'\n", image[i], ch, mem_to_ascii[ch]);
if (ch == 0xff) {
uptr->STATUS |= ERROR;
break;
}
}
sim_debug(DEBUG_DATA, &cdr_dev, "DATA: %03o\n", ch);
eor = chan_input_char(dev, &ch, 0);
if (eor)
break;
@ -300,6 +319,21 @@ t_stat cdr_svc (UNIT *uptr)
return SCPE_OK;
}
t_stat
cdr_reset(DEVICE *dptr)
{
int i;
memset(&hol_to_mem[0], 0xff, 4096);
for(i = 0; i < (sizeof(mem_to_hol)/sizeof(uint16)); i++) {
uint16 temp;
temp = mem_to_hol[i];
hol_to_mem[temp] = i;
}
return SCPE_OK;
}
/* Boot from given device */
t_stat
cdr_boot(int32 unit_num, DEVICE * dptr)
@ -319,6 +353,25 @@ cdr_boot(int32 unit_num, DEVICE * dptr)
return SCPE_OK;
}
t_stat
cdr_attach(UNIT * uptr, CONST char *file)
{
t_stat r;
if ((r = sim_card_attach(uptr, file)) != SCPE_OK)
return r;
uptr->STATUS = 0;
chan_set_done(GET_UADDR(uptr->flags));
return SCPE_OK;
}
t_stat
cdr_detach(UNIT * uptr)
{
return sim_card_detach(uptr);
}
t_stat cdr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{

4
ICL1900/icl1900_defs.h
View File

@ -59,6 +59,10 @@ extern uint32 XR[8];
#define DEBUG_STATUS 0x0000040 /* Show status conditions */
extern DEBTAB dev_debug[];
extern DEBTAB card_debug[];
extern uint8 hol_to_mem[4096];
extern uint8 mem_to_ascii[64];
extern uint16 mem_to_hol[64];
extern uint32 SR64;
extern uint32 SR65;

22
ICL1900/icl1900_eds8.c
View File

@ -84,7 +84,6 @@
#define EDS8_ERR 004000 /* Hard error */
#define EDS8_PATH 010000 /* Wrong track */
#define EDS8_LONG 020000 /* Reached end of cylinder during read/write */
#define EDS8_IRQ 040000 /* Drive changed status */
#define ST1_OK 001 /* Unit available */
#define ST1_ERR 002 /* Hard error */
@ -151,6 +150,7 @@ void eds8_cmd(int dev, uint32 cmd, uint32 *resp) {
*resp = 5;
return;
}
cmd &= ~02000;
switch(cmd & 070) {
case 000: if (cmd == 7)
cmd |= EDS8_QUAL1|EDS8_QUAL2;
@ -186,7 +186,10 @@ void eds8_cmd(int dev, uint32 cmd, uint32 *resp) {
}
sim_debug(DEBUG_STATUS, &eds8_dev, "Status: unit:=%d %02o %02o\n", eds8_drive, cmd, *resp);
return;
case 030: if (cmd < 036)
case 030:
sim_debug(DEBUG_CMD, &eds8_dev, "Cmd: unit=%d %02o\n", eds8_drive, cmd);
cmd &= 077;
if (cmd < 036)
cmd |= EDS8_QUAL1|EDS8_QUAL2;
break;
case 040:
@ -198,7 +201,9 @@ void eds8_cmd(int dev, uint32 cmd, uint32 *resp) {
uptr->CMD |= ((cmd & 017) << 16);
uptr->CMD &= ~EDS8_QUAL2;
}
sim_debug(DEBUG_STATUS, &eds8_dev, "Qual: unit:=%d %02o %02o\n", eds8_drive, cmd, *resp);
cmd = uptr->CMD;
*resp = 5;
break;
default:
*resp = 3;
@ -248,6 +253,7 @@ t_stat eds8_svc (UNIT *uptr)
/* If we need to seek, move heads. */
if (uptr->CMD & EDS8_SK) {
int diff;
sim_debug(DEBUG_DETAIL, &eds8_dev, "Seek: unit:=%d %d %d\n", unit, uptr->CYL, (uptr->CMD >> 16) & 0377);
diff = uptr->CYL - ((uptr->CMD >> 16) & 0377);
i = 1;
if (diff < 0) {
@ -298,16 +304,18 @@ t_stat eds8_svc (UNIT *uptr)
/* Set desired cylinder to value */
if ((uptr->CMD & EDS8_RUN) == 0) {
int trk = (uptr->CMD >> 16) & 0377;
sim_debug(DEBUG_DETAIL, &eds8_dev, "Seek: start unit:=%d %d %d\n", unit, uptr->CYL, trk);
if (uptr->CYL == trk) {
/* Terminate */
uptr->CMD &= ~(EDS8_RUN|EDS8_SK|EDS8_BUSY);
uptr->CMD |= EDS8_TERM|EDS8_IRQ;
uptr->CMD |= EDS8_TERM;
} else if (trk > CYLS) {
/* Terminate with error */
uptr->CMD &= ~(EDS8_RUN|EDS8_SK|EDS8_BUSY);
uptr->CMD |= EDS8_TERM|EDS8_PATH;
uptr->CMD |= EDS8_TERM;
} else {
uptr->CMD |= EDS8_RUN|EDS8_SK;
uptr->CMD |= EDS8_RUN|EDS8_SK|EDS8_TERM;
sim_activate(uptr, 500);
}
eds8_busy = 0;
/* trigger controller available */
@ -317,7 +325,7 @@ t_stat eds8_svc (UNIT *uptr)
if (uptr->CYL == ((uptr->CMD >> 16) & 0377)) {
/* Terminate */
uptr->CMD &= ~(EDS8_RUN|EDS8_SK|EDS8_BUSY);
uptr->CMD |= EDS8_TERM|EDS8_IRQ;
uptr->CMD |= EDS8_TERM;
chan_set_done(dev);
}
break;
@ -617,7 +625,7 @@ eds8_attach(UNIT * uptr, CONST char *file)
if ((r = attach_unit(uptr, file)) != SCPE_OK)
return r;
uptr->CYL = 0;
uptr->CMD = EDS8_TERM|EDS8_IRQ;
uptr->CMD = EDS8_TERM;
chan_set_done(GET_UADDR(eds8_dev.flags));
}

32
ICL1900/icl1900_lp.c
View File

@ -31,7 +31,7 @@
#define NUM_DEVS_LPR 0
#endif
#define UNIT_V_TYPE (UNIT_V_UF + 1)
#define UNIT_V_TYPE (UNIT_V_UF + 0)
#define UNIT_TYPE (0x1f << UNIT_V_TYPE)
#define GET_TYPE(x) ((UNIT_TYPE & (x)) >> UNIT_V_TYPE)
#define SET_TYPE(x) (UNIT_TYPE & ((x) << UNIT_V_TYPE))
@ -48,6 +48,7 @@
#define AUTO 00100
#define PRINT 00040
#define QUAL 00020
#define SPACE 00010
#define TERMINATE 0001
@ -83,8 +84,8 @@ CONST char *lpr_description (DEVICE *dptr);
DIB lpr_dib = { CHAR_DEV, &lpr_cmd, &lpr_nsi_cmd, &lpr_nsi_status };
UNIT lpr_unit[] = {
{ UDATA (&lpr_svc, UNIT_LPR(11), 0), 10000 },
{ UDATA (&lpr_svc, UNIT_LPR(13), 0), 10000 },
{ UDATA (&lpr_svc, UNIT_LPR(14), 0), 10000 },
};
@ -142,25 +143,32 @@ void lpr_cmd(int dev, uint32 cmd, uint32 *resp) {
if (NSI_TYPE(uptr->flags))
return;
if ((uptr->flags & UNIT_ATT) == 0)
return;
if (uptr->CMD & QUAL) {
uptr->CMD |= cmd << 8;
uptr->CMD &= ~QUAL;
sim_debug(DEBUG_CMD, &lpr_dev, "QUAL: %03o %03o %03o\n", cmd, uptr->CMD, uptr->STATUS);
*resp = 5;
return;
}
if (cmd == 032 || cmd == 02) { /* Command */
if (uptr->STATUS & BUSY) {
*resp = 3;
return;
}
uptr->CMD = (cmd == 02) ? AUTO: 0;
uptr->CMD = (cmd == 02) ? AUTO: QUAL;
uptr->STATUS = BUSY;
sim_activate(uptr, uptr->wait);
chan_clr_done(GET_UADDR(uptr->flags));
*resp = 5;
} else if (cmd == SEND_Q) {
if ((uptr->flags & UNIT_ATT) == 0)
if ((uptr->flags & UNIT_ATT) != 0)
*resp = 040;
if (uptr->STATUS & 06)
*resp = 040;
*resp |= uptr->STATUS & TERMINATE;
uptr->STATUS &= ~1;
if ((uptr->STATUS & BUSY) == 0)
*resp |= 030;
} else if (cmd == SEND_P) { /* Send P */
if ((uptr->flags & UNIT_ATT) != 0)
*resp = (uptr->STATUS & ERROR) | 1;
@ -286,6 +294,11 @@ t_stat lpr_svc (UNIT *uptr)
return SCPE_OK;
}
if (uptr->CMD & QUAL) {
sim_activate(uptr, uptr->wait);
return SCPE_OK;
}
len = 96;
if (LW_120(uptr->flags))
len = 120;
@ -293,7 +306,7 @@ t_stat lpr_svc (UNIT *uptr)
len = 160;
for (i = 0; i < len && eor == 0; i++) {
eor = chan_output_char(GET_UADDR(uptr->flags), &ch, 0);
sim_debug(DEBUG_DATA, &lpr_dev, "DATA: %03o\n", ch);
sim_debug(DEBUG_DATA, &lpr_dev, "DATA: %03o\n", ch);
switch (ch & 060) {
case 000: ch = 0060 | (ch & 017); break;
case 020: ch = 0040 | (ch & 017); break;
@ -304,8 +317,9 @@ t_stat lpr_svc (UNIT *uptr)
}
buffer[i++] = '\r';
buffer[i++] = '\n';
buffer[i++] = '\0';
buffer[i] = '\0';
fprintf(stderr, "Buffer: %s", buffer);
sim_fwrite(&buffer, 1, i, uptr->fileref);
/* Check if Done */
if (eor) {

6
ICL1900/icl1900_mt.c
View File

@ -167,10 +167,10 @@ void mt_cmd(int dev, uint32 cmd, uint32 *resp) {
if (mt_busy == 0)
*resp |= STQ_CTL_RDY;
if ((uptr->flags & UNIT_ATT) != 0) {
*resp |= STQ_TPT_RDY;
if (uptr->STATUS == 0)
*resp |= STQ_TPT_RDY;
if (!sim_tape_wrp(uptr))
*resp |= STQ_WRP;
// if ((uptr->CMD & MT_BUSY) == 0)
if (uptr->STATUS & 07776 || (uptr->CMD & MT_BUSY) == 0)
*resp |= STQ_P1;
}
@ -184,9 +184,11 @@ void mt_cmd(int dev, uint32 cmd, uint32 *resp) {
if (uptr->STATUS & 07700)
*resp |= ST1_P2;
}
uptr->STATUS &= 07700;
} else if (cmd == SEND_P2) {
if ((uptr->flags & UNIT_ATT) != 0)
*resp = (uptr->STATUS >> 6) & 037;
uptr->STATUS = 0;
}
sim_debug(DEBUG_STATUS, &mt_dev, "Status: unit:=%d %02o %02o\n", mt_drive, cmd, *resp);
return;

2
ICL1900/icl1900_stdio.c
View File

@ -342,8 +342,6 @@ chan_nsi_status(int dev, uint32 *resp) {
if (dibp != NULL && dibp->nsi_cmd != NULL) {
(dibp->nsi_status)(dev, resp);
}
if (dev > 10)
fprintf(stderr, "Status %d %08o\n\r", dev, *resp);
}

53
ICL1900/icl1900_sys.c
View File

@ -94,6 +94,18 @@ DEBTAB dev_debug[] = {
{"STATUS", DEBUG_STATUS, "Show status conditions"},
{0, 0}
};
/* Simulator card debug controls */
DEBTAB card_debug[] = {
{"CMD", DEBUG_CMD, "Show command execution to devices"},
{"DATA", DEBUG_DATA, "Show data transfers"},
{"DETAIL", DEBUG_DETAIL, "Show details about device"},
{"EXP", DEBUG_EXP, "Show console data"},
{"STATUS", DEBUG_STATUS, "Show status conditions"},
{"CARD", DEBUG_CARD, "Show Card read/punches"},
{0, 0}
};
uint8 parity_table[64] = {
@ -156,6 +168,47 @@ const char ascii_to_mem[128] = {
070, 071, 072, 024, -1, -1, -1, -1,
};
uint16 mem_to_hol[64] = {
/* 0 1 2 3 4 5 6 7 */
0x200, 0x100, 0x080, 0x040, 0x020, 0x010, 0x008, 0x004, /* 0x */
/* 8 9 : ; < = > ? */
0x002, 0x001, 0x812, 0x822, 0x40A, 0x20A, 0x412, 0x212, /* 1x */
/* bl ! " # lb, % & ` */
0x000, 0x206, 0x600, 0x042, 0x242, 0x222, 0x800, 0x80a, /* 2x */
/* ( ) * + , - . / */
0x012, 0x00a, 0x422, 0xA00, 0x282, 0x400, 0x842, 0x300, /* 3x */
/* @ A B C D E F G */
0x012, 0x900, 0x880, 0x840, 0x820, 0x810, 0x808, 0x804, /* 4x */
/* H I J K L M N O */
0x802, 0x801, 0x500, 0x480, 0x440, 0x420, 0x410, 0x408, /* 5x */
/* P Q R S T U V W */
0x404, 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, /* 6x */
/* X Y Z [ $ ] ^ _ */
0x204, 0x202, 0x201, 0x482, 0x442, 0x006, 0x406, 0x206, /* 7x */
};
uint8 hol_to_mem[4096];
/* 2+8 22 12+2+8 33 11+2+8 73 0+2+8 24
3+8 23 12+3+8 36 11+3+8 74 0+3+8 34
4+8 40 12+4+8 13 11+4+8 32 0+4+8 25
5+8 30 12+5+8 12 11+5+8 16 0+5+8 17
6+8 31 12+6+8 27 11+6+8 14 0+6+8 15
7+8 75 12+7+8 21 11+7+8 76 0+7+8 77
0-9 00 -> 11
12+0 -> 26
12+n -> 40+n
11 -> 35
11+0 -> 22
11+n -> 51+n
10 -> 0
10+1 -> 37
10+n -> 61
*/
/* Load a card image file into memory. */

37
ICL1900/icl1900_tr.c
View File

@ -113,6 +113,8 @@ void ptr_nsi_status (int dev, uint32 *resp);
t_stat ptr_svc (UNIT *uptr);
t_stat ptr_reset (DEVICE *dptr);
t_stat ptr_boot (int32 unit_num, DEVICE * dptr);
t_stat ptr_attach(UNIT *, CONST char *);
t_stat ptr_detach(UNIT *);
t_stat ptr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
CONST char *ptr_description (DEVICE *dptr);
@ -138,7 +140,7 @@ MTAB ptr_mod[] = {
DEVICE ptr_dev = {
"TR", ptr_unit, NULL, ptr_mod,
NUM_DEVS_PTR, 8, 22, 1, 8, 22,
NULL, NULL, &ptr_reset, &ptr_boot, &attach_unit, &detach_unit,
NULL, NULL, &ptr_reset, &ptr_boot, &ptr_attach, &ptr_detach,
&ptr_dib, DEV_DISABLE | DEV_DEBUG, 0, dev_debug,
NULL, NULL, &ptr_help, NULL, NULL, &ptr_description
};
@ -209,11 +211,14 @@ void ptr_cmd(int dev, uint32 cmd, uint32 *resp) {
}
if ((uptr->STATUS & ERROR) != 0)
*resp |= 040;
sim_debug(DEBUG_STATUS, &ptr_dev, "STATUS: %03o %03o\n", cmd, *resp);
uptr->STATUS &= ~TERMINATE;
} else if (cmd == 024) { /* Send P */
if ((uptr->flags & UNIT_ATT) != 0)
*resp = 1;
if ((uptr->STATUS & ERROR) != 0)
*resp |= 2;
sim_debug(DEBUG_STATUS, &ptr_dev, "STATUS: %03o %03o\n", cmd, *resp);
uptr->STATUS = 0;
chan_clr_done(dev);
}
@ -264,6 +269,7 @@ void ptr_nsi_cmd(int dev, uint32 cmd) {
if (cmd & 02) {
if (uptr->CMD & BUSY)
uptr->CMD |= DISC;
sim_debug(DEBUG_CMD, &ptr_dev, "Stop: %03o\n", cmd);
return;
}
@ -285,6 +291,7 @@ void ptr_nsi_cmd(int dev, uint32 cmd) {
uptr->CMD |= IGN_BLNK;
uptr->CMD |= BUSY;
uptr->STATUS = 0;
sim_debug(DEBUG_CMD, &ptr_dev, "Start: %03o\n", cmd);
sim_activate(uptr, uptr->wait);
chan_clr_done(dev);
}
@ -323,6 +330,7 @@ void ptr_nsi_status(int dev, uint32 *resp) {
*resp = uptr->STATUS;
if (uptr->CMD & BUSY)
*resp |= 040;
sim_debug(DEBUG_STATUS, &ptr_dev, "STATUS: %03o\n", *resp);
uptr->STATUS = 0;
chan_clr_done(dev);
}
@ -359,12 +367,12 @@ t_stat ptr_svc (UNIT *uptr)
}
/* Read next charater */
if ((uptr->flags & UNIT_ATT) == 0 ||
feof(uptr->fileref) ||
(data = getc (uptr->fileref)) == EOF) {
if (feof(uptr->fileref) || (data = getc (uptr->fileref)) == EOF) {
uptr->CMD &= 1;
sim_debug(DEBUG_DETAIL, &ptr_dev, "Tape Empty\n");
detach_unit(uptr);
chan_set_done(dev);
uptr->STATUS = TERMINATE;
uptr->STATUS = TERMINATE|OPAT;
return SCPE_OK;
}
@ -510,6 +518,25 @@ ptr_boot(int32 unit_num, DEVICE * dptr)
return SCPE_OK;
}
t_stat
ptr_attach(UNIT * uptr, CONST char *file)
{
t_stat r;
if ((r = attach_unit(uptr, file)) != SCPE_OK)
return r;
uptr->STATUS = 0;
chan_set_done(GET_UADDR(uptr->flags));
return SCPE_OK;
}
t_stat
ptr_detach(UNIT * uptr)
{
return detach_unit(uptr);
}
t_stat ptr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{