1
0
mirror of https://github.com/rcornwell/sims.git synced 2026-04-16 00:21:25 +00:00

KA10: Fixes to WAITS FIX instruction.

This commit is contained in:
Richard Cornwell
2020-05-30 16:18:43 -04:00
parent 9b40636adf
commit b170ecd50c
2 changed files with 19 additions and 5 deletions

View File

@@ -92,7 +92,7 @@
#define POS_Y 00000377700
#define CBRT 00000000070 /* Current brightness */
#define CSIZE 00000000007 /* Current char size */
#define POS_X_V 16
#define POS_X_V 17
#define POS_Y_V 6
#define CBRT_V 3
#define CSIZE_V 0

View File

@@ -4273,6 +4273,8 @@ in_loop:
}
}
} while (ind & !pi_rq);
/* If not a JRST clear the upper half of AR. */
if (IR != 0254) {
AR &= RMASK;
}
@@ -5776,7 +5778,7 @@ dpnorm:
hst[hst_p].mb = AR;
}
MQ = 0;
AR = SWAP_AR;
AR = AR << 18; /* Move to upper half */
goto ufa;
}
#endif
@@ -6223,7 +6225,7 @@ fnorm:
if (((SC & 0400) != 0) ^ ((SC & 0200) != 0))
fxu_hold_set = 1;
#endif
if (IR != 0130) { /* !UFA */
if (IR != 0130 && IR != 0247) { /* !UFA and WAITS FIX */
fnormx:
while (AR != 0 && ((AR & FPSBIT) != 0) == ((AR & FPNBIT) != 0) &&
((AR & FPNBIT) != 0) == ((AR & FP1BIT) != 0)) {
@@ -6293,6 +6295,18 @@ fnormx:
check_apr_irq();
}
#endif
#if WAITS
/* WAITS FIX Instruction. This can't occur if WAITS not set */
if (IR == 0247) {
/* Extend sign if negative */
if (flag1)
AR |= EMASK;
set_reg(AC, AR);
break;
}
#endif
/* Set exponent */
SCAD = SC ^ ((AR & SMASK) ? 0377 : 0);
AR &= SMASK|MMASK;
AR |= ((uint64)(SCAD & 0377)) << 27;
@@ -6304,6 +6318,7 @@ fnormx:
MQ |= SMASK;
}
#else
/* FADL FSBL FMPL */
if ((IR & 07) == 1) {
SC = (SC + (0777 ^ 26)) & 0777;
@@ -6316,14 +6331,13 @@ fnormx:
}
}
#endif
/* Kill exponent if 0 */
if ((AR & MMASK) == 0)
AR = 0;
/* Handle UFA */
if (IR == 0130) {
set_reg(AC + 1, AR);
break;
}
break;