1
0
mirror of https://github.com/rcornwell/sims.git synced 2026-04-25 03:35:58 +00:00

KA10: Updated ITS paging hardware and tape handling.

This commit is contained in:
Richard Cornwell
2018-02-05 22:54:10 -05:00
parent 11f0ca56b0
commit b2e3cc29e5
3 changed files with 41 additions and 11 deletions

View File

@@ -1331,6 +1331,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
int page = (RMASK & addr) >> 10;
int acc;
int uf = (FLAGS & USER) != 0;
int ofd = fault_data;
/* If paging is not enabled, address is direct */
if (!page_enable) {
@@ -1378,6 +1379,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
}
}
/* Map the page */
if (!uf) {
/* Handle system mapping */
@@ -1416,16 +1418,18 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
case 1: /* Read Only Access */
if (!wr)
return 1;
fault_data |= 0100;
if ((fault_data & 00770) == 0)
fault_data |= 0100;
break;
case 2: /* Read write first */
if (fetch && (FLAGS & PURE)) {
fault_data |= 0020;
break;
}
if (!wr)
if (!wr) /* Read is OK */
return 1;
fault_data |= 040;
if ((fault_data & 00770) == 0)
fault_data |= 040;
break;
case 3: /* All access */
if (fetch && (FLAGS & PURE)) {
@@ -1435,8 +1439,9 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
return 1;
}
fault:
/* Update fault data */
fault_addr = (page) | ((uf)? 0400 : 0) | ((data & 0777) << 9);
/* Update fault data, fault address only if new fault */
if ((ofd & 00770) == 0)
fault_addr = (page) | ((uf)? 0400 : 0) | ((data & 0777) << 9);
if ((xct_flag & 04) == 0) {
mem_prot = 1;
fault_data |= 01000;
@@ -1886,10 +1891,18 @@ if ((reason = build_dev_tab ()) != SCPE_OK) /* build, chk dib_tab */
#if ITS
one_p_arm = 0;
#endif
#if ITS
if (QITS)
sim_activate(&cpu_unit[1], 10000);
#endif
while ( reason == 0) { /* loop until ABORT */
if (sim_interval <= 0) { /* check clock queue */
if ((reason = sim_process_event()) != SCPE_OK) {/* error? stop sim */
#if ITS
if (QITS)
sim_cancel(&cpu_unit[1]);
#endif
return reason;
}
}
@@ -2036,8 +2049,17 @@ st_pi:
/* Check if possible idle loop */
if (sim_idle_enab && (FLAGS & USER) != 0 && PC < 020 && AB < 020 &&
(IR & 0760) == 0340)
(IR & 0760) == 0340) {
#if ITS
if (QITS)
sim_cancel(&cpu_unit[1]);
#endif
sim_idle (TMR_RTC, FALSE);
#if ITS
if (QITS)
sim_activate(&cpu_unit[1], 10000);
#endif
}
/* Update history */
#if KI
@@ -4640,10 +4662,19 @@ last:
pi_restore = 0;
}
sim_interval--;
if (!pi_cycle && instr_count != 0 && --instr_count == 0)
if (!pi_cycle && instr_count != 0 && --instr_count == 0) {
#if ITS
if (QITS)
sim_cancel(&cpu_unit[1]);
#endif
return SCPE_STEP;
}
}
/* Should never get here */
#if ITS
if (QITS)
sim_cancel(&cpu_unit[1]);
#endif
return reason;
}
@@ -4715,7 +4746,6 @@ sim_activate(&cpu_unit[0], 10000);
#if ITS
if (QITS) {
sim_rtcn_init_unit (&cpu_unit[1], cpu_unit[1].wait, TMR_RTC);
sim_activate(&cpu_unit[1], 10000);
}
#endif
return SCPE_OK;

View File

@@ -784,7 +784,7 @@ t_stat mt_srv(UNIT * uptr)
sim_activate(uptr, 5000);
return SCPE_OK;
}
sim_activate(uptr, 400);
sim_activate(uptr, 500);
return SCPE_OK;
}

View File

@@ -43,7 +43,7 @@ t_stat pd_set_off(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat pd_show_on(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
UNIT pd_unit[] = {
{UDATA(NULL, UNIT_DISABLE , 0)}, /* 0 */
{UDATA(NULL, UNIT_DISABLE, 0)}, /* 0 */
};
DIB pd_dib = {PD_DEVNUM, 1, &pd_devio, NULL};
@@ -57,7 +57,7 @@ DEVICE pd_dev = {
"PD", pd_unit, NULL, pd_mod,
1, 8, 0, 1, 8, 36,
NULL, NULL, NULL, NULL, NULL, NULL,
&pd_dib, DEV_DISABLE | DEV_DEBUG, 0, NULL,
&pd_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, NULL,
NULL, NULL, NULL, NULL, NULL, &pd_description
};