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https://github.com/rcornwell/sims.git
synced 2026-04-25 03:35:58 +00:00
KA10: Updated ITS paging hardware and tape handling.
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@@ -1331,6 +1331,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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int page = (RMASK & addr) >> 10;
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int acc;
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int uf = (FLAGS & USER) != 0;
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int ofd = fault_data;
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/* If paging is not enabled, address is direct */
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if (!page_enable) {
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@@ -1378,6 +1379,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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}
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}
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/* Map the page */
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if (!uf) {
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/* Handle system mapping */
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@@ -1416,16 +1418,18 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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case 1: /* Read Only Access */
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if (!wr)
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return 1;
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fault_data |= 0100;
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if ((fault_data & 00770) == 0)
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fault_data |= 0100;
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break;
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case 2: /* Read write first */
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if (fetch && (FLAGS & PURE)) {
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fault_data |= 0020;
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break;
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}
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if (!wr)
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if (!wr) /* Read is OK */
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return 1;
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fault_data |= 040;
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if ((fault_data & 00770) == 0)
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fault_data |= 040;
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break;
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case 3: /* All access */
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if (fetch && (FLAGS & PURE)) {
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@@ -1435,8 +1439,9 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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return 1;
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}
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fault:
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/* Update fault data */
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fault_addr = (page) | ((uf)? 0400 : 0) | ((data & 0777) << 9);
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/* Update fault data, fault address only if new fault */
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if ((ofd & 00770) == 0)
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fault_addr = (page) | ((uf)? 0400 : 0) | ((data & 0777) << 9);
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if ((xct_flag & 04) == 0) {
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mem_prot = 1;
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fault_data |= 01000;
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@@ -1886,10 +1891,18 @@ if ((reason = build_dev_tab ()) != SCPE_OK) /* build, chk dib_tab */
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#if ITS
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one_p_arm = 0;
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#endif
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#if ITS
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if (QITS)
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sim_activate(&cpu_unit[1], 10000);
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#endif
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while ( reason == 0) { /* loop until ABORT */
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if (sim_interval <= 0) { /* check clock queue */
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if ((reason = sim_process_event()) != SCPE_OK) {/* error? stop sim */
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#if ITS
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if (QITS)
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sim_cancel(&cpu_unit[1]);
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#endif
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return reason;
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}
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}
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@@ -2036,8 +2049,17 @@ st_pi:
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/* Check if possible idle loop */
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if (sim_idle_enab && (FLAGS & USER) != 0 && PC < 020 && AB < 020 &&
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(IR & 0760) == 0340)
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(IR & 0760) == 0340) {
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#if ITS
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if (QITS)
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sim_cancel(&cpu_unit[1]);
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#endif
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sim_idle (TMR_RTC, FALSE);
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#if ITS
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if (QITS)
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sim_activate(&cpu_unit[1], 10000);
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#endif
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}
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/* Update history */
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#if KI
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@@ -4640,10 +4662,19 @@ last:
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pi_restore = 0;
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}
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sim_interval--;
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if (!pi_cycle && instr_count != 0 && --instr_count == 0)
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if (!pi_cycle && instr_count != 0 && --instr_count == 0) {
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#if ITS
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if (QITS)
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sim_cancel(&cpu_unit[1]);
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#endif
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return SCPE_STEP;
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}
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}
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/* Should never get here */
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#if ITS
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if (QITS)
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sim_cancel(&cpu_unit[1]);
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#endif
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return reason;
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}
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@@ -4715,7 +4746,6 @@ sim_activate(&cpu_unit[0], 10000);
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#if ITS
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if (QITS) {
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sim_rtcn_init_unit (&cpu_unit[1], cpu_unit[1].wait, TMR_RTC);
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sim_activate(&cpu_unit[1], 10000);
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}
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#endif
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return SCPE_OK;
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@@ -784,7 +784,7 @@ t_stat mt_srv(UNIT * uptr)
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sim_activate(uptr, 5000);
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return SCPE_OK;
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}
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sim_activate(uptr, 400);
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sim_activate(uptr, 500);
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return SCPE_OK;
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}
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@@ -43,7 +43,7 @@ t_stat pd_set_off(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat pd_show_on(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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UNIT pd_unit[] = {
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{UDATA(NULL, UNIT_DISABLE , 0)}, /* 0 */
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{UDATA(NULL, UNIT_DISABLE, 0)}, /* 0 */
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};
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DIB pd_dib = {PD_DEVNUM, 1, &pd_devio, NULL};
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@@ -57,7 +57,7 @@ DEVICE pd_dev = {
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"PD", pd_unit, NULL, pd_mod,
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1, 8, 0, 1, 8, 36,
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NULL, NULL, NULL, NULL, NULL, NULL,
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&pd_dib, DEV_DISABLE | DEV_DEBUG, 0, NULL,
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&pd_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, NULL,
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NULL, NULL, NULL, NULL, NULL, &pd_description
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};
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