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https://github.com/rcornwell/sims.git
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IBM360: Misc bug fixes, still not working.
This commit is contained in:
Richard Cornwell
parent
ad6d475519
commit
c663c1ff53
@ -493,6 +493,16 @@ chan_end(uint16 addr, uint8 flags) {
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if (chan_status[chan] & (STATUS_DEND|STATUS_CEND)) {
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chan_byte[chan] = BUFF_NEWCMD;
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while ((ccw_flags[chan] & FLAG_CD)) {
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if (load_ccw(chan, 1))
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break;
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if (ccw_count[chan] != 0 && (ccw_flags[chan] & FLAG_SLI) == 0) {
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sim_debug(DEBUG_DETAIL, &cpu_dev, "chan_end length\n");
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chan_status[chan] |= STATUS_LENGTH;
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ccw_flags[chan] = 0;
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}
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}
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}
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irq_pend = 1;
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@ -53,6 +53,7 @@ uint32 cregs[16]; /* Control registers /67 or 370 only */
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uint8 sysmsk; /* Interupt mask */
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uint8 st_key; /* Storage key */
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uint8 cc; /* CC */
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uint8 ilc; /* Instruction length code */
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uint8 pmsk; /* Program mask */
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uint16 irqcode; /* Interupt code */
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uint8 flags; /* Misc flags */
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@ -195,6 +196,7 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, MEMAMOUNT(12), "196K", "196K", &cpu_set_size },
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{ UNIT_MSIZE, MEMAMOUNT(16), "256K", "256K", &cpu_set_size },
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{ UNIT_MSIZE, MEMAMOUNT(32), "512K", "512K", &cpu_set_size },
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{ UNIT_MSIZE, MEMAMOUNT(128), "2M", "2M", &cpu_set_size },
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{ FEAT_PROT, 0, NULL, "NOPROT", NULL, NULL, NULL, "No Storage protection"},
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{ FEAT_PROT, FEAT_PROT, "PROT", "PROT", NULL, NULL, NULL, "Storage protection"},
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{ FEAT_DEC, 0, NULL, "NODECIMAL", NULL, NULL, NULL},
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@ -248,9 +250,9 @@ void post_extirq() {
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void storepsw(uint32 addr, uint16 ircode) {
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uint32 word;
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irqaddr = addr + 0x40;
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word = ((uint32)sysmsk) << 24 |
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((uint32)st_key) << 16 |
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((uint32)flags) << 16 |
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word = (((uint32)sysmsk) << 24) |
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(((uint32)st_key) << 16) |
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(((uint32)flags) << 16) |
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((uint32)ircode);
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M[addr >> 2] = word;
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if (hst_lnt) {
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@ -261,8 +263,9 @@ void storepsw(uint32 addr, uint16 ircode) {
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hst[hst_p].src1 = word;
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}
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addr += 4;
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word = ((uint32)pmsk) << 24 |
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((uint32)cc) << 28 |
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word = (((uint32)ilc) << 30) |
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(((uint32)cc) << 28) |
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(((uint32)pmsk) << 24) |
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PC;
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M[addr >> 2] = word;
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if (hst_lnt) {
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@ -536,7 +539,7 @@ sim_instr(void)
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reason = SCPE_OK;
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/* Enable timer if option set */
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if (cpu_unit.flags & FEAT_TIMER) {
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sim_activate(&cpu_unit, 10000);
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sim_activate(&cpu_unit, 100);
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}
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interval_irq = 0;
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@ -598,8 +601,10 @@ wait_loop:
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}
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//}
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ilc = 0;
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if (ReadHalf(PC, &src1))
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goto supress;
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ilc = 1;
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if (hst_lnt)
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hst[hst_p].inst[0] = src1;
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PC += 2;
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@ -613,15 +618,17 @@ wait_loop:
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pmsk += 0x40;
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if (ReadHalf(PC, &addr1))
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goto supress;
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if (hst_lnt)
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hst[hst_p].inst[1] = addr1;
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ilc = 2;
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PC += 2;
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if (hst_lnt)
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hst[hst_p].inst[1] = addr1;
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/* Check if SS */
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if ((op & 0xc0) == 0xc0) {
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pmsk += 0x40;
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if (ReadHalf(PC, &addr2))
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goto supress;;
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PC += 2;
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ilc = 3;
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if (hst_lnt)
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hst[hst_p].inst[2] = addr2;
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}
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@ -656,7 +663,7 @@ opr:
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goto supress;
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}
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if (reg1 & 0x9) {
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reason=1;
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// reason=1;
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storepsw(OPPSW, IRC_SPEC);
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goto supress;
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}
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@ -720,7 +727,9 @@ opr:
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case OP_BALR:
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case OP_BAL:
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dest = ((((cc & 03) << 4) | pmsk) << 24) | PC;
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dest = (((uint32)ilc) << 30) |
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((uint32)(cc & 03) << 28) |
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(((uint32)pmsk) << 24) | PC;
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if (op != OP_BALR || (reg & 0xf))
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PC = addr1 & 0xffffff;
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regs[reg1] = dest;
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@ -955,9 +964,10 @@ set_cc3:
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storepsw(OPPSW, IRC_SPEC);
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break;
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}
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src1 = regs[reg1|1];
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case OP_MH:
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fill = 0;
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// fprintf(stderr, "Mul %d x %d = ", src1, src2);
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fprintf(stderr, "Mul %d x %d = ", src1, src2);
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if (src1 & MSIGN) {
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fill = 1;
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@ -991,7 +1001,7 @@ set_cc3:
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} else {
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regs[reg1] = src1;
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}
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//fprintf(stderr, " %d %08x %08x\n\r", src1, dest, src1);
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fprintf(stderr, " %d %08x %08x\n\r", src1, dest, src1);
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// reason =1;
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break;
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@ -1601,7 +1611,7 @@ save_dbl:
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}
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if (dest & MSIGN) {
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storepsw(OPPSW, IRC_FIXDIV);
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reason =1;
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// reason =1;
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//fprintf(stderr, "\n\r");
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break;
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}
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@ -2034,12 +2044,11 @@ rtc_srv(UNIT * uptr)
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int32 t;
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t = sim_rtcn_calb (rtc_tps, TMR_RTC);
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sim_activate_after(uptr, 1000000/rtc_tps);
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t = M[0x50>>2];
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M[0x50>>2]--;
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if (((t ^ M[0x50>>2]) & MSIGN) != 0 && (t & MSIGN) == 0) {
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if (M[0x50>>2] == 0) {
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fprintf(stderr, "Timer %08x\n\r", M[0x50>>2]);
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interval_irq = 1;
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}
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M[0x50>>2]--;
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}
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return SCPE_OK;
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}
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@ -429,6 +429,12 @@ t_stat dasd_srv(UNIT * uptr)
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if ((uptr->u3 & 0x83) == 0x82) {
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sim_debug(DEBUG_DETAIL, dptr, "adv head unit=%d %02x %d %d\n", unit, state,
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data->tpos, uptr->u4 & 0xff);
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if ((data->filemsk & DK_MSK_SK) == DK_MSK_SKNONE) {
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uptr->u5 |= (SNS_WRP << 8);
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uptr->u3 &= ~0xff;
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chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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goto index;
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}
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uptr->u4 ++;
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if ((uptr->u3 & 0x7) == 1 && (uptr->u3 & 0x60) != 0)
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uptr->u3 &= ~DK_INDEX;
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@ -454,6 +460,7 @@ t_stat dasd_srv(UNIT * uptr)
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uptr->u3 &= ~0xff;
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chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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}
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index:
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uptr->u3 |= DK_INDEX;
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data->tstart = data->tsize * (uptr->u4 & 0xff);
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data->tpos = data->rpos = 0;
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@ -503,7 +510,7 @@ t_stat dasd_srv(UNIT * uptr)
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}
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break;
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case DK_POS_KEY: /* In Key area */
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data->tpos++;
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data->tpos++;
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if (data->count == data->klen) {
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sim_debug(DEBUG_POS, dptr, "state key unit=%d %d %d\n", unit, data->rec,
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data->count);
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@ -517,7 +524,7 @@ t_stat dasd_srv(UNIT * uptr)
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}
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break;
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case DK_POS_DATA: /* In Data area */
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data->tpos++;
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data->tpos++;
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if (data->count == data->dlen) {
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sim_debug(DEBUG_POS, dptr, "state data unit=%d %d %d\n", unit, data->rec,
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data->count);
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@ -804,13 +811,18 @@ t_stat dasd_srv(UNIT * uptr)
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case DK_RD_CNT: /* Read count */
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/* Wait for next address mark */
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if (state == DK_POS_AM)
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// if (uptr->u3 & DK_PARAM) {
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// uptr->u5 |= (SNS_NOREC << 8);
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// uptr->u3 &= ~0xff;
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// chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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// }
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uptr->u3 |= DK_PARAM;
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/* If at end of disk, index or home address, stop reading */
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if (state == DK_POS_END || state == DK_POS_INDEX || state == DK_POS_HA)
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uptr->u3 &= ~DK_PARAM;
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// if (state == DK_POS_END || state == DK_POS_INDEX || state == DK_POS_HA)
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// uptr->u3 &= ~DK_PARAM;
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/* When we are at count segment and passed address mark */
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if (uptr->u3 & DK_PARAM && state == DK_POS_CNT) {
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if (uptr->u3 & DK_PARAM && state == DK_POS_CNT && data->rec != 0) {
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ch = *da;
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sim_debug(DEBUG_DETAIL, dptr, "readcnt ID unit=%d %d %x %02x %x %d %x\n",
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unit, count, state, ch, uptr->u4, data->tpos, uptr->u4);
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@ -1035,17 +1047,17 @@ rd:
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chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP);
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break;
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}
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if (state == DK_POS_DATA && count == data->dlen) {
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uptr->u3 &= ~(0xff|DK_PARAM);
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chan_end(addr, SNS_CHNEND|SNS_DEVEND);
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break;
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}
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if (state == DK_POS_INDEX) {
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uptr->u5 = SNS_TRKOVR << 8;
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uptr->u3 &= ~(0xff|DK_PARAM);
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chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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break;
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}
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if (state == DK_POS_DATA && count == data->dlen) {
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uptr->u3 &= ~(0xff|DK_PARAM);
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chan_end(addr, SNS_CHNEND|SNS_DEVEND);
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break;
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}
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ch = *da;
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sim_debug(DEBUG_DATA, dptr, "RD Char %02x %02x %d %d\n",
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ch, state, count, data->tpos);
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@ -1173,6 +1185,9 @@ rd:
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if (((uptr->u6 & 0x13) == 0x11 &&
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(uptr->u3 & (DK_SHORTSRC|DK_SRCOK)) == DK_SRCOK)) {
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uptr->u3 |= DK_PARAM;
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sim_debug(DEBUG_DETAIL, dptr, "WR KD unit=%d %d k=%d d=%d %02x %04x %d\n",
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unit, data->rec, data->klen, data->dlen, data->state,
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8 + data->klen + data->dlen, count);
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} else {
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uptr->u5 |= SNS_CMDREJ | (SNS_INVSEQ << 8);
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uptr->u6 = 0;
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@ -1196,6 +1211,9 @@ rd:
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if (((uptr->u6 & 0x3) == 1 && (uptr->u6 & 0xE0) != 0 &&
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(uptr->u3 & (DK_SHORTSRC|DK_SRCOK)) == DK_SRCOK)) {
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uptr->u3 |= DK_PARAM;
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sim_debug(DEBUG_DETAIL, dptr, "WR D unit=%d %d k=%d d=%d %02x %04x %d\n",
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unit, data->rec, data->klen, data->dlen, data->state,
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8 + data->klen + data->dlen, count);
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} else {
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uptr->u5 |= SNS_CMDREJ | (SNS_INVSEQ << 8);
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uptr->u6 = 0;
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@ -1212,7 +1230,7 @@ wrckd:
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uptr->u3 &= ~(0xff|DK_PARAM);
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chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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break;
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} else if (state == DK_POS_DATA && count == data->dlen) {
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} else if (state == DK_POS_DATA && data->count == data->dlen) {
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uptr->u6 = cmd;
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uptr->u3 &= ~(0xff|DK_PARAM);
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chan_end(addr, SNS_CHNEND|SNS_DEVEND);
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@ -1241,7 +1259,8 @@ wrckd:
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data->state = DK_POS_KEY;
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if (data->klen == 0)
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data->state = DK_POS_DATA;
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}
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data->count = 0;
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}
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}
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break;
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@ -197,7 +197,7 @@ uint8 lpr_startcmd(UNIT * uptr, uint16 chan, uint8 cmd)
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sim_debug(DEBUG_CMD, &lpr_dev, "Cmd %02x\n", cmd);
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switch (cmd & 0x7) {
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switch (cmd & 0x3) {
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case 1: /* Write command */
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uptr->u3 &= ~(LPR_CMDMSK);
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uptr->u3 |= (cmd & LPR_CMDMSK);
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@ -215,14 +215,14 @@ uint8 lpr_startcmd(UNIT * uptr, uint16 chan, uint8 cmd)
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return SNS_CHNEND;
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case 0: /* Status */
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if (cmd == 0x4) { /* Sense */
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uptr->u3 &= ~(LPR_CMDMSK);
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uptr->u3 |= (cmd & LPR_CMDMSK);
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sim_activate(uptr, 10); /* Start unit off */
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return 0;
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}
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break;
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case 4: /* Sense */
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uptr->u3 &= ~(LPR_CMDMSK);
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uptr->u3 |= (cmd & LPR_CMDMSK);
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sim_activate(uptr, 10); /* Start unit off */
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return 0;
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default: /* invalid command */
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uptr->u5 |= SNS_CMDREJ;
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break;
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