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KA10: Minor cleanup of KI10 paging, RP10 Disk and TMA Tape.
This commit is contained in:
Richard Cornwell
parent
bd83b1f2be
commit
cd8849128c
@ -105,7 +105,7 @@
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#define TMR_RTC 1
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#define UNIT_V_MSIZE (UNIT_V_UF + 0)
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#if KI10
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#if KI
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#define UNIT_MSIZE (0177 << UNIT_V_MSIZE)
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#else
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#define UNIT_MSIZE (017 << UNIT_V_MSIZE)
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@ -269,7 +269,7 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 8, "128K", "128K", &cpu_set_size },
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{ UNIT_MSIZE, 12, "196K", "196K", &cpu_set_size },
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{ UNIT_MSIZE, 16, "256K", "256K", &cpu_set_size },
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#if KI_22BIT
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#if KI_22BIT|KI
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{ UNIT_MSIZE, 32, "512K", "512K", &cpu_set_size },
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{ UNIT_MSIZE, 64, "1024K", "1024K", &cpu_set_size },
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{ UNIT_MSIZE, 128, "2048K", "2048K", &cpu_set_size },
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@ -998,18 +998,26 @@ t_stat null_dev(uint32 dev, uint64 *data) {
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int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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uint64 data;
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int base = ub_ptr;
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int page = addr >> 9;
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int page = (RMASK & addr) >> 9;
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int uf = (FLAGS & USER) != 0;
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if (page_fault)
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return 0;
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/* If paging is not enabled, address is direct */
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if (!page_enable) {
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*loc = addr;
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return 1;
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}
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/* If fetching byte data, use write access */
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if (BYF5 && (IR & 06) == 6)
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wr = 1;
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/* If this is modify instruction use write access */
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wr |= modify;
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/* Figure out if this is a user space access */
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if (flag)
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uf = 0;
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else if (xct_flag != 0 && !cur_context && !uf) {
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@ -1019,6 +1027,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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}
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}
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/* If user, check if small user enabled */
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if (uf) {
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if (small_user && (page & 0340) != 0) {
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fault_data = (((uint64)(page))<<18) | ((uint64)(uf) << 27) | 020LL;
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@ -1026,20 +1035,17 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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fprintf(stderr, " %03o small fault\n\r", page);
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return 0;
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}
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data = M[base + (page >> 1)];
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} else {
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/* If paging is not enabled, address is direct */
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if (!page_enable) {
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*loc = addr;
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return 1;
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}
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/* Handle system mapping */
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/* Pages 340-377 via UBR */
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if ((page & 0740) == 0340) {
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page += 01000 - 0340;
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/* Pages 400-777 via EBR */
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} else if (page & 0400) {
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base = eb_ptr;
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/* Pages 000-037 direct map */
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} else {
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/* Check if supervisory mode */
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if (!flag && ((FLAGS & PUBLIC) != 0)) {
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/* Handle public violation */
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fault_data = (((uint64)(page))<<18) | ((uint64)(uf) << 27) | 021LL;
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@ -1050,11 +1056,14 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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return 1;
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}
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}
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/* Map the page */
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data = M[base + (page >> 1)];
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/* Even in left half, Odd in right half. */
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if ((page & 1) == 0)
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data >>= 18;
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data &= RMASK;
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*loc = ((data & 017777) << 9) + (addr & 0777);
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/* Access check logic */
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if (!flag && ((FLAGS & PUBLIC) != 0) && ((data & 0200000) == 0)) {
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/* Handle public violation */
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fault_data = (((uint64)(page))<<18) | ((uint64)(uf) << 27) | 021LL;
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@ -379,6 +379,8 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
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}
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if (tmp)
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df10->status &= ~PI_ENABLE;
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else
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df10_setirq(df10);
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}
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sim_debug(DEBUG_CONO, dptr, "DP %03o CONO %06o %d PC=%o %06o\n", dev,
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(uint32)*data, ctlr, PC, df10->status);
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@ -543,28 +545,33 @@ t_stat dp_svc (UNIT *uptr)
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if (uptr->STATUS & END_CYL) {
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uptr->UFLAGS |= DONE;
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df10_finish_op(df10, 0);
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sim_debug(DEBUG_DATA, dptr, "DP %03o DFS %012llo %06o %06o\n", ctlr, M[df10->cia|1], df10->ccw, df10->cda);
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return SCPE_OK;
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}
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if (sect >= dp_drv_tab[dtype].sect) {
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uptr->UFLAGS |= DONE;
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uptr->STATUS |= SEC_ERR;
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df10_finish_op(df10, 0);
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sim_debug(DEBUG_DATA, dptr, "DP %03o DFS %012llo %06o %06o\n", ctlr, M[df10->cia|1], df10->ccw, df10->cda);
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return SCPE_OK;
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}
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if (surf >= dp_drv_tab[dtype].surf) {
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uptr->UFLAGS |= DONE;
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uptr->STATUS |= SUF_ERR;
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df10_finish_op(df10, 0);
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sim_debug(DEBUG_DATA, dptr, "DP %03o DFS %012llo %06o %06o\n", ctlr, M[df10->cia|1], df10->ccw, df10->cda);
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return SCPE_OK;
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}
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if (cyl != uptr->CUR_CYL) {
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uptr->UFLAGS |= DONE;
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uptr->STATUS |= SRC_ERR;
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df10_finish_op(df10, 0);
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sim_debug(DEBUG_DATA, dptr, "DP %03o DFS %012llo %06o %06o\n", ctlr, M[df10->cia|1], df10->ccw, df10->cda);
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return SCPE_OK;
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}
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if ((uptr->STATUS & BUSY) == 0) {
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df10_finish_op(df10, 0);
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sim_debug(DEBUG_DATA, dptr, "DP %03o DFS %012llo %06o %06o\n", ctlr, M[df10->cia|1], df10->ccw, df10->cda);
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return SCPE_OK;
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}
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if (cmd != WR) {
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@ -647,6 +654,7 @@ t_stat dp_svc (UNIT *uptr)
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if (r)
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sim_activate(uptr, 25);
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else {
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sim_debug(DEBUG_DATA, dptr, "DP %03o DFS %012llo %06o %06o\n", ctlr, M[df10->cia|1], df10->ccw, df10->cda);
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uptr->STATUS &= ~(SRC_DONE|BUSY);
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uptr->UFLAGS |= DONE;
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}
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@ -257,8 +257,6 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
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case WTM:
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break;
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case READ:
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// if ((uptr->u3 & ODD_PARITY) != 0)
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// status |= PARITY_ERR;
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CLR_BUF(uptr);
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uptr->u5 = 0;
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uptr->u6 = 0;
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@ -269,8 +267,6 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
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break;
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}
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case CMP:
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// if ((uptr->u3 & ODD_PARITY) != 0)
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// status |= PARITY_ERR;
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CLR_BUF(uptr);
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uptr->u5 = 0;
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uptr->u6 = 0;
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@ -281,14 +277,9 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
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set_interrupt(MT_DEVNUM, pia);
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}
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}
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// if (NOP_CLR != ((uptr->u3 & FUNCTION) >> 9)) {
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// uptr->u3 |= MT_MOTION;
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// status |= JOB_DONE;
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// break;
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// }
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status |= IDLE_UNIT;
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uptr->u3 |= MT_BUSY;
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sim_activate(uptr, 100);
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sim_activate(uptr, 300);
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} else {
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sim_activate(uptr, 9999999);
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sim_debug(DEBUG_CONO, dptr, "MT CONO %03o hung PC=%06o\n", dev, PC);
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@ -297,8 +288,6 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
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case DATAI:
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/* Xfer data */
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// if (status & JOB_DONE)
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// mt_df10.buf = 0;
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clr_interrupt(MT_DEVNUM);
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*data = hold_reg;
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uptr->u3 &= ~MT_BUFFUL;
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@ -321,13 +310,7 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
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hold_reg = *data;
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status &= ~DATA_REQUEST;
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clr_interrupt(MT_DEVNUM);
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// if ((uptr->u3 & MT_BRFUL) == 0) {
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// mt_df10.buf = hold_reg;
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// uptr->u3 |= MT_BRFUL;
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// uptr->u3 &= ~MT_BUFFUL;
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// } else {
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uptr->u3 |= MT_BUFFUL;
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// }
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uptr->u3 |= MT_BUFFUL;
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sim_debug(DEBUG_DATA, dptr, "MT %03o <%012llo, %012llo\n",
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dev, hold_reg, mt_df10.buf);
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break;
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@ -352,17 +335,10 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
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case CONO|04:
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if (*data & 1) {
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uptr->u3 |= MT_STOP;
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// if (status & DATA_REQUEST) {
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// status &= ~DATA_REQUEST;
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// clr_interrupt(MT_DEVNUM);
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// }
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sim_debug(DEBUG_DETAIL, dptr, "MT stop %03o\n", dev);
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}
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if (*data & 2) {
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// mt_df10.buf = hold_reg;
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hold_reg ^= mt_df10.buf;
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// hold_reg = 0;
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// mt_df10.buf = 0;
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}
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sim_debug(DEBUG_CONO, dptr, "MT CONO %03o control %o %o %012llo %012llo\n",
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dev, uptr->u3, unit, hold_reg, mt_df10.buf);
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@ -384,6 +360,7 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
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return SCPE_OK;
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}
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/* Wrapper to handle reading of hold register or via DF10 */
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void mt_df10_read(DEVICE *dptr, UNIT *uptr) {
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if (dptr->flags & MTDF_TYPEB) {
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if (!df10_read(&mt_df10)) {
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@ -410,6 +387,7 @@ void mt_df10_read(DEVICE *dptr, UNIT *uptr) {
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uptr->u5 = 0;
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}
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/* Wrapper to handle writing of hold register or via DF10 */
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void mt_df10_write(DEVICE *dptr, UNIT *uptr) {
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if (dptr->flags & MTDF_TYPEB) {
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if (!df10_write(&mt_df10)) {
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@ -669,21 +647,7 @@ t_stat mt_srv(UNIT * uptr)
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uptr->u5++;
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if (uptr->u5 == cc_max) {
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uptr->u5 = 0;
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// if (uptr->u5 & MT_BUFFUL) {
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// if ((dptr->flags & MTDF_TYPEB) == 0) {
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// status |= DATA_REQUEST;
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// set_interrupt(MT_DEVNUM, pia);
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// }
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// uptr->u3 &= ~(MT_BUFFUL);
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// mt_df10.buf = hold_reg;
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// uptr->u3 |= MT_BRFUL;
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// } else {
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uptr->u3 &= ~MT_BRFUL;
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// if ((dptr->flags & MTDF_TYPEB) == 0) {
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// status |= DATA_REQUEST;
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// set_interrupt(MT_DEVNUM, pia);
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// }
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// }
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uptr->u3 &= ~MT_BRFUL;
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}
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status &= ~CHAR_COUNT;
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status |= (uint64)(uptr->u5) << 18;
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@ -701,10 +665,6 @@ t_stat mt_srv(UNIT * uptr)
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uptr->hwmark = 0;
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uptr->u5 = 0;
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uptr->u6 = 0;
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// if ((dptr->flags & MTDF_TYPEB) == 0) {
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// status |= DATA_REQUEST;
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// set_interrupt(MT_DEVNUM, pia);
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// }
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break;
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}
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if ((uptr->u3 & MT_BRFUL) == 0)
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@ -729,21 +689,7 @@ t_stat mt_srv(UNIT * uptr)
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uptr->u5++;
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if (uptr->u5 == cc_max) {
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uptr->u5 = 0;
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// if (uptr->u5 & MT_BUFFUL) {
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// if ((dptr->flags & MTDF_TYPEB) == 0) {
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// status |= DATA_REQUEST;
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// set_interrupt(MT_DEVNUM, pia);
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// }
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// uptr->u3 &= ~(MT_BUFFUL);
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// mt_df10.buf = hold_reg;
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// uptr->u3 |= MT_BRFUL;
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// } else {
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uptr->u3 &= ~MT_BRFUL;
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// if ((dptr->flags & MTDF_TYPEB) == 0) {
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// status |= DATA_REQUEST;
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// set_interrupt(MT_DEVNUM, pia);
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// }
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// }
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uptr->u3 &= ~MT_BRFUL;
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}
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status &= ~CHAR_COUNT;
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status |= (uint64)(uptr->u5) << 18;
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