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mirror of https://github.com/rcornwell/sims.git synced 2026-02-14 19:56:54 +00:00

KA10: Updated card handling and printer.

This commit is contained in:
Richard Cornwell
2019-08-10 16:53:04 -04:00
parent 96221a4e23
commit d2780b441e
4 changed files with 59 additions and 8 deletions

View File

@@ -34,7 +34,7 @@
#include "sim_defs.h"
#if (NUM_DEVS_CP > 0)
#define UNIT_CDP UNIT_ATTABLE | UNIT_DISABLE | MODE_029
#define UNIT_CDP UNIT_ATTABLE | UNIT_DISABLE | MODE_026
#define CP_DEVNUM 0110
@@ -121,6 +121,7 @@ DEVICE cp_dev = {
t_stat cp_devio(uint32 dev, uint64 *data) {
UNIT *uptr = &cp_unit;
uint16 col;
switch(dev & 3) {
case CONI:
@@ -170,7 +171,24 @@ t_stat cp_devio(uint32 dev, uint64 *data) {
*data = 0;
break;
case DATAO:
cp_buffer[uptr->COL++] = *data & 0xfff;
col = *data & 0xfff;
switch(col) {
case 04006: col = 03000; break; /* ! - */
case 01022: col = 00006; break; /* " - */
case 01012: col = 01202; break; /* # - */
case 01006: col = 01042; break; /* % - */
case 02006: col = 05000; break; /* & - */
case 00012: col = 00042; break; /* ' - */
case 03000: col = 00022; break; /* : - */
case 01202: col = 02012; break; /* ; - */
case 02012: col = 00012; break; /* > - */
case 05000: col = 04202; break; /* ? - */
case 02022: col = 04022; break; /* [ - */
case 00006: col = 01012; break; /* \ - */
case 04022: col = 02022; break; /* ] - */
case 00022: col = 00202; break; /* ^ - */
}
cp_buffer[uptr->COL++] = col;
uptr->STATUS &= ~DATA_REQ;
clr_interrupt(dev);
sim_debug(DEBUG_DATAIO, &cp_dev, "CP: DATAO %012llo %d\n", *data,

View File

@@ -34,7 +34,7 @@
#include "sim_defs.h"
#if (NUM_DEVS_CR > 0)
#define UNIT_CDR UNIT_ATTABLE | UNIT_RO | UNIT_DISABLE | MODE_029
#define UNIT_CDR UNIT_ATTABLE | UNIT_RO | UNIT_DISABLE | MODE_029 | MODE_LOWER
#define CR_DEVNUM 0150
@@ -94,7 +94,7 @@ uint16 cr_buffer[80];
DIB cr_dib = { CR_DEVNUM, 1, cr_devio, NULL};
UNIT cr_unit = {
UDATA(cr_srv, UNIT_CDR, 0), 1000,
UDATA(cr_srv, UNIT_CDR, 0), 2000,
};
MTAB cr_mod[] = {
@@ -170,7 +170,9 @@ t_stat cr_devio(uint32 dev, uint64 *data) {
case DATAI:
clr_interrupt(dev);
if (uptr->STATUS & DATA_RDY) {
*data = uptr->DATA;
*data = uptr->DATA & ~RSIGN;
if (uptr->DATA & RSIGN)
*data |= SMASK;
sim_debug(DEBUG_DATAIO, &cr_dev, "CR: DATAI %012llo\n", *data);
uptr->STATUS &= ~DATA_RDY;
} else
@@ -237,6 +239,8 @@ cr_srv(UNIT *uptr) {
/* Copy next column over */
if (uptr->STATUS & CARD_IN_READ) {
uint32 data;
int i;
if (uptr->COL >= 80) {
uptr->STATUS &= ~(CARD_IN_READ|READING);
if (sim_card_input_hopper_count(uptr) == 0)
@@ -246,7 +250,32 @@ cr_srv(UNIT *uptr) {
sim_activate(uptr, uptr->wait);
return SCPE_OK;
}
uptr->DATA = cr_buffer[uptr->COL++];
data = cr_buffer[uptr->COL++];
switch(data) {
case 0x482: data = 0x806; break; /* ! - 12 8 7 */
case 0xA00: data = 0x882; break; /* [ - 12 8 2 */
case 0x882: data = 0x482; break; /* ] - 11 8 2 */
case 0x405: data = 0xa00; break; /* { - 12 0 */
case 0x600: data = 0xc00; break; /* | - 12 11 */
case 0x805: data = 0x600; break; /* } - 11 0 */
case 0x806: data = 0x700; break; /* ~ - 11 0 1 */
}
uptr->DATA = data;
/* Generate upper 18 bits of data */
uptr->DATA |= ((data & 0x001) << 25) |
((data & 0xe00) << 13) |
((data & 0x002) << 20);
for (i = 1; i <= 7; i++) {
if (data & 0x100) {
/* Set flag it more then one punch */
if ((uptr->DATA & 07000000) != 0){
uptr->DATA |= (int32)RSIGN;
break;
}
uptr->DATA |= i << 18;
}
data <<= 1;
}
if (uptr->STATUS & DATA_RDY) {
uptr->STATUS |= DATA_MISS;
}

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@@ -107,7 +107,7 @@ const char *dc_description (DEVICE *dptr);
DIB dc_dib = { DC_DEVNUM, 1, &dc_devio, NULL };
UNIT dc_unit = {
UDATA (&dc_svc, TT_MODE_7B+UNIT_IDLE+UNIT_ATTABLE, 0), KBD_POLL_WAIT
UDATA (&dc_svc, TT_MODE_7B+UNIT_IDLE+UNIT_DISABLE+UNIT_ATTABLE, 0), KBD_POLL_WAIT
};
REG dc_reg[] = {

View File

@@ -40,6 +40,8 @@
#define POS u5
#define LINE u6
#define MARGIN 6
#define UNIT_V_CT (UNIT_V_UF + 0)
#define UNIT_UC (1 << UNIT_V_CT)
#define UNIT_UTF8 (2 << UNIT_V_CT)
@@ -182,9 +184,11 @@ lpt_printline(UNIT *uptr, int nl) {
lpt_buffer[uptr->POS++] = '\n';
uptr->LINE++;
}
if (nl > 0 && uptr->LINE > (int32)uptr->capac) {
if (nl > 0 && uptr->LINE >= ((int32)uptr->capac - MARGIN)) {
lpt_buffer[uptr->POS++] = '\f';
uptr->LINE = 0;
} else if (nl < 0 && uptr->LINE >= (int32)uptr->capac) {
uptr->LINE = 0;
}
sim_fwrite(&lpt_buffer, 1, uptr->POS, uptr->fileref);