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https://github.com/rcornwell/sims.git
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SEL32: Correct SCSI disk initialization code
SEL32: Update sel32_com.c for MPX1X SEL32: Do more general code cleanup
This commit is contained in:
James C. Bevier
parent
252dff6ec7
commit
d9bb3abc46
@ -576,7 +576,6 @@ int32 load_ccw(CHANP *chp, int32 tic_ok)
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/* the disk returns the bad iocl in sw1 */
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chp->ccw_addr = chp->chan_caw & MASK24; /* set the bad IOCL address */
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chp->chan_status |= STATUS_PCHK; /* program check for invalid iocd addr */
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//** uptr->SNS |= SNS_INAD; /* invalid address status */
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return 1; /* error return */
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}
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}
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@ -858,9 +857,11 @@ int chan_write_byte(uint16 chsa, uint8 *data)
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/* see if at end of buffer */
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if (chp->chan_byte == BUFF_CHNEND) { /* check for end of data */
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// sim_debug(DEBUG_EXP, &cpu_dev,
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// "chan_write_byte BUFF_CHNEND ccw_flags %04x addr %06x cnt %04x\n",
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// chp->ccw_flags, chp->ccw_addr, chp->ccw_count);
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#if 0
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_write_byte BUFF_CHNEND ccw_flags %04x addr %06x cnt %04x\n",
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chp->ccw_flags, chp->ccw_addr, chp->ccw_count);
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#endif
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/* if SLI not set, we have incorrect length */
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if ((chp->ccw_flags & FLAG_SLI) == 0) {
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte 4 setting SLI ret\n");
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@ -869,18 +870,21 @@ int chan_write_byte(uint16 chsa, uint8 *data)
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return 1; /* return error */
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}
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if (chp->ccw_count == 0) {
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// sim_debug(DEBUG_EXP, &cpu_dev,
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// "chan_write_byte ZERO chan %04x ccw_count %04x addr %06x\n",
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// chan, chp->ccw_count, chp->ccw_addr);
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#if 0
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_write_byte ZERO chan %04x ccw_count %04x addr %06x\n",
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chan, chp->ccw_count, chp->ccw_addr);
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#endif
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if ((chp->ccw_flags & FLAG_DC) == 0) { /* see if we have data chaining */
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_write_byte no DC ccw_flags %04x\n", chp->ccw_flags);
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chp->chan_status |= STATUS_CEND; /* no, end of data */
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chp->chan_byte = BUFF_CHNEND; /* thats all the data we want */
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// sim_debug(DEBUG_EXP, &cpu_dev,
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// "chan_write_byte BUFF_CHNEND chp %p chan_byte %04x\n",
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// chp, chp->chan_byte);
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#if 0
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_write_byte BUFF_CHNEND chp %p chan_byte %04x\n",
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chp, chp->chan_byte);
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#endif
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return 1; /* return done error */
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} else {
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/* we have data chaining, process iocl */
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@ -890,9 +894,11 @@ int chan_write_byte(uint16 chsa, uint8 *data)
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chp->ccw_count, chp->ccw_addr, chan);
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return 1; /* return error */
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}
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// sim_debug(DEBUG_EXP, &cpu_dev,
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// "chan_write_byte with DC IOCD loaded cnt %04x addr %06x chan %04x\n",
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// chp->ccw_count, chp->ccw_addr, chan);
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#if 0
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_write_byte with DC IOCD loaded cnt %04x addr %06x chan %04x\n",
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chp->ccw_count, chp->ccw_addr, chan);
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#endif
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}
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}
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/* we have data byte to write to chp->ccw_addr */
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@ -900,14 +906,18 @@ int chan_write_byte(uint16 chsa, uint8 *data)
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if (chp->ccw_flags & FLAG_SKIP) {
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chp->ccw_count--; /* decrement skip count */
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chp->chan_byte = BUFF_BUSY; /* busy, but no data */
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// sim_debug(DEBUG_EXP, &cpu_dev,
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// "chan_write_byte1 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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#if 0
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_write_byte1 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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#endif
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if ((chp->ccw_cmd & 0xff) == CMD_RDBWD)
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chp->ccw_addr--; /* backward */
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else
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chp->ccw_addr++; /* forward */
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// sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte SKIP ret addr %08x cnt %04x\n",
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// chp->ccw_addr, chp->ccw_count);
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#if 0
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte SKIP ret addr %08x cnt %04x\n",
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chp->ccw_addr, chp->ccw_count);
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#endif
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return 0;
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}
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chp->chan_buf = *data; /* get data byte */
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@ -916,8 +926,10 @@ int chan_write_byte(uint16 chsa, uint8 *data)
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chp->ccw_count--; /* reduce count */
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chp->chan_byte = BUFF_BUSY; /* busy, but no data */
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// sim_debug(DEBUG_DETAIL, &cpu_dev,
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// "chan_write_byte2 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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#if 0
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sim_debug(DEBUG_DETAIL, &cpu_dev,
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"chan_write_byte2 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte);
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#endif
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if ((chp->ccw_cmd & 0xff) == CMD_RDBWD) /* see if reading backwards */
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chp->ccw_addr -= 1; /* no, use previous address */
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else
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@ -1048,9 +1060,6 @@ void chan_end(uint16 chsa, uint16 flags) {
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} else {
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/* we have channel end and no CC flag, continue channel prog */
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UNIT *uptr = chp->unitptr; /* get the unit ptr */
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// DEVICE *dptr = uptr->dptr; /* get device pointer */
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// int unit = uptr - dptr->units; /* get the UNIT number */
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// DIB *dibp = dib_chan[get_chan(chsa)]; /* get the DIB pointer */
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DEVICE *dptr = get_dev(uptr);
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uint16 chsa = GET_UADDR(uptr->u3);
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int unit = (uptr-dptr->units); /* get the UNIT number */
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@ -1331,10 +1340,6 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
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uint16 chsa;
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uint32 tempa, inta, spadent, chan, incha;
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uint32 word1, word2, cmd;
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#define DEBUG_DISK
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#ifdef DEBUG_DISK
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uint32 itva;
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#endif
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DEVICE *dptr;
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/* get the device entry for the logical channel in SPAD */
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@ -1356,15 +1361,8 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
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}
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}
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chan_icb = find_int_icb(lchsa); /* Interrupt level context block address */
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#ifdef DEBUG_DISK
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itva = SPAD[0xf1] + (inta<<2); /* int vector address */
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chan_icb = RMW(itva); /* Interrupt context block addr */
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iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */
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incha = RMW(chan_icb+20); /* post inch addr in ICB+5w */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"startxio itva %03x icba %04x iocla %06x incha %06x IOCD1 %08x IOCD2 %08x\n",
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itva, chan_icb, iocla, incha, RMW(iocla), RMW(iocla+4));
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#endif
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/* check if we have a valid unit */
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chp = find_chanp_ptr(chsa); /* find the chanp pointer */
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if (chp == 0) goto missing;
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@ -1399,7 +1397,7 @@ missing:
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return SCPE_OK; /* not found, CC3 */
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}
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#ifndef FOR_DEBUG
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#ifdef FOR_DEBUG
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if ((INTS[inta]&INTS_ACT) || (SPAD[inta+0x80]&SINT_ACT)) { /* look for level active */
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/* just output a warning */
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sim_debug(DEBUG_XIO, &cpu_dev,
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@ -1408,7 +1406,6 @@ missing:
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}
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#endif
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#ifndef USE_TIO_CODE_03112021
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/* channel not busy and ready to go, check for any status ready */
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/* see if any status ready to post */
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if (FIFO_Num(chsa&0x7f00)) {
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@ -1441,8 +1438,7 @@ missing:
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return SCPE_OK; /* No CC's all OK */
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}
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}
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#endif
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#ifndef TRY_03132021
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/* check for a Command or data chain operation in progresss */
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if ((chp->chan_byte & BUFF_BUSY) && (chp->chan_byte != BUFF_POST)) {
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uint16 tstat = chp->chan_status; /* save status */
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@ -1452,7 +1448,6 @@ missing:
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sim_debug(DEBUG_EXP, &cpu_dev,
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"startxio busy return CC3&CC4 chsa %04x chp %p cmd %02x flags %04x byte %02x\n",
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chsa, chp, chp->ccw_cmd, chp->ccw_flags, chp->chan_byte);
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#ifndef DISABLE_03112021_03132021
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/* ethernet controller wants an interrupt for busy status */
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if ((dptr != NULL) &&
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(DEV_TYPE(dptr) == DEV_ETHER)) { /* see if this is ethernet */
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@ -1469,8 +1464,6 @@ missing:
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chp, chsa, chp->ccw_flags, tstat, tcnt);
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return SCPE_OK; /* just busy CC3&CC4 */
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}
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#endif
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#ifndef ADD_03112021
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sim_debug(DEBUG_EXP, &cpu_dev,
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"startxio busy2 return CC3&CC4 chsa %04x chp %p cmd %02x flags %04x byte %02x\n",
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chsa, chp, chp->ccw_cmd, chp->ccw_flags, chp->chan_byte);
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@ -1480,9 +1473,7 @@ missing:
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"startxio done2 BUSY chp %p chsa %04x ccw_flags %04x stat %04x cnt %04x\n",
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chp, chsa, chp->ccw_flags, tstat, tcnt);
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return SCPE_OK; /* just busy CC3&CC4 */
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#endif
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}
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#endif /*TRY_03132021*/
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sim_debug(DEBUG_XIO, &cpu_dev,
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"startxio int spad %08x icb %06x inta %02x chan %04x\n",
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@ -1868,7 +1859,6 @@ t_stat rschnlxio(uint16 lchsa, uint32 *status) { /* reset channel XIO */
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dibp->chan_fifo_in = 0; /* reset the FIFO pointers */
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dibp->chan_fifo_out = 0; /* reset the FIFO pointers */
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chp->chan_inch_addr = 0; /* remove inch status buffer address */
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// lev = find_int_lev(chan); /* Interrupt Level for channel */
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INTS[inta] &= ~INTS_ACT; /* clear level active */
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SPAD[inta+0x80] &= ~SINT_ACT; /* clear in spad too */
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@ -1943,13 +1933,11 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
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}
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/* see if interrupt is setup in SPAD and determine IVL for channel */
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// sim_debug(DEBUG_XIO, &cpu_dev, "HIO dev spad %08x lchsa %04x rchsa %04x\n", spadent, lchsa, rchsa);
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sim_debug(DEBUG_EXP, &cpu_dev, "HIO dev spad %08x lchsa %04x rchsa %04x\n", spadent, lchsa, rchsa);
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/* the haltio opcode processing software has already checked for F class */
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inta = ((~spadent)>>16)&0x7f; /* get channel interrupt level */
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chp->chan_int = inta; /* make sure it is set in channel */
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// sim_debug(DEBUG_XIO, &cpu_dev, "HIO int spad %08x inta %02x rchan %02x\n", spadent, inta, rchan);
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sim_debug(DEBUG_EXP, &cpu_dev, "HIO int spad %08x inta %02x rchan %02x\n", spadent, inta, rchan);
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/* get the address of the interrupt IVL in main memory */
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@ -1957,7 +1945,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
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chan_icb = RMW(itva); /* Interrupt context block addr */
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iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */
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// sim_debug(DEBUG_XIO, &cpu_dev,
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sim_debug(DEBUG_EXP, &cpu_dev,
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"$$ HIO busy test byte %02x rchsa %04x cmd %02x ccw_flags %04x IOCD1 %08x IOCD2 %08x\n",
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chp->chan_byte, rchsa, chp->ccw_cmd, chp->ccw_flags, RMW(iocla), RMW(iocla+4));
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@ -2010,7 +1997,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
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"HIO BUFF_DONE2d chp %p chan_byte %04x\n", chp, chp->chan_byte);
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/* the channel is not busy, so return OK */
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*status = CC1BIT; /* request accepted, post good status, so CC1 */
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// sim_debug(DEBUG_CMD, &cpu_dev,
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sim_debug(DEBUG_EXP, &cpu_dev,
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"$$$ HIO END3 rchsa %04x cmd %02x ccw_flags %04x status %04x\n",
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rchsa, chp->ccw_cmd, chp->ccw_flags, *status);
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@ -2037,7 +2023,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
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sim_debug(DEBUG_EXP, &cpu_dev,
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"$$$ HIO END1 not busy return rchsa %04x cmd %02x ccw_flags %04x status %04x\n",
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rchsa, chp->ccw_cmd, chp->ccw_flags, *status);
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#ifndef MAYBE_NOT
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chp->chan_byte = BUFF_DONE; /* we are done */
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chp->chan_status = (STATUS_DEND|STATUS_CEND|STATUS_EXPT);
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store_csw(chp); /* store the status */
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@ -2046,7 +2031,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
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chp->chan_status = 0; /* no status anymore */
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chp->ccw_cmd = 0; /* no command anymore */
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irq_pend = 1; /* flag to test for int condition */
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#endif
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return SCPE_OK; /* CC1 & all OK */
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}
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@ -2170,19 +2154,17 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
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chp = find_chanp_ptr(chsa); /* find the chanp pointer */
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uptr = chp->unitptr; /* get the unit ptr */
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// sim_debug(DEBUG_CMD, &cpu_dev, "rsctlxio 1 chan %04x SPAD %08x\n", chsa, spadent);
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sim_debug(DEBUG_EXP, &cpu_dev, "rsctlxio 1 chan %04x SPAD %08x\n", chsa, spadent);
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if (dibp == 0 || uptr == 0) { /* if no dib or unit ptr, CC3 on return */
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*status = CC3BIT; /* not found, so CC3 */
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return SCPE_OK; /* not found, CC3 */
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}
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// sim_debug(DEBUG_CMD, &cpu_dev, "rsctlxio 2 chan %04x spad %08x\r\n", chsa, spadent);
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sim_debug(DEBUG_EXP, &cpu_dev, "rsctlxio 2 chan %04x spad %08x\r\n", chsa, spadent);
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/* is device or unit marked disabled? */
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dptr = get_dev(uptr); /* get device ptr */
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// if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) { /* is unit attached? */
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/* is device/unit disabled? */
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if ((dptr->flags & DEV_DIS) || (uptr->flags & UNIT_DIS)) {
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/* is device/unit disabled? */
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*status = CC3BIT; /* not enabled, so error CC3 */
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sim_debug(DEBUG_EXP, &cpu_dev,
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"RSCTL rchsa %04x device/unit not enabled, CC3 returned\n", chsa);
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@ -2226,7 +2208,6 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
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if (dibp->rsctl_io != NULL) { /* NULL if no rsctl_io function */
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/* call the device controller to process rsctl */
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j = dibp->rsctl_io(uptr); /* get status from device */
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// sim_debug(DEBUG_CMD, &cpu_dev,
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sim_debug(DEBUG_EXP, &cpu_dev,
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"rsctl_io returned %02x chsa %04x\n", j, chsa);
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}
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@ -2238,7 +2219,6 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
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chp->ccw_flags = 0; /* clear flags */
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chp->ccw_cmd = 0; /* read command */
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}
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// sim_debug(DEBUG_CMD, &cpu_dev, "rsctlxio return CC1 chan %04x lev %04x\n", chan, lev);
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sim_debug(DEBUG_EXP, &cpu_dev, "rsctlxio return CC1 chan %04x lev %04x\n", chan, lev);
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/* returning 0 for status breaks ethernet controller */
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if ((dptr != NULL) &&
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@ -2431,13 +2411,9 @@ uint32 scan_chan(uint32 *ilev) {
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return 0; /* not ready, return */
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}
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#ifndef TEMP_PUTBACK_03172021
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/* see if we are able to look for ints */
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// if (irq_pend == 0) /* pending int? */
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// return 0; /* no, done */
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if (CPUSTATUS & BIT24) /* interrupts blocked? */
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return 0; /* yes, done */
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#endif
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/* ints not blocked, so look for highest requesting interrupt */
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for (i=0; i<112; i++) {
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@ -2767,7 +2743,6 @@ t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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return r; /* number error, return error */
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//printf("Set new dev DEVICE ptr %s chan %04x\r\n", cptr, chan);
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//ZZchan &= 0x7f00; /* clean channel address */
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dibp->chan_addr = chan; /* set new parent channel addr */
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/* change all the unit addresses with the new channel, but keep sub address */
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@ -2780,7 +2755,6 @@ t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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//printf("Got unit %x old chsa %04x\r\n", i, ochsa);
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dib_unit[ochsa] = NULL; /* clear sa dib pointer */
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dib_unit[ochsa&0x7f00] = NULL; /* clear the channel dib address */
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// if (dptr->flags & DEV_CHAN) { /* Is this a channel device IOP/MFP */
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if (ochsa & 0xf0) { /* Is this a channel device IOP/MFP */
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chan &= 0x7ff0; /* clean channel sub-address */
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chsa = chan | (ochsa & 0xf); /* merge new channel with old sa */
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@ -31,10 +31,7 @@
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/* Constants */
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#define COM_LINES 8 /* lines defined */
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#define COM_INIT_POLL 8000
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//#define COML_WAIT 500
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#define COML_WAIT 500
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//#define COM_WAIT 500
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//#define COM_WAIT 5000
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#define COM_WAIT 1000
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#define COM_NUMLIN com_desc.lines /* curr # lines */
|
||||
@ -48,12 +45,6 @@
|
||||
#define COML_REP 0x04 /* rcv enable pend */
|
||||
#define COML_RBP 0x10 /* rcv break pend */
|
||||
|
||||
/* Channel state */
|
||||
#define COMC_IDLE 0 /* idle */
|
||||
#define COMC_INIT 1 /* init */
|
||||
#define COMC_RCV 2 /* receive */
|
||||
#define COMC_END 3 /* end */
|
||||
|
||||
struct _com_data
|
||||
{
|
||||
uint8 incnt; /* char count */
|
||||
@ -64,10 +55,6 @@ com_data[COM_LINES];
|
||||
uint8 com_rbuf[COM_LINES]; /* rcv buf */
|
||||
uint8 com_xbuf[COM_LINES]; /* xmt buf */
|
||||
uint8 com_stat[COM_LINES]; /* status */
|
||||
uint32 com_lstat[COM_LINES][2] = { 0 }; /* 8 bytes of line settings status */
|
||||
uint32 com_sns[COM_LINES] = { 0 }; /* 4 bytes of line settings status */
|
||||
uint32 com_ace[COM_LINES] = { 0 }; /* 4 bytes of ACE settings */
|
||||
uint32 comi_cmd = COMC_IDLE; /* channel state */
|
||||
|
||||
TMLN com_ldsc[COM_LINES] = { 0 }; /* line descrs */
|
||||
TMXR com_desc = { COM_LINES, 0, 0, com_ldsc }; /* com descr */
|
||||
@ -252,7 +239,7 @@ const char *com_description(DEVICE *dptr); /* device description */
|
||||
com_dev COM device descriptor
|
||||
com_unit COM unit descriptor
|
||||
com_reg COM register list
|
||||
com_mod COM modifieers list
|
||||
com_mod COM modifiers list
|
||||
*/
|
||||
|
||||
//#define COM_UNITS 2
|
||||
@ -309,8 +296,7 @@ DEVICE com_dev = {
|
||||
COM_UNITS, 8, 15, 1, 8, 8,
|
||||
&tmxr_ex, &tmxr_dep, &com_reset, NULL, &com_attach, &com_detach,
|
||||
/* ctxt is the DIB pointer */
|
||||
&com_dib, DEV_NET|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
|
||||
// &com_dib, DEV_NET|DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
|
||||
&com_dib, DEV_MUX|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
|
||||
NULL, NULL, NULL, NULL, NULL, &com_description
|
||||
};
|
||||
|
||||
@ -318,7 +304,7 @@ DEVICE com_dev = {
|
||||
coml_dev COM device descriptor
|
||||
coml_unit COM unit descriptor
|
||||
coml_reg COM register list
|
||||
coml_mod COM modifieers list
|
||||
coml_mod COM modifiers list
|
||||
*/
|
||||
|
||||
/*#define UNIT_COML UNIT_ATTABLE|UNIT_DISABLE|UNIT_IDLE */
|
||||
@ -398,16 +384,12 @@ DEVICE coml_dev = {
|
||||
NULL, NULL, NULL,
|
||||
/* ctxt is the DIB pointer */
|
||||
&coml_dib, DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
|
||||
// &coml_dib, DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
|
||||
NULL, NULL, NULL, NULL, NULL, &com_description
|
||||
};
|
||||
|
||||
/* 8-line serial routines */
|
||||
void coml_ini(UNIT *uptr, t_bool f)
|
||||
{
|
||||
/* maybe do something here on master channel init */
|
||||
// uptr->SNS = 0; /* status is online & ready */
|
||||
//1Xuptr->SNS = 0x00003003; /* status is online & ready */
|
||||
/* set SNS_RLSDS SNS_DSRS SNS_CTSS SNS_RTS SNS_CTS */
|
||||
uptr->SNS = 0x0000b003; /* status is online & ready */
|
||||
uptr->CMD &= LMASK; /* leave only chsa */
|
||||
@ -454,7 +436,6 @@ t_stat coml_preio(UNIT *uptr, uint16 chan) {
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
int unit = (uptr - dptr->units);
|
||||
uint16 chsa = GET_UADDR(uptr->CMD); /* get channel/sub-addr */
|
||||
// int cmd = coml_chp[unit].ccw_cmd;
|
||||
UNIT *ruptr = &dptr->units[unit&7]; /* read uptr */
|
||||
UNIT *wuptr = &dptr->units[(unit&7)+8]; /* write uptr */
|
||||
|
||||
@ -516,7 +497,7 @@ t_stat coml_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
"coml_startcmd chsa %04x: Cmd WRITE %02x\n", chsa, cmd);
|
||||
|
||||
/* see if DSR is set, if not give unit check error */
|
||||
if (((ruptr->SNS & SNS_DSRS) == 0)|| ((ruptr->SNS & SNS_CONN) == 0)) {
|
||||
if (((ruptr->SNS & SNS_DSRS) == 0) || ((ruptr->SNS & SNS_CONN) == 0)) {
|
||||
//YY if ((com_ldsc[unit&7].conn == 0) ||
|
||||
ruptr->SNS &= ~SNS_RDY; /* status is not ready */
|
||||
wuptr->SNS &= ~SNS_RDY; /* status is not ready */
|
||||
@ -550,7 +531,7 @@ t_stat coml_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
case COM_RDHFC: /* 0x8E */ /* Read command w/hardware flow control only */
|
||||
|
||||
/* see if DSR is set, if not give unit check error */
|
||||
if (((ruptr->SNS & SNS_DSRS) == 0)|| ((ruptr->SNS & SNS_CONN) == 0)) {
|
||||
if (((ruptr->SNS & SNS_DSRS) == 0) || ((ruptr->SNS & SNS_CONN) == 0)) {
|
||||
//XX if (com_ldsc[unit&7].conn == 0) {
|
||||
ruptr->SNS &= ~SNS_RDY; /* status is not ready */
|
||||
wuptr->SNS &= ~SNS_RDY; /* status is not ready */
|
||||
@ -595,8 +576,6 @@ t_stat coml_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
|
||||
case COM_SNS: /* 0x04 */ /* Sense (8 bytes) */
|
||||
unit &= 0x7; /* make unit 0-7 */
|
||||
com_lstat[unit][0] = 0; /* Clear status wd 0 */
|
||||
com_lstat[unit][1] = 0; /* Clear status wd 1 */
|
||||
/* status is in SNS (u5) */
|
||||
/* ACE is in ACE (u4) */
|
||||
///*MPX*/ uptr->SNS = 0x03813401;
|
||||
@ -607,47 +586,35 @@ t_stat coml_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
|
||||
/* byte 0 device status */
|
||||
ch = (uptr->SNS >> 24) & 0xff; /* no bits in byte 0 */
|
||||
// ch = (com_lstat[unit][0] >> 24) & 0xff;
|
||||
chan_write_byte(chsa, &ch); /* write status */
|
||||
|
||||
/* byte 1 line status and error conditions */
|
||||
ch = (uptr->SNS >> 16) & 0xff; /* no bits in byte 1 */
|
||||
// com_lstat[unit][0] |= (SNS_RING); /* set char detect status */
|
||||
// com_lstat[unit][0] |= (SNS_ASCIICD); /* set char detect status */
|
||||
// ch = (com_lstat[unit][0] >> 16) & 0xff;
|
||||
chan_write_byte(chsa, &ch); /* write status */
|
||||
|
||||
/* byte 2 modem status */
|
||||
// com_lstat[unit][0] |= (SNS_CTSS|SNS_DSRS); /* set CTS & DSR status */
|
||||
// com_lstat[unit][0] |= (SNS_MRING); /* set char detect status */
|
||||
// SNS_DELDSR will be set if just connected, clear at end
|
||||
ch = (uptr->SNS >> 8) & 0xff; /* CTS & DSR bits in byte 2 */
|
||||
chan_write_byte(chsa, &ch); /* write status */
|
||||
|
||||
/* byte 3 modem control/operation mode */
|
||||
// com_lstat[unit][0] |= (SNS_DTR); /* set DTR status */
|
||||
// ch = (com_lstat[unit][0]) & 0xff; /* set current status */
|
||||
ch = uptr->SNS & 0xff; /* maybe DTR bit in byte 3 */
|
||||
chan_write_byte(chsa, &ch); /* write status */
|
||||
|
||||
/* byte 4 ACE byte 0 parameters (parity, stop bits, char len */
|
||||
// ch = (com_lstat[unit][1] >> 24) & 0xff;
|
||||
ch = (uptr->ACE >> 24) & 0xff; /* ACE byte 0 */
|
||||
chan_write_byte(chsa, &ch); /* write status */
|
||||
|
||||
/* byte 5 ACE byte 1 parameters (baud rate) */
|
||||
// ch = (com_lstat[unit][1] >> 16) & 0xff;
|
||||
ch = (uptr->ACE >> 16) & 0xff; /* ACE byte 1 */
|
||||
chan_write_byte(chsa, &ch); /* write status */
|
||||
|
||||
/* byte 6 ACE parameters (Firmware ID 0x62) */
|
||||
// ch = (com_lstat[unit][1] >> 8) & 0xff;
|
||||
ch = 0x62; /* ACE IOP firmware byte 0 */
|
||||
// ch = 0x19; /* ACE MFP firmware byte 0 */
|
||||
chan_write_byte(chsa, &ch); /* write status */
|
||||
|
||||
/* byte 7 ACE parameters (Revision Level 0x4?) */
|
||||
// ch = (com_lstat[unit][1] >> 0) & 0xff;
|
||||
// Firmware 0x44 supports RTS flow control */
|
||||
// Firmware 0x45 supports DCD modem control */
|
||||
// ch = 0x44; /* ACE firmware byte 1 */
|
||||
@ -690,7 +657,6 @@ t_stat coml_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
uptr->ACE |= ((uint32)ch << 8); /* insert special char */
|
||||
ruptr->ACE = uptr->ACE; /* set special char in read unit */
|
||||
wuptr->ACE = uptr->ACE; /* set special char in write unit */
|
||||
// uptr->CMD = ~SNS_RTS; /* Request to send not ready */
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"coml_startcmd chsa %04x: Cmd %02x DEFSC char %02x SNS %08x ACE %08x\n",
|
||||
chsa, cmd, ch, uptr->SNS, uptr->ACE);
|
||||
@ -733,45 +699,6 @@ t_stat coml_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
|
||||
#if 0
|
||||
/* ACE byte 0 Modem Control/Operation status */
|
||||
/* stored in u4 bytes 0-3 */
|
||||
#define SNS_HALFD 0x80000000 /* Half-duplix operation set */
|
||||
#define SNS_MRINGE 0x40000000 /* Modem ring enabled */
|
||||
#define SNS_ACEFP 0x20000000 /* Forced parity 0=odd, 1=even */
|
||||
#define SNS_ACEP 0x10000000 /* Parity 0=odd, 1=even */
|
||||
#define SNS_ACEPE 0x08000000 /* Parity enable 0=dis, 1=enb */
|
||||
#define SNS_ACESTOP 0x04000000 /* Stop bit 0=1, 1=1.5 or 2 */
|
||||
#define SNS_ACECLEN 0x02000000 /* Character length 00=5, 01=6, 10=7, 11=8 */
|
||||
#define SNS_ACECL2 0x01000000 /* 2nd bit for above */
|
||||
|
||||
/* ACE byte 1 Baud rate */
|
||||
#define SNS_NUB50 0x00800000 /* Zero N/U */
|
||||
#define SNS_NUB51 0x00400000 /* Zero N/U */
|
||||
#define SNS_RINGCR 0x00200000 /* Ring or wakeup character recognition 0=enb, 1=dis */
|
||||
#define SNS_DIAGL 0x00100000 /* Set diagnostic loopback */
|
||||
#define SNS_BAUD 0x000F0000 /* Baud rate bits 4-7 */
|
||||
#define BAUD50 0x00000000 /* 50 baud */
|
||||
#define BAUD75 0x00010000 /* 75 baud */
|
||||
#define BAUD110 0x00020000 /* 110 baud */
|
||||
#define BAUD114 0x00030000 /* 134 baud */
|
||||
#define BAUD150 0x00040000 /* 150 baud */
|
||||
#define BAUD300 0x00050000 /* 300 baud */
|
||||
#define BAUD600 0x00060000 /* 600 baud */
|
||||
#define BAUD1200 0x00070000 /* 1200 baud */
|
||||
#define BAUD1800 0x00080000 /* 1800 baud */
|
||||
#define BAUD2000 0x00090000 /* 2000 baud */
|
||||
#define BAUD2400 0x000A0000 /* 2400 baud */
|
||||
#define BAUD3600 0x000B0000 /* 3600 baud */
|
||||
#define BAUD4800 0x000C0000 /* 4800 baud */
|
||||
#define BAUD7200 0x000D0000 /* 7200 baud */
|
||||
#define BAUD9600 0x000E0000 /* 9600 baud */
|
||||
#define BAUD19200 0x000F0000 /* 19200 baud */
|
||||
|
||||
/* ACE byte 2 Wake-up character */
|
||||
#define ACE_WAKE 0x0000FF00 /* 8 bit wake-up character */
|
||||
#endif
|
||||
|
||||
case COM_SACE: /* 0xff */ /* Set ACE parameters (3 chars) */
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"coml_startcmd chsa %04x: Cmd %02x SACE\n", chsa, cmd);
|
||||
@ -970,15 +897,8 @@ t_stat comc_srv(UNIT *uptr)
|
||||
ch = sim_tt_inpcvt(ch, TT_GET_MODE(coml_unit[ln].flags));
|
||||
com_rbuf[ln] = ch; /* save char */
|
||||
|
||||
#if 1
|
||||
/* Special char detect? */
|
||||
if ((ch & 0x7f) == ((nuptr->ACE >> 8) & 0xff)) { /* is it spec char */
|
||||
#if 0
|
||||
if (cmd == 0) {
|
||||
nuptr->CNT = 0; /* no I/O yet */
|
||||
com_data[ln].incnt = 0; /* no input data */
|
||||
}
|
||||
#endif
|
||||
nuptr->CMD |= COM_SCD; /* set special char detected */
|
||||
nuptr->SNS |= SNS_SPCLCD; /* set special char detected */
|
||||
// nuptr->SNS |= SNS_RLSDS; /* set rec'd line signal detect */
|
||||
@ -989,7 +909,6 @@ t_stat comc_srv(UNIT *uptr)
|
||||
set_devwake(chsa, SNS_ATTN|SNS_DEVEND|SNS_CHNEND);
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* put char in buffer */
|
||||
com_data[ln].ibuff[com_data[ln].incnt++] = ch;
|
||||
|
||||
@ -1705,7 +1705,8 @@ t_stat Mem_write(uint32 addr, uint32 *data)
|
||||
case 0x0: case 0x2: case 0x6: case 0xa: case 0xe:
|
||||
/* O/S or user has read/execute access, do protection violation */
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"Mem_writeA protect error @ %06x prot %02x modes %08x\n", addr, prot, MODES);
|
||||
"Mem_writeA protect error @ %06x prot %02x modes %08x\n",
|
||||
addr, prot, MODES);
|
||||
if (CPU_MODEL == MODEL_V9)
|
||||
TRAPSTATUS |= BIT1; /* set bit 1 of trap status */
|
||||
else
|
||||
@ -1714,7 +1715,8 @@ t_stat Mem_write(uint32 addr, uint32 *data)
|
||||
case 0x4: case 0x8: case 0xc:
|
||||
/* O/S or user has write access, no protection violation */
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"Mem_writeB protect is ok @ %06x prot %02x modes %08x\n", addr, prot, MODES);
|
||||
"Mem_writeB protect is ok @ %06x prot %02x modes %08x\n",
|
||||
addr, prot, MODES);
|
||||
}
|
||||
map = RMR((page<<1)); /* read the map reg contents */
|
||||
raddr = TLB[page]; /* get the base address & bits */
|
||||
@ -1868,18 +1870,6 @@ wait_loop:
|
||||
return reason;
|
||||
break;
|
||||
}
|
||||
#ifdef XXX
|
||||
else {
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
"Process Event other reason %08x interval %08x\n",
|
||||
reason, sim_interval);
|
||||
reason = STOP_IBKPT;
|
||||
sim_interval= 0; /* count down */
|
||||
break;
|
||||
//JB return reason;
|
||||
//JB break; /* process */
|
||||
}
|
||||
#else
|
||||
else {
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
"Process Event other reason %08x interval %08x\n",
|
||||
@ -1887,7 +1877,6 @@ wait_loop:
|
||||
return reason;
|
||||
break; /* process */
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@ -2947,7 +2936,6 @@ exec:
|
||||
/* 7 - Read & Lock Enabled (=1)/Disabled (=0) */
|
||||
/* 8-12 - Lower Bound of Shared Memory */
|
||||
/* 3-31 - Reserved and must be zero */
|
||||
// sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_CMD, &cpu_dev,
|
||||
"SMC V6/67 GPR[%02x] = %08x SMCR = %08x CPU STATUS SPAD[f9] = %08x\n",
|
||||
reg, GPR[reg], SMCR, SPAD[0xf9]);
|
||||
@ -6495,18 +6483,22 @@ sim_debug(DEBUG_IRQ, &cpu_dev,
|
||||
/* insert status CCs */
|
||||
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000));
|
||||
} else {
|
||||
#if 0
|
||||
/* may want to handle class E someday */
|
||||
// if ((TRAPME = testEIO(device, testcode, &status)))
|
||||
// goto newpsd; /* error returned, trap cpu */
|
||||
if ((TRAPME = testEIO(device, testcode, &status)))
|
||||
goto newpsd; /* error returned, trap cpu */
|
||||
/* return status has new CC's in bits 1-4 of status word */
|
||||
// /* insert status CCs */
|
||||
// PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000));
|
||||
/* insert status CCs */
|
||||
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000));
|
||||
#endif
|
||||
goto inv; /* invalid instruction until I fix it */
|
||||
}
|
||||
} else {
|
||||
/* TODO process a CD */
|
||||
// if ((TRAPME = startEIO(device, &status)))
|
||||
// goto newpsd; /* error returned, trap cpu */
|
||||
#if 0
|
||||
if ((TRAPME = startEIO(device, &status)))
|
||||
goto newpsd; /* error returned, trap cpu */
|
||||
#endif
|
||||
if (device == 0x7f) {
|
||||
temp = (IR & 0x7f); /* get cmd from instruction */
|
||||
status = itm_rdwr(temp, GPR[0], ix); /* read/write the interval timer */
|
||||
@ -7348,7 +7340,7 @@ t_stat cpu_ex(t_value *vptr, t_addr baddr, UNIT *uptr, int32 sw)
|
||||
sim_debug(DEBUG_CMD, &cpu_dev, "cpu_ex Mem_read status = %02x\n", status);
|
||||
if (status == ALLOK) {
|
||||
*vptr = (M[realaddr] >> (8 * (3 - (baddr & 0x3)))); /* return memory contents */
|
||||
return SCPE_OK; /* we are all ok */
|
||||
return SCPE_OK; /* we are all ok */
|
||||
}
|
||||
return SCPE_NXM; /* no, none existant memory error */
|
||||
}
|
||||
|
||||
@ -673,7 +673,6 @@ uint32 get_dmatrk(UNIT *uptr, uint32 star, uint8 buf[])
|
||||
/* get the alternate track address */
|
||||
cyl = (buf[22] << 8) | buf[23]; /* get the cylinder */
|
||||
trk = buf[24]; /* get the track */
|
||||
//bad sec = 0; /* sec is zero */
|
||||
nstar = CHS2STAR(cyl, trk, sec);
|
||||
sim_debug(DEBUG_DETAIL, dptr,
|
||||
"Track %08x is defective, new track %08x\n", tstart, nstar);
|
||||
@ -942,9 +941,7 @@ loop:
|
||||
sim_debug(DEBUG_EXP, dptr,
|
||||
"disk_iocl continue wait chsa %04x status %08x\n",
|
||||
chp->chan_dev, chp->chan_status);
|
||||
#ifndef CHANGE_03072021
|
||||
chp->chan_qwait = QWAIT; /* run 25 instructions before starting iocl */
|
||||
#endif
|
||||
}
|
||||
} else
|
||||
|
||||
@ -1279,7 +1276,6 @@ t_stat disk_srv(UNIT *uptr)
|
||||
} else
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
|
||||
break;
|
||||
@ -1310,7 +1306,6 @@ t_stat disk_srv(UNIT *uptr)
|
||||
uptr->SNS2 |= (SNS_SKER|SNS_SEND);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK); /* error */
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1494,7 +1489,6 @@ iha_error:
|
||||
/* TODO add drive status bits here */
|
||||
if ((test_write_byte_end(chsa)) == 0) {
|
||||
/* bytes 12 & 13 contain drive related status */
|
||||
// ch = 0xc0; /* seek end and unit selected for now */
|
||||
uptr->SNS2 |= (SNS_SEND|SNS_USEL); /* selected & seek end */
|
||||
/* bits 2-7 have sector pulse count */
|
||||
ch = ((sec * 2) % SPT(type)) & 0x3f;/* get index cnt */
|
||||
@ -1664,7 +1658,6 @@ iha_error:
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Check if already on correct cylinder */
|
||||
@ -1697,7 +1690,6 @@ iha_error:
|
||||
chan_end(chsa, SNS_DEVEND|SNS_CHNEND);
|
||||
}
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
|
||||
case DSK_XEZ: /* 0x37 */ /* Rezero & Read IPL record */
|
||||
sim_debug(DEBUG_CMD, dptr, "XEZ REZERO IPL unit=%02x seek 0\n", unit);
|
||||
@ -1714,13 +1706,11 @@ iha_error:
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
/* we are on cylinder/track/sector zero, so go on */
|
||||
sim_debug(DEBUG_DETAIL, dptr, "disk_srv done seek trk 0\n");
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_DEVEND|SNS_CHNEND);
|
||||
// return SCPE_OK;
|
||||
break;
|
||||
|
||||
case DSK_LMR: /* 0x1F */
|
||||
@ -1767,7 +1757,6 @@ iha_error:
|
||||
if (len <= 1) {
|
||||
uptr->SNS |= SNS_CMDREJ; /* cmd rejected */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
|
||||
// return SCPE_OK;
|
||||
break;
|
||||
}
|
||||
/* Read in 2-4 character tess code */
|
||||
@ -1785,7 +1774,6 @@ iha_error:
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
|
||||
else
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
|
||||
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
|
||||
return SCPE_OK;
|
||||
break;
|
||||
}
|
||||
@ -1820,7 +1808,6 @@ iha_error:
|
||||
unit, buf[0], buf[1], buf[2], buf[3]);
|
||||
|
||||
chan_end(chsa, tstart);
|
||||
// return SCPE_OK;
|
||||
break;
|
||||
|
||||
case DSK_FNSK: /* 0x0B Format for no skip */
|
||||
@ -1851,7 +1838,6 @@ iha_error:
|
||||
}
|
||||
sim_debug(DEBUG_DETAIL, dptr, "\n");
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
|
||||
// return SCPE_OK;
|
||||
break;
|
||||
|
||||
case DSK_RD: /* Read Data command 0x02 */
|
||||
@ -1910,7 +1896,6 @@ iha_error:
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
@ -1939,7 +1924,6 @@ iha_error:
|
||||
uptr->CHS++; /* next sector number */
|
||||
/* process the next sector of data */
|
||||
for (i=0; i<len; i++) {
|
||||
//0906 for (i=0; i<ssize; i++) {
|
||||
ch = buf[i]; /* get a char from buffer */
|
||||
if (chan_write_byte(chsa, &ch)) { /* put a byte to memory */
|
||||
if (chp->chan_status & STATUS_PCHK) /* test for memory error */
|
||||
@ -2010,7 +1994,6 @@ iha_error:
|
||||
ssize, chp->ccw_count, chp->ccw_addr,
|
||||
((uptr->CHS)>>16)&0xffff, ((uptr->CHS)>>8)&0xff, (uptr->CHS)&0xff);
|
||||
|
||||
//// uptr->CHS++; /* next sector number */
|
||||
/* get sector offset */
|
||||
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
|
||||
|
||||
@ -2094,7 +2077,6 @@ iha_error:
|
||||
|
||||
uptr->SNS &= ~SNS_DEFTRK; /* remove defective flag */
|
||||
/* see if spare track */
|
||||
//was if (lbuf[4] & 0x30) { /* see if spare or reserved track */
|
||||
if (lbuf[4] & 0x20) { /* see if spare track */
|
||||
uptr->SNS |= SNS_DADE; /* disk addr error */
|
||||
chp->chan_status |= STATUS_PCHK; /* channel prog check */
|
||||
@ -2370,7 +2352,6 @@ iha_error:
|
||||
/* Write sector label to disk */
|
||||
/* write 30 bytes, b0-b1=cyl, b1=trk, b2=sec */
|
||||
len = chp->ccw_count; /* get number bytes to read */
|
||||
// mema = uptr->CHS+(len/30); /* save address */
|
||||
mema = uptr->CHS; /* save address */
|
||||
|
||||
sim_debug(DEBUG_DETAIL, dptr, "before WSL Sector %x len %x\n", uptr->CHS, len);
|
||||
@ -2406,7 +2387,6 @@ iha_error:
|
||||
chp->ccw_count = len; /* restore number bytes to read */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
|
||||
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_LENGTH);
|
||||
return SCPE_OK;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -795,7 +795,6 @@ uint32 get_dpatrk(UNIT *uptr, uint32 star, uint8 buf[])
|
||||
/* get the alternate track address */
|
||||
cyl = (buf[22] << 8) | buf[23]; /* get the cylinder */
|
||||
trk = buf[24]; /* get the track */
|
||||
//bad sec = 0; /* sec is zero */
|
||||
nstar = CHS2STAR(cyl, trk, sec);
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"Track %08x is defective, new track %08x\n", tstart, nstar);
|
||||
@ -961,7 +960,6 @@ loop:
|
||||
"hsdp_iocl tic cmd bad address chan %02x tic caw %06x IOCD wd 1 %08x\n",
|
||||
chan, chp->chan_caw, word1);
|
||||
chp->chan_status |= STATUS_PCHK; /* program check for invalid tic */
|
||||
// chp->chan_caw = word1; /* get new IOCD address */
|
||||
chp->chan_caw = word1 & MASK24; /* get new IOCD address */
|
||||
uptr->SNS |= SNS_CMDREJ; /* cmd rejected status */
|
||||
uptr->SNS |= SNS_INAD; /* invalid address status */
|
||||
@ -974,7 +972,6 @@ loop:
|
||||
chan, chp->chan_caw, word1);
|
||||
goto loop; /* restart the IOCD processing */
|
||||
}
|
||||
// chp->chan_caw = word1; /* get new IOCD address */
|
||||
chp->chan_caw = word1 & MASK24; /* get new IOCD address */
|
||||
chp->chan_status |= STATUS_PCHK; /* program check for invalid tic */
|
||||
uptr->SNS |= SNS_CMDREJ; /* cmd rejected status */
|
||||
@ -1066,9 +1063,7 @@ loop:
|
||||
sim_debug(DEBUG_EXP, dptr,
|
||||
"hsdp_iocl continue wait chsa %04x status %08x\n",
|
||||
chp->chan_dev, chp->chan_status);
|
||||
#ifndef CHANGE_03072021
|
||||
chp->chan_qwait = QWAIT; /* run 25 instructions before starting iocl */
|
||||
#endif
|
||||
}
|
||||
} else
|
||||
|
||||
@ -1250,7 +1245,6 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
{
|
||||
uint16 chsa = GET_UADDR(uptr->CMD);
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
// UNIT *uptr0 = dptr->units; /* get unit 0 pointer */
|
||||
CHANP *chp = find_chanp_ptr(chsa); /* get channel prog pointer */
|
||||
int cmd = uptr->CMD & DSK_CMDMSK;
|
||||
int type = GET_TYPE(uptr->flags);
|
||||
@ -1485,7 +1479,6 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
} else
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
|
||||
break;
|
||||
@ -1516,7 +1509,6 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
uptr->SNS2 |= (SNS_SKER|SNS_SEND);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK); /* error */
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1547,7 +1539,6 @@ iha_error:
|
||||
sim_debug(DEBUG_EXP, dptr, "hsdp_srv IHA error on seek to %04x\n", tstart);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
|
||||
break;
|
||||
@ -1666,7 +1657,6 @@ iha_error:
|
||||
if ((trk == (hsdp_type[type].nhds-1)) && /* see if last trk */
|
||||
((cyl == hsdp_type[type].cyl-1)) && /* see if last cyl */
|
||||
(sec == 0)) { /* sec is zero */
|
||||
// ch = 0xff; /* show last track */
|
||||
ch = 0; /* show last track */
|
||||
}
|
||||
#endif
|
||||
@ -1719,7 +1709,6 @@ iha_error:
|
||||
/* TODO add drive status bits here */
|
||||
if ((test_write_byte_end(chsa)) == 0) {
|
||||
/* bytes 12 & 13 contain drive related status */
|
||||
// ch = 0xc0; /* seek end and unit selected for now */
|
||||
uptr->SNS2 |= (SNS_SEND|SNS_USEL); /* selected & seek end */
|
||||
/* bits 2-7 have sector pulse count */
|
||||
ch = ((sec * 2) % SPT(type)) & 0x3f;/* get index cnt */
|
||||
@ -1730,7 +1719,6 @@ iha_error:
|
||||
chan_write_byte(chsa, &ch);
|
||||
|
||||
ch = 0x30; /* drive on cylinder and ready for now */
|
||||
// uptr->SNS2 &= ~uptr->SNS2; /* clean out old status */
|
||||
uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */
|
||||
ch = uptr->SNS2 & 0xff; /* drive on cylinder and ready for now */
|
||||
sim_debug(DEBUG_CMD, dptr, "hsdp_srv dsr unit=%02x 2 %02x\n",
|
||||
@ -1738,7 +1726,6 @@ iha_error:
|
||||
chan_write_byte(chsa, &ch);
|
||||
}
|
||||
uptr->SNS &= 0xff000000; /* reset status */
|
||||
//28 uptr->SNS2 = (SNS_UNR|SNS_ONC); /* reset status to on cyl & ready */
|
||||
uptr->SNS2 = 0; /* reset status */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
|
||||
@ -1759,7 +1746,6 @@ iha_error:
|
||||
/* we have already seeked to the required sector */
|
||||
/* we do not need to seek again, so move on */
|
||||
chan_end(chsa, SNS_DEVEND|SNS_CHNEND);
|
||||
// return SCPE_OK;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1809,7 +1795,6 @@ iha_error:
|
||||
}
|
||||
}
|
||||
}
|
||||
//0106 chp->ccw_count = len; /* restore count for diag, huh? */
|
||||
/* else the cyl, trk, and sect are ready to update */
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"hsdp_srv STAR unit=%02x star %02x %02x %02x %02x\n",
|
||||
@ -1850,7 +1835,6 @@ iha_error:
|
||||
/* Check if seek valid */
|
||||
if (cyl >= hsdp_type[type].cyl ||
|
||||
trk >= hsdp_type[type].nhds ||
|
||||
//0118 buf[3] >= hsdp_type[type].spt) {
|
||||
buf[3] >= uptr->LSC) {
|
||||
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
@ -1870,7 +1854,6 @@ iha_error:
|
||||
}
|
||||
|
||||
/* get alternate track if this one is defective */
|
||||
//sim_debug(DEBUG_CMD, dptr, "Dpatrk2 %08x label\n", tempt);
|
||||
tempt = get_dpatrk(uptr, tstar, lbuf);
|
||||
|
||||
if ((tempt == 0) && (tstar != 0)) {
|
||||
@ -1898,7 +1881,6 @@ iha_error:
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
|
||||
/* do a delay to slow things down */
|
||||
@ -1924,7 +1906,6 @@ iha_error:
|
||||
// sim_activate(uptr, 400+k); /* start us off */
|
||||
#endif
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
|
||||
case DSK_XEZ: /* 0x37 */ /* Rezero & Read IPL record */
|
||||
|
||||
@ -1941,13 +1922,11 @@ iha_error:
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
/* we are on cylinder/track/sector zero, so go on */
|
||||
sim_debug(DEBUG_CMD, dptr, "hsdp_srv done seek trk 0\n");
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_DEVEND|SNS_CHNEND);
|
||||
// return SCPE_OK;
|
||||
break;
|
||||
|
||||
case DSK_LMR: /* 0x1F */
|
||||
@ -1986,7 +1965,6 @@ iha_error:
|
||||
/* now read sector label data */
|
||||
len = chp->ccw_count;
|
||||
for (i = 0; i < len; i++) {
|
||||
//0906 for (i = 0; i < 30; i++) {
|
||||
if (chan_read_byte(chsa, &buf[i])) {
|
||||
if (chp->chan_status & STATUS_PCHK) /* test for memory error */
|
||||
uptr->SNS |= SNS_INAD; /* invalid address */
|
||||
@ -2002,8 +1980,6 @@ iha_error:
|
||||
}
|
||||
sim_debug(DEBUG_CMD, dptr, "\n");
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
|
||||
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
// return SCPE_OK;
|
||||
break;
|
||||
|
||||
case DSK_RD: /* Read Data */
|
||||
@ -2021,7 +1997,6 @@ iha_error:
|
||||
uptr->CHS = hsdpsec2star(tstart, type);
|
||||
|
||||
/* get alternate track if this one is defective */
|
||||
//sim_debug(DEBUG_CMD, dptr, "Dpatrk3 %08x label\n", uptr->CHS);
|
||||
tempt = get_dpatrk(uptr, uptr->CHS, lbuf);
|
||||
/* file offset in bytes to std or alt track */
|
||||
tstart = STAR2SEC(tempt, SPT(type), SPC(type)) * SSB(type);
|
||||
@ -2051,7 +2026,6 @@ iha_error:
|
||||
/* see if reserved track */
|
||||
if (lbuf[4] & 0x10) { /* see if reserved track */
|
||||
uptr->SNS |= SNS_MOCK; /* mode check error */
|
||||
// uptr->SNS |= SNS_RTAE; /* reserved track access error */
|
||||
uptr->SNS |= SNS_RES8; /* reserved track access error */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
|
||||
@ -2064,7 +2038,6 @@ iha_error:
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
// return SCPE_OK;
|
||||
}
|
||||
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
@ -2246,7 +2219,6 @@ iha_error:
|
||||
tstart = tstart * SSB(type);
|
||||
|
||||
/* get alternate track if this one is defective */
|
||||
//sim_debug(DEBUG_CMD, dptr, "Dpatrk4 %08x label\n", uptr->CHS);
|
||||
tempt = get_dpatrk(uptr, uptr->CHS, lbuf);
|
||||
/* file offset in bytes to std or alt track */
|
||||
tstart = STAR2SEC(tempt, SPT(type), SPC(type)) * SSB(type);
|
||||
@ -2265,7 +2237,6 @@ iha_error:
|
||||
|
||||
uptr->SNS &= ~SNS_DEFTRK; /* remove defective flag */
|
||||
/* see if spare track */
|
||||
//was if (lbuf[4] & 0x30) { /* see if spare or reserved track */
|
||||
if (lbuf[4] & 0x20) { /* see if spare track */
|
||||
uptr->SNS |= SNS_DADE; /* disk addr error */
|
||||
chp->chan_status |= STATUS_PCHK; /* channel prog check */
|
||||
@ -2276,7 +2247,6 @@ iha_error:
|
||||
/* see if reserved track */
|
||||
if (lbuf[4] & 0x10) { /* see if reserved track */
|
||||
uptr->SNS |= SNS_MOCK; /* mode check error */
|
||||
// uptr->SNS |= SNS_RTAE; /* reserved track access error */
|
||||
uptr->SNS |= SNS_RES8; /* reserved track access error */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
|
||||
@ -2556,7 +2526,6 @@ iha_error:
|
||||
case DSK_WTF: /* 0x41 Write track format */
|
||||
case DSK_WSL: /* WSL 0x31 */
|
||||
len = chp->ccw_count; /* get number bytes to read */
|
||||
// mema = uptr->CHS+(len/30); /* save address */
|
||||
mema = uptr->CHS; /* save address */
|
||||
|
||||
sim_debug(DEBUG_CMD, dptr, "before WSL/WTF Sector %x len %x\n", uptr->CHS, len);
|
||||
@ -2592,7 +2561,6 @@ iha_error:
|
||||
chp->ccw_count = len; /* restore number bytes to read */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
|
||||
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_LENGTH);
|
||||
return SCPE_OK;
|
||||
break;
|
||||
}
|
||||
@ -3255,7 +3223,6 @@ int hsdp_format(UNIT *uptr) {
|
||||
/* get sector address of utx diag map (DMAP) track 0 pointer */
|
||||
/* put data = 0xf0000000 + (cyl-1), 0x8a000000 + daddr, */
|
||||
/* 0x9a000000 + (cyl-1), 0xf4000000 */
|
||||
// int32 daddr = vaddr - SPT(type);
|
||||
int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
|
||||
/* make logical */
|
||||
int32 logda = daddr*(SPT(type)-1)/(SPT(type));
|
||||
@ -3639,7 +3606,6 @@ ldone:
|
||||
/* get umap sector address from umapaddr */
|
||||
info = (buff[16]<<24) | (buff[17]<<16) | (buff[18]<<8) | buff[19];
|
||||
daddr = umapaddr * ssize; /* byte offset in file */
|
||||
// printf("info %8x daddr %8x\r\n", info, daddr);
|
||||
if ((sim_fseek(uptr->fileref, umapaddr*ssize, SEEK_SET)) != 0) { /* seek umap */
|
||||
detach_unit(uptr); /* detach if error */
|
||||
return SCPE_FMT; /* error */
|
||||
|
||||
@ -45,8 +45,6 @@
|
||||
#define UNIT_MT UNIT_ATTABLE | UNIT_DISABLE | UNIT_ROABLE
|
||||
#define DEV_BUF_NUM(x) (((x) & 07) << DEV_V_UF2)
|
||||
#define GET_DEV_BUF(x) (((x) >> DEV_V_UF2) & 07)
|
||||
//#define MTUF_V_WLK (UNIT_V_UF + 0) /* write lock */
|
||||
//#define MTUF_WLK (1u << MTUF_V_WLK)
|
||||
|
||||
#define CMD u3
|
||||
/* BTP tape commands */
|
||||
@ -395,7 +393,6 @@ t_stat mt_preio(UNIT *uptr, uint16 chan) {
|
||||
uptr->SNS &= ~(SNS_RDY|SNS_ONLN); /* unit not online or rdy */
|
||||
uptr->SNS &= ~SNS_LOAD; /* reset BOT detected */
|
||||
return SCPE_OK; /* good to go */
|
||||
// return SNS_BSY;
|
||||
}
|
||||
|
||||
sim_debug(DEBUG_CMD, dptr, "mt_preio unit %02x chsa %04x OK\n", unit, chsa);
|
||||
@ -457,7 +454,6 @@ t_stat mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
chan, chp->ccw_addr, chp->ccw_count);
|
||||
if (cmd != 0x03) { /* if this is a nop do not zero status */
|
||||
uptr->SNS = (uptr->SNS & 0x0000ff00); /* clear all but byte 2 */
|
||||
// uptr->SNS |= (SNS_RDY|SNS_ONLN); /* set ready status */
|
||||
}
|
||||
if ((uptr->flags & UNIT_ATT) == 0) { /* unit attached status */
|
||||
uptr->SNS |= SNS_INTVENT; /* unit intervention required */
|
||||
@ -497,14 +493,6 @@ t_stat mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
return SNS_CHNEND|SNS_DEVEND|STATUS_PCHK; /* add DEVEND 08/16/20 */
|
||||
break;
|
||||
}
|
||||
#if 0
|
||||
/* not reached */
|
||||
if (uptr->SNS & 0xff000000) /* errors? */
|
||||
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK;
|
||||
sim_debug(DEBUG_EXP, dptr,
|
||||
"mt_startcmd ret CHNEND|DEVEND chan %04x unit %04x cmd %02x\n", chan, unit, cmd);
|
||||
return SNS_CHNEND|SNS_DEVEND;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Map simH errors into machine errors */
|
||||
@ -576,9 +564,7 @@ t_stat mt_srv(UNIT *uptr)
|
||||
uint32 mema;
|
||||
uint16 len;
|
||||
uint8 ch;
|
||||
// uint8 buf[1024];
|
||||
|
||||
// sim_debug(DEBUG_DETAIL, dptr, "mt_srv unit %04x cmd %02x\n", unit, cmd);
|
||||
sim_debug(DEBUG_CMD, dptr, "mt_srv unit %04x cmd %02x\n", unit, cmd);
|
||||
|
||||
switch (cmd) {
|
||||
@ -722,7 +708,6 @@ t_stat mt_srv(UNIT *uptr)
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
return SCPE_OK;
|
||||
}
|
||||
// uptr->SNS |= (SNS_RDY|SNS_ONLN); /* set ready status */
|
||||
|
||||
switch (cmd) {
|
||||
case MT_READ: /* 0x02 */ /* read a record from the device */
|
||||
@ -1147,7 +1132,6 @@ t_stat mt_srv(UNIT *uptr)
|
||||
uptr->SNS &= ~(SNS_RDY|SNS_ONLN); /* unit not online or rdy */
|
||||
uptr->SNS &= ~SNS_LOAD; /* reset BOT detected */
|
||||
r = sim_tape_detach(uptr);
|
||||
//?? set_devattn(chsa, SNS_DEVEND); /* ready int???? */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
|
||||
}
|
||||
break;
|
||||
|
||||
@ -1416,10 +1416,12 @@ int scsi_format(UNIT *uptr) {
|
||||
sim_switches = oldsw; /* restore switches */
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* see if user wants to initialize the disk */
|
||||
if (!get_yn("Initialize disk? [Y] ", TRUE)) {
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* VDT 249264 (819/18/0) 0x3cdb0 for 9346 - 823/19/16 vaddr */
|
||||
/* MDT 249248 (819/17/0) 0x3cda0 for 9346 - 823/19/16 daddr */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user