mirror of
https://github.com/rcornwell/sims.git
synced 2026-03-29 02:55:02 +00:00
SEL32: Add disk diag support code for disk and hsdp routines.
SEL32: Correct console echo command. SEL32: Correct skipinstr useage.
This commit is contained in:
AZBevier
@@ -215,9 +215,11 @@ int32 RDYQ_Put(uint32 entry)
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RDYQIN += 1; /* next entry */
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RDYQIN %= RDYQ_SIZE; /* modulo RDYQ size */
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irq_pend = 1; /* do a scan */
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#ifdef USE_RDYQ
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// waitrdyq = 5;
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//25waitrdyq = 2;
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waitrdyq = 1; /* wait at least 1 instruction */
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#endif
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return 0; /* all OK */
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}
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@@ -339,6 +341,11 @@ uint32 find_int_icb(uint16 chsa)
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return 0; /* not found */
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}
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icba = RMW(icba); /* get address of ICB from memory */
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if (!MEM_ADDR_OK(icba)) { /* needs to be valid address in memory */
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sim_debug(DEBUG_EXP, &cpu_dev,
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"find_int_icb ERR chsa %04x icba %02x\n", chsa, icba);
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return 0; /* not found */
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}
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sim_debug(DEBUG_IRQ, &cpu_dev,
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"find_int_icb icba %06x SPADC %08x chsa %04x lev %02x SPADI %08x INTS %08x\n",
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icba, spadent, chsa, inta, SPAD[inta+0x80], INTS[inta]);
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@@ -1255,27 +1262,32 @@ missing:
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#ifndef NOTHERE
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/* check for a Command or data chain operation in progresss */
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if ((chp->chan_byte & BUFF_BUSY) && chp->chan_byte != BUFF_POST) {
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uint16 tstat, tcnt;
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uint16 tstat = chp->chan_status; /* save status */
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uint16 tcnt = chp->ccw_count; /* save count */
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DEVICE *dptr = get_dev(uptr);
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sim_debug(DEBUG_EXP, &cpu_dev,
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"startxio busy return CC3&CC4 chsa %04x chp %p cmd %02x flags %04x byte %02x\n",
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chsa, chp, chp->ccw_cmd, chp->ccw_flags, chp->chan_byte);
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#ifdef OLDWAY
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*status = CC4BIT|CC3BIT; /* busy, so CC3&CC4 */
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#else
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*status = CC1BIT; /* CCs = 1, SIO accepted & queued, no echo status */
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/* handle an Ethernet controller busy by sending interrupt/status */
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tstat = chp->chan_status; /* save status */
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tcnt = chp->ccw_count; /* save count */
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chp->chan_status = STATUS_BUSY|STATUS_CEND|STATUS_DEND; /* set busy status */
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chp->ccw_count = 0; /* zero count */
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store_csw(chp); /* store the status */
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chp->chan_status = tstat; /* restore status */
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chp->ccw_count = tcnt; /* restore count */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"startxio done BUSY chp %p chsa %04x ccw_flags %04x stat %04x cnt %04x\n",
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chp, chsa, chp->ccw_flags, tstat, tcnt);
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#endif
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/* ethernet controller wants an interrupt for busy status */
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if (DEV_TYPE(dptr) == DEV_ETHER) {
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*status = CC1BIT; /* CCs = 1, SIO accepted & queued, no echo status */
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/* handle an Ethernet controller busy by sending interrupt/status */
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chp->chan_status = STATUS_BUSY|STATUS_CEND|STATUS_DEND; /* set busy status */
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chp->ccw_count = 0; /* zero count */
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store_csw(chp); /* store the status */
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chp->chan_status = tstat; /* restore status */
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chp->ccw_count = tcnt; /* restore count */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"startxio done BUSY/INT chp %p chsa %04x ccw_flags %04x stat %04x cnt %04x\n",
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chp, chsa, chp->ccw_flags, tstat, tcnt);
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} else {
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/* everyone else just gets a busy return */
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*status = CC4BIT|CC3BIT; /* busy, so CC3&CC4 */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"startxio done BUSY chp %p chsa %04x ccw_flags %04x stat %04x cnt %04x\n",
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chp, chsa, chp->ccw_flags, tstat, tcnt);
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}
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#ifdef DO_DYNAMIC_DEBUG
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/* start debugging */
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if (chsa == 0x0c00)
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@@ -1428,6 +1440,10 @@ t_stat testxio(uint16 chsa, uint32 *status) { /* test XIO */
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/* the channel is not busy, see if any status to post */
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if (post_csw(chp, 0)) {
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#ifdef DO_DYNAMIC_DEBUG
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/* start debugging */
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cpu_dev.dctrl |= (DEBUG_INST | DEBUG_TRAP | DEBUG_EXP | DEBUG_IRQ);
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#endif
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*status = CC2BIT; /* status stored from SIO, so CC2 */
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sim_debug(DEBUG_XIO, &cpu_dev,
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"testxio END status stored incha %06x chsa %04x sw1 %08x sw2 %08x\n",
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@@ -1876,9 +1892,9 @@ uint32 cont_chan(uint16 chsa)
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int32 stat; /* return status 0/1 from loadccw */
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CHANP *chp = find_chanp_ptr(chsa); /* channel program */
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sim_debug(DEBUG_EXP, &cpu_dev,
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"cont_chan entry chp %p chan_byte %02x chsa %04x addr %06x\n",
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chp, chp->chan_byte, chsa, chp->ccw_addr);
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sim_debug(DEBUG_EXP, &cpu_dev,
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"cont_chan entry chp %p chan_byte %02x chsa %04x addr %06x\n",
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chp, chp->chan_byte, chsa, chp->ccw_addr);
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/* we have entries, continue channel program */
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if (chp->chan_byte != BUFF_NEXT) {
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/* channel program terminated already, ignore entry */
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@@ -2139,6 +2155,17 @@ sim_debug(DEBUG_EXP, &cpu_dev, "scan_chanx BUFF_DONE chp %p chan_byte %04x\n", c
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*ilev = i; /* return interrupt level */
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irq_pend = 0; /* not pending anymore */
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return(chan_icba); /* return ICB address */
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} else {
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/* we had an interrupt request, but no status is available */
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/* clear the interrupt and go on */
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/* this is a fix for MPX1X restart 092220 */
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sim_debug(DEBUG_IRQ, &cpu_dev,
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"scan_chan highest int has no stat irq %02x SPAD %08x INTS %08x\n",
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i, SPAD[i+0x80], INTS[i]);
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/* requesting, make active and turn off request flag */
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INTS[i] &= ~INTS_ACT; /* turn off active int */
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SPAD[i+0x80] &= ~SINT_ACT; /* clear active in SPAD too */
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}
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}
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}
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@@ -2148,7 +2175,7 @@ tryme:
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//25irq_pend = 0; /* not pending anymore */
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#ifndef TEST_082520
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if (RDYQ_Num()) {
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#ifndef NOTNOW
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#ifdef USE_RDYQ
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if (waitrdyq > 0) {
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waitrdyq--;
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irq_pend = 1; /* still pending */
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@@ -115,7 +115,7 @@ UNIT con_unit[] = {
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{UDATA(&con_srvo, UNIT_CON, 0), 0, UNIT_ADDR(0x7EFD)}, /* Output */
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};
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//DIB con_dib = {NULL, con_startcmd, NULL, NULL, NULL, con_ini, con_unit, con_chp, NUM_UNITS_CON, 0xf, 0x7e00, 0, 0, 0};
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//DIB con_dib = {NULL,con_startcmd,NULL,NULL,NULL,con_ini,con_unit,con_chp,NUM_UNITS_CON,0xf,0x7e00,0,0,0};
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DIB con_dib = {
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con_preio, /* uint16 (*pre_io)(UNIT *uptr, uint16 chan)*/ /* Start I/O */
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con_startcmd, /* uint16 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd)*/ /* Start command */
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@@ -282,82 +282,93 @@ t_stat con_srvo(UNIT *uptr) {
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int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
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int cmd = uptr->CMD & CON_MSK;
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CHANP *chp = find_chanp_ptr(chsa); /* find the chanp pointer */
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int len = chp->ccw_count; /* INCH command count */
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uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
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uint32 tstart;
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int cnt = 0;
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uint8 ch;
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo enter CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
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/* if input tried from output device, error */
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if ((cmd == CON_RD) || (cmd == CON_ECHO) || (cmd == 0xC0)) { /* check for output */
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/* CON_RD: 0x02 */ /* Read command */
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/* CON_ECHO: 0x0a */ /* Read command w/ECHO */
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/* if input requested for output device, give error */
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if (unit == 1) {
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uptr->SNS |= SNS_CMDREJ; /* command rejected */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo Read to output device CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
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chan_end(chsa, SNS_CHNEND|SNS_UNITCHK); /* unit check */
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return SCPE_OK;
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}
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}
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switch (cmd) {
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if ((cmd == CON_NOP) || (cmd == CON_INCH2)) { /* NOP has to do nothing */
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/* if input tried from output device, error */
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case CON_RD: /* 0x02 */ /* Read command */
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case CON_ECHO: /* 0x0a */ /* Read command w/ECHO */
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case 0x0C: /* 0x0C */ /* Unknown command */
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/* if input requested for output device, give error */
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uptr->SNS |= SNS_CMDREJ; /* command rejected */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo INCH/NOP unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
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"con_srvo Read to output device CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
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chan_end(chsa, SNS_CHNEND|SNS_UNITCHK); /* unit check */
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break;
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case CON_INCH2: /* 0xf0 */ /* INCH command */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo INCH unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
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unit, uptr->CMD, cmd, con_data[unit].incnt, uptr->u4);
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if (cmd == CON_INCH2) { /* Channel end only for INCH */
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int len = chp->ccw_count; /* INCH command count */
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uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
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//FIXME - test error return for error
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// int i = set_inch(uptr, mema); /* new address */
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set_inch(uptr, mema); /* new address */
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/* now call set_inch() function to write and test inch buffer addresses */
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tstart = set_inch(uptr, mema); /* new address */
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if ((tstart == SCPE_MEM) || (tstart == SCPE_ARG)) { /* any error */
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/* we have error, bail out */
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uptr->SNS |= SNS_CMDREJ;
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo INCH CMD %08x chsa %04x len %02x inch %06x\n", uptr->CMD, chsa, len, mema);
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chan_end(chsa, SNS_CHNEND); /* INCH done */
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} else {
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo NOP CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
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"con_srvo INCH Error unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
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unit, uptr->CMD, cmd, con_data[unit].incnt, uptr->u4);
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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break;
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}
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return SCPE_OK;
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}
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo INCH CMD %08x chsa %04x len %02x inch %06x\n", uptr->CMD, chsa, len, mema);
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chan_end(chsa, SNS_CHNEND); /* return OK */
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break;
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if ((cmd == CON_WR) || (cmd == CON_RWD)) {
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int cnt = 0;
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case CON_NOP: /* 0x03 */ /* NOP has do nothing */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo NOP unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
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unit, uptr->CMD, cmd, con_data[unit].incnt, uptr->u4);
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo NOP CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
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break;
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case CON_RWD: /* 0x37 */ /* TOF and write line */
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case CON_WR: /* 0x01 */ /* Write command */
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/* see if write complete */
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if (uptr->CMD & CON_OUTPUT) {
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/* write is complete, post status */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo write CMD %08x chsa %04x cmd %02x complete\n",
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uptr->CMD, chsa, cmd);
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uptr->CMD &= LMASK; /* nothing left, command complete */
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/*RTC*/ outbusy = 0; /* output done */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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/*RTC*/ outbusy = 0; /* output done */
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chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
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return SCPE_OK;
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break;
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}
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//Comment out clock flag 072020
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/*RTC*/ outbusy = 1; /* tell clock output waiting */
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/*RTC*/ outbusy = 1; /* tell clock output waiting */
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/* Write to device */
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while (chan_read_byte(chsa, &ch) == SCPE_OK) { /* get byte from memory */
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/* HACK HACK HACK */
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ch &= 0x7f; /* make 7 bit w/o parity */
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sim_putchar(ch); /* output next char to device */
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cnt++; /* count chars output */
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ch &= 0x7f; /* make 7 bit w/o parity */
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sim_putchar(ch); /* output next char to device */
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cnt++; /* count chars output */
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}
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uptr->CMD |= CON_OUTPUT; /* output command complete */
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uptr->CMD |= CON_OUTPUT; /* output command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvo write wait %03x CMD %08x chsa %04x cmd %02x to complete\n",
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// 41*cnt+47, uptr->CMD, chsa, cmd);
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19*cnt+23, uptr->CMD, chsa, cmd);
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fflush(sim_deb);
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// sim_activate(uptr, 19*cnt+23); /* wait for a while */
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// sim_activate(uptr, 31*cnt+47); /* wait for a while */
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/*719*/ sim_activate(uptr, 41*cnt+47); /* wait for a while */
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//719 sim_activate(uptr, 81*cnt+87); /* wait for a while */
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// sim_activate(uptr, 19*cnt+23); /* wait for a while */
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// sim_activate(uptr, 31*cnt+47); /* wait for a while */
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/*719*/ sim_activate(uptr, 41*cnt+47); /* wait for a while */
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//719 sim_activate(uptr, 81*cnt+87); /* wait for a while */
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break;
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}
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return SCPE_OK;
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}
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@@ -368,6 +379,9 @@ t_stat con_srvi(UNIT *uptr) {
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int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
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int cmd = uptr->CMD & CON_MSK;
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CHANP *chp = find_chanp_ptr(chsa); /* find the chanp pointer */
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int len = chp->ccw_count; /* INCH command count */
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uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
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uint32 tstart;
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uint8 ch;
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t_stat r;
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@@ -378,46 +392,55 @@ t_stat con_srvi(UNIT *uptr) {
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"con_srvi enter CMD %08x chsa %04x cmd %02x incnt %02x u4 %02x\n",
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uptr->CMD, chsa, cmd, con_data[unit].incnt, uptr->u4);
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/* if output tried to input device, error */
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if ((cmd == CON_RWD) || (cmd == CON_WR) || (cmd == 0x0C)) { /* check for output */
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/* CON_RWD: 0x37 */ /* TOF and write line */
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/* CON_WR: 0x01 */ /* Write command */
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/* if input requested for output device, give error */
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if (unit == 0) {
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uptr->SNS |= SNS_CMDREJ; /* command rejected */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvi Write to input device CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
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chan_end(chsa, SNS_CHNEND|SNS_UNITCHK); /* unit check */
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// fall thru return SCPE_OK;
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}
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}
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switch (cmd) {
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if ((cmd == CON_NOP) || (cmd == CON_INCH2)) { /* NOP is do nothing */
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/* if output tried to input device, error */
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case CON_RWD: /* 0x37 */ /* TOF and write line */
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case CON_WR: /* 0x01 */ /* Write command */
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case 0x0C: /* 0x0C */ /* Unknown command */
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/* if input requested for output device, give error */
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uptr->SNS |= SNS_CMDREJ; /* command rejected */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvi INCH/NOP unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
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"con_srvi Write to input device CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
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chan_end(chsa, SNS_CHNEND|SNS_UNITCHK); /* unit check */
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break;
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case CON_INCH2: /* 0xf0 */ /* INCH command */
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uptr->CMD &= LMASK; /* nothing left, command complete */
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sim_debug(DEBUG_CMD, &con_dev,
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"con_srvi INCH unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
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unit, uptr->CMD, cmd, con_data[unit].incnt, uptr->u4);
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if (cmd == CON_INCH2) { /* Channel end only for INCH */
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int len = chp->ccw_count; /* INCH command count */
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uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
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//FIXME add code to test return from set_inch
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set_inch(uptr, mema); /* new address */
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con_data[unit].incnt = 0; /* buffer empty */
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uptr->u4 = 0; /* no I/O yet */
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/* now call set_inch() function to write and test inch buffer addresses */
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tstart = set_inch(uptr, mema); /* new address */
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if ((tstart == SCPE_MEM) || (tstart == SCPE_ARG)) { /* any error */
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/* we have error, bail out */
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uptr->SNS |= SNS_CMDREJ;
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sim_debug(DEBUG_CMD, &con_dev,
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||||
"con_srvi INCH CMD %08x chsa %04x len %02x inch %06x\n", uptr->CMD, chsa, len, mema);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
|
||||
} else {
|
||||
sim_debug(DEBUG_CMD, &con_dev,
|
||||
"con_srvi NOP CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* NOP done */
|
||||
"con_srvi INCH Error unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
|
||||
unit, uptr->CMD, cmd, con_data[unit].incnt, uptr->u4);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
}
|
||||
con_data[unit].incnt = 0; /* buffer empty */
|
||||
uptr->u4 = 0; /* no I/O yet */
|
||||
sim_debug(DEBUG_CMD, &con_dev,
|
||||
"con_srvi INCH CMD %08x chsa %04x len %02x inch %06x\n", uptr->CMD, chsa, len, mema);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
|
||||
/* drop through to poll input */
|
||||
}
|
||||
break;
|
||||
|
||||
switch (cmd) {
|
||||
case CON_NOP: /* 0x03 */ /* NOP has do nothing */
|
||||
uptr->CMD &= LMASK; /* nothing left, command complete */
|
||||
sim_debug(DEBUG_CMD, &con_dev,
|
||||
"con_srvi NOP unit %02x: CMD %08x cmd %02x incnt %02x u4 %02x\n",
|
||||
unit, uptr->CMD, cmd, con_data[unit].incnt, uptr->u4);
|
||||
sim_debug(DEBUG_CMD, &con_dev,
|
||||
"con_srvi NOP CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
|
||||
/* drop through to poll input */
|
||||
break;
|
||||
|
||||
case CON_RD: /* 0x02 */ /* read from device */
|
||||
case CON_ECHO: /* 0x0a */ /* read from device w/ECHO */
|
||||
@@ -432,6 +455,12 @@ t_stat con_srvi(UNIT *uptr) {
|
||||
/* process any characters */
|
||||
if (uptr->u4 != con_data[unit].incnt) { /* input available */
|
||||
ch = con_data[unit].ibuff[uptr->u4]; /* get char from read buffer */
|
||||
#ifndef ECHO_ON_READ_092220
|
||||
/* this fixes mpx1x time entry on startup */
|
||||
if (uptr->CMD & CON_EKO) /* ECHO requested */
|
||||
sim_putchar(ch); /* ECHO the char */
|
||||
#endif
|
||||
|
||||
if (chan_write_byte(chsa, &ch)) { /* write byte to memory */
|
||||
/* write error */
|
||||
cmd = 0; /* no cmd now */
|
||||
@@ -503,8 +532,11 @@ t_stat con_srvi(UNIT *uptr) {
|
||||
"con_srvi handle readch unit %02x: CMD %08x read %02x u4 %02x incnt %02x\n",
|
||||
unit, uptr->CMD, ch, uptr->u4, con_data[unit].incnt);
|
||||
|
||||
#ifdef ECHO_ON_READ_092220
|
||||
/* this fixes mpx1x time entry on startup */
|
||||
if (uptr->CMD & CON_EKO) /* ECHO requested */
|
||||
sim_putchar(ch); /* ECHO the char */
|
||||
#endif
|
||||
|
||||
/* put char in buffer */
|
||||
con_data[unit].ibuff[con_data[unit].incnt++] = ch;
|
||||
|
||||
@@ -1981,7 +1981,9 @@ wait_loop:
|
||||
sim_debug(DEBUG_IRQ, &cpu_dev,
|
||||
"Load Skipinstr %1x set loading PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
skipinstr, PSD1, PSD2, CPUSTATUS);
|
||||
#ifdef NO_SKIP_HERE
|
||||
skipinstr = 1; /* skip next interrupt test only once */
|
||||
#endif
|
||||
goto skipi; /* skip int test */
|
||||
}
|
||||
/* process any channel programs that are queued */
|
||||
@@ -1989,7 +1991,7 @@ wait_loop:
|
||||
uint32 chsa; /* channel/sub adddress */
|
||||
int32 stat; /* return status 0/1 from loadccw */
|
||||
|
||||
#ifdef NOT_NOW
|
||||
#ifdef USE_RDYQ
|
||||
if (waitrdyq > 0) {
|
||||
waitrdyq--;
|
||||
} else
|
||||
@@ -2093,12 +2095,15 @@ wait_loop:
|
||||
"<|>Int2 %02x ICBA %06x IOCLA %06x STAT %08x SW1 %08x SW2 %08x\n",
|
||||
il, int_icb, RMW(int_icb+16), RMW(int_icb+20), RMW(bc), RMW(bc+4));
|
||||
wait4int = 0; /* wait is over for int */
|
||||
/*917*/ drop_nop = 0; /* no nop skipping */
|
||||
#ifdef NOTNOW
|
||||
sim_debug(DEBUG_IRQ, &cpu_dev,
|
||||
"<|> Skipinstr %1x set intr %02x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
skipinstr, il, PSD1, PSD2, CPUSTATUS);
|
||||
#endif
|
||||
#ifdef NO_SKIP_HERE
|
||||
skipinstr = 1; /* skip next inter test after this instr */
|
||||
#endif
|
||||
goto skipi; /* skip int test */
|
||||
}
|
||||
}
|
||||
@@ -2106,7 +2111,7 @@ wait_loop:
|
||||
/*25*/ irq_pend = 0; /* not pending anymore */
|
||||
if (RDYQ_Num()) {
|
||||
uint32 chsa; /* channel/sub adddress */
|
||||
#ifndef NOTNOW
|
||||
#ifdef USE_RDYQ
|
||||
if (waitrdyq > 0) {
|
||||
waitrdyq--;
|
||||
irq_pend = 1; /* still pending */
|
||||
@@ -2145,7 +2150,9 @@ wait_loop:
|
||||
"Skipinstr %1x set @ attn int PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
skipinstr, PSD1, PSD2, CPUSTATUS);
|
||||
#endif
|
||||
#ifdef NO_SKIP_HERE
|
||||
skipinstr = 1; /* skip next interrupt test only once */
|
||||
#endif
|
||||
goto newpsd; /* got process trap */
|
||||
}
|
||||
|
||||
@@ -3838,7 +3845,9 @@ skipit:
|
||||
"<|>IntX deactivate level %02x at CALM PSD1 %08x\n",
|
||||
irq_auto, PSD1);
|
||||
/*AIR*/ irq_auto = 0; /* show done processing in blocked mode */
|
||||
#ifdef NO_SKIP_HERE
|
||||
/*051920*/ skipinstr = 1; /* skip interrupt test */
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -5456,7 +5465,9 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
|
||||
"<|>IntX deactivate level %02x at SVC #%2x PSD1 %08x\n",
|
||||
irq_auto, temp2, PSD1);
|
||||
/*AIR*/ irq_auto = 0; /* show done processing in blocked mode */
|
||||
#ifdef NO_SKIP_HERE
|
||||
/*051920*/ skipinstr = 1; /* skip interrupt test */
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -6019,7 +6030,6 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
|
||||
TRAPSTATUS |= BIT18; /* set bit 18 of trap status */
|
||||
goto newpsd; /* memory read error or map fault */
|
||||
}
|
||||
//bad /* 723 */ temp &= ~0x02000000; /* reset base reg bit 6 */
|
||||
bc = CPUSTATUS; /* save the CPU STATUS */
|
||||
TPSD[0] = PSD1; /* save the PSD for the instruction */
|
||||
TPSD[1] = PSD2;
|
||||
@@ -6027,6 +6037,11 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
|
||||
ix = SPAD[0xf5]; /* save the current PSD2 */
|
||||
reg = irq_pend; /* save intr status */
|
||||
|
||||
#ifdef DO_DYNAMIC_DEBUG
|
||||
/* start debugging */
|
||||
if (PC == 0x1e59c)
|
||||
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_TRAP | DEBUG_EXP | DEBUG_IRQ);
|
||||
#endif
|
||||
if (opr & 0x0200) { /* Was it LPSDCM? */
|
||||
if ((TRAPME = Mem_read(addr+4, &temp2))) { /* get PSD2 from memory */
|
||||
if ((CPU_MODEL == MODEL_97) || (CPU_MODEL == MODEL_V9)) {
|
||||
@@ -6056,6 +6071,7 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
|
||||
modes = PSD1 & 0x87000000; /* extract bits 0, 5, 6, 7 from PSD 1 */
|
||||
CPUSTATUS &= ~0x87000000; /* reset bits in CPUSTATUS */
|
||||
CPUSTATUS |= modes; /* now insert into CPUSTATUS */
|
||||
#ifdef NOTNEEDED
|
||||
/* set new arithmetic trap state in CPUSTATUS */
|
||||
if (PSD1 & AEXPBIT) {
|
||||
CPUSTATUS |= AEXPBIT; /* set bit 7 of cpu status */
|
||||
@@ -6068,6 +6084,7 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
|
||||
modes |= EXTDBIT; /* set extended mode */
|
||||
} else
|
||||
CPUSTATUS &= ~EXTDBIT; /* reset bit 5 of cpu status */
|
||||
#endif
|
||||
/* set new map mode and interrupt blocking state in CPUSTATUS */
|
||||
if (PSD2 & MAPBIT) {
|
||||
CPUSTATUS |= 0x00800000; /* set bit 8 of cpu status */
|
||||
@@ -6087,7 +6104,9 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
|
||||
sim_debug(DEBUG_IRQ, &cpu_dev,
|
||||
"<|>IntX deactivate level %02x at LPSD(CM) %08x\n", irq_auto, PSD1);
|
||||
/*AIR*/ irq_auto = 0; /* show done processing in blocked mode */
|
||||
#ifdef NO_SKIP_HERE
|
||||
skipinstr = 1; /* skip interrupt test */
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -6366,7 +6385,7 @@ TPSD[0], TPSD[1], PSD1, PSD2, TRAPME);
|
||||
INTS[prior] &= ~INTS_ACT; /* deactivate specified int level */
|
||||
SPAD[prior+0x80] &= ~SINT_ACT; /* deactivate in SPAD too */
|
||||
irq_pend = 1; /* start scanning interrupts again */
|
||||
/* instruction following a DAI cn not be interrupted */
|
||||
/* instruction following a DAI can not be interrupted */
|
||||
/* skip tests for interrupts if this is the case */
|
||||
#ifdef NOTNOW
|
||||
sim_debug(DEBUG_IRQ, &cpu_dev,
|
||||
@@ -6688,6 +6707,10 @@ mcheck:
|
||||
}
|
||||
}
|
||||
#endif
|
||||
if ((INTS[ix] & INTS_ACT) == 0)
|
||||
sim_debug(DEBUG_XIO, &cpu_dev,
|
||||
"DCI INT %02x is NOT set chan %04x suba %04x status %08x\n",
|
||||
ix, chan, suba, rstatus);
|
||||
/* SPAD entries for interrupts begin at 0x80 */
|
||||
INTS[ix] &= ~INTS_ENAB; /* disable specified int level */
|
||||
SPAD[ix+0x80] &= ~SINT_ENAB; /* disable in SPAD too */
|
||||
@@ -6704,10 +6727,16 @@ mcheck:
|
||||
|
||||
if ((TRAPME = checkxio(rchsa, &rstatus)))
|
||||
goto newpsd; /* error returned, trap cpu */
|
||||
if ((INTS[ix] & INTS_ACT) == 0)
|
||||
sim_debug(DEBUG_XIO, &cpu_dev,
|
||||
"ACI INT %02x is NOT set chan %04x suba %04x status %08x\n",
|
||||
ix, chan, suba, rstatus);
|
||||
/* SPAD entries for interrupts begin at 0x80 */
|
||||
INTS[ix] |= INTS_ACT; /* activate specified int level */
|
||||
SPAD[ix+0x80] |= SINT_ACT; /* enable in SPAD too */
|
||||
//WAS INTS[ix] &= ~INTS_REQ; /* clears any requests also */
|
||||
//WAS NOT DONE INTS[ix] &= ~INTS_REQ; /* clears any requests also */
|
||||
/*917*/ /* tech manual says to remove any request */
|
||||
/*917*/ INTS[ix] &= ~INTS_REQ; /* clears any requests also */
|
||||
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
|
||||
break;
|
||||
|
||||
@@ -6720,18 +6749,15 @@ mcheck:
|
||||
|
||||
if ((TRAPME = checkxio(rchsa, &rstatus)))
|
||||
goto newpsd; /* error returned, trap cpu */
|
||||
sim_debug(DEBUG_XIO, &cpu_dev,
|
||||
"DACI after checkxio chan %04x suba %04x status %08x\n", chan, suba, rstatus);
|
||||
if ((INTS[ix] & INTS_ACT) == 0)
|
||||
sim_debug(DEBUG_XIO, &cpu_dev,
|
||||
"DACI INT %02x is NOT set chan %04x suba %04x status %08x\n",
|
||||
ix, chan, suba, rstatus);
|
||||
/* SPAD entries for interrupts begin at 0x80 */
|
||||
INTS[ix] &= ~INTS_ACT; /* deactivate specified int level */
|
||||
SPAD[ix+0x80] &= ~SINT_ACT; /* deactivate in SPAD too */
|
||||
irq_pend = 1; /* start scanning interrupts again */
|
||||
skipinstr = 1; /* skip interrupt test */
|
||||
#ifdef NOTNOW
|
||||
sim_debug(DEBUG_XIO, &cpu_dev,
|
||||
"DACI INTS[%02x] %08x Skipinstr %1x set PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
ix, INTS[ix], skipinstr, PSD1, PSD2, CPUSTATUS);
|
||||
#endif
|
||||
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
|
||||
break;
|
||||
} /* end of XIO switch */
|
||||
@@ -7078,6 +7104,20 @@ newpsd:
|
||||
modes = PSD1 & 0x87000000; /* extract bits 0, 5, 6, 7 from PSD 1 */
|
||||
CPUSTATUS &= ~0x87000000; /* reset bits in CPUSTATUS */
|
||||
CPUSTATUS |= modes; /* not insert into CPUSTATUS */
|
||||
#ifdef NOTNEEDED
|
||||
/* set new arithmetic trap state in CPUSTATUS */
|
||||
/*917*/ if (PSD1 & AEXPBIT) {
|
||||
CPUSTATUS |= AEXPBIT; /* set bit 7 of cpu status */
|
||||
modes |= AEXPBIT; /* set arithmetic exception mode */
|
||||
} else
|
||||
CPUSTATUS &= ~AEXPBIT; /* reset bit 7 of cpu status */
|
||||
/*917*/ /* set new extended state in CPUSTATUS */
|
||||
if (PSD1 & EXTDBIT) {
|
||||
CPUSTATUS |= EXTDBIT; /* set bit 5 of cpu status */
|
||||
modes |= EXTDBIT; /* set extended mode */
|
||||
} else
|
||||
CPUSTATUS &= ~EXTDBIT; /* reset bit 5 of cpu status */
|
||||
#endif
|
||||
/* set new map mode and interrupt blocking state in CPUSTATUS */
|
||||
if (PSD2 & MAPBIT) {
|
||||
CPUSTATUS |= 0x00800000; /* set bit 8 of cpu status */
|
||||
|
||||
@@ -98,30 +98,44 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
|
||||
/* 26 words of scratchpad */
|
||||
/* 4 words of label buffer registers */
|
||||
|
||||
/* track label / sector label definations */
|
||||
/************************************/
|
||||
/* track label definations 34 bytes */
|
||||
/* for track 0, write max cyl/head/sec values in 0-3 */
|
||||
/* otherwise write current values */
|
||||
/*
|
||||
short lcyl; cylinder
|
||||
char ltkn; track
|
||||
char lid; sector id
|
||||
char lflg1; track/sector status flags
|
||||
bit 0 good
|
||||
1 alternate
|
||||
2 spare
|
||||
3 reserved
|
||||
4 flaw
|
||||
0 short lcyl; cylinder
|
||||
2 char ltkn; head or track number
|
||||
3 char lid; track label id (0xff means last track)
|
||||
4 char lflg1; track status flags
|
||||
bit 0 good trk
|
||||
1 alternate trk
|
||||
2 spare trk
|
||||
3 reserved trk
|
||||
4 defective trk
|
||||
5 last track
|
||||
6 start of alternate
|
||||
char lflg2;
|
||||
short lspar1;
|
||||
short lspar2;
|
||||
short ldef1;
|
||||
int ldeallp; DMAP block number trk0
|
||||
int lumapp; UMAP block number sec1
|
||||
short ladef3;
|
||||
short laltcyl;
|
||||
char lalttk; sectors per track
|
||||
char ldscnt; number of heads
|
||||
char ldatrflg; device attributes
|
||||
6-7 n/u = 0
|
||||
5 char lflg2;
|
||||
bit 0 write lock
|
||||
1 write protected
|
||||
2-7 n/u = 0
|
||||
6 short lspar1; n/u = 0
|
||||
8 short lspar2; n/u = 0
|
||||
10 short ldef1; defect #1 sec and byte position
|
||||
* for track 0 write DMAP
|
||||
* write sector number of cyl-4, hds-2, sec 0 value in 12-15
|
||||
* otherwise write current values
|
||||
12 short ldef2; defect #2 sec and byte position
|
||||
14 short ldef3; defect #3 sec and byte position
|
||||
* for track 0 write UMAP which is DMAP - 2 * SPT
|
||||
* write sector number of cyl-4, hds-4, sec 0 value in 16-19
|
||||
* otherwise write current values
|
||||
16 short ladef1; defect #1 abs position
|
||||
18 short ladef2; defect #2 abs position
|
||||
20 short ladef3; defect #3 abs position
|
||||
22 short laltcyl; alternate cylinder number or return cyl num
|
||||
24 char lalttk; alrernate track number or return track num
|
||||
25 char ldscnt; data sector count 16/20
|
||||
26 char ldatrflg; device attributes
|
||||
bit 0 n/u
|
||||
1 disk is mhd
|
||||
2 n/u
|
||||
@@ -131,9 +145,58 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
|
||||
6/7 00 768 bytes/blk
|
||||
01 1024 bytes/blk
|
||||
10 2048 bytes/blk
|
||||
char ldatrscnt; sectors per track (again)
|
||||
char ldatrmhdc; MHD head count
|
||||
char ldatrfhdc; FHD head count
|
||||
27 char ldatrscnt; sectors per track (again)
|
||||
28 char ldatrmhdc; MHD head count
|
||||
29 char ldatrfhdc; FHD head count
|
||||
30 uint32 lcrc; Label CRC-32 value
|
||||
*/
|
||||
|
||||
/*************************************/
|
||||
/* sector label definations 34 bytes */
|
||||
/*
|
||||
0 short lcyl; cylinder number
|
||||
2 char lhd; head number
|
||||
3 char lsec; sec # 0-15 or 0-19 for 16/20 format
|
||||
4 char lflg1; track/sector status flags
|
||||
bit 0 good sec
|
||||
1 alternate sec
|
||||
2 spare sec
|
||||
3 reserved sec
|
||||
4 defective sec
|
||||
5 last sec
|
||||
6-7 n/u = 0
|
||||
5 char lflg2;
|
||||
bit 0 write lock
|
||||
1 write protected
|
||||
2-7 n/u = 0
|
||||
6 short lspar1; n/u = 0
|
||||
8 short lspar2; n/u = 0
|
||||
10 short ldef1; defect #1 sec and byte position
|
||||
12 short ldef2; defect #2 sec and byte position
|
||||
14 short ldef3; defect #3 sec and byte position
|
||||
* for track 0 write UMAP which is DMAP - 2 * SPT
|
||||
* write sector number of cyl-4, hds-4, sec 0 value in 16-19
|
||||
* otherwise write zeros
|
||||
16 short lspar3; n/u = 0
|
||||
18 short lspar4; n/u = 0
|
||||
20 short lspar5; n/u = 0
|
||||
22 short laltcyl; alternate cylinder number or return cyl num
|
||||
24 char lalttk; alrernate track number or return track num
|
||||
25 char ldscnt; data sector count 16/20
|
||||
26 char ldatrflg; device attributes
|
||||
bit 0 n/u
|
||||
1 disk is mhd
|
||||
2 n/u
|
||||
3 n/u
|
||||
4 n/u
|
||||
5 dual ported
|
||||
6/7 00 768 bytes/blk
|
||||
01 1024 bytes/blk
|
||||
10 2048 bytes/blk
|
||||
27 char ldatrscnt; sectors per track (again)
|
||||
28 char ldatrmhdc; MHD head count
|
||||
29 char ldatrfhdc; FHD head count
|
||||
30 uint32 lcrc; Label CRC-32 value
|
||||
*/
|
||||
|
||||
#define CMD u3
|
||||
@@ -220,7 +283,7 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
|
||||
#define SNS_DADE 0x40 /* Disc addressing or seek error */
|
||||
#define SNS_BUCK 0x20 /* Buffer check */
|
||||
#define SNS_ECCS 0x10 /* ECC error in sector label */
|
||||
#define SNS_ECCD 0x08 /* ECC error iin data */
|
||||
#define SNS_ECCD 0x08 /* ECC error in data */
|
||||
#define SNS_ECCT 0x04 /* ECC error in track label */
|
||||
#define SNS_RTAE 0x02 /* Reserve track access error */
|
||||
#define SNS_UESS 0x01 /* Uncorrectable ECC error */
|
||||
@@ -292,11 +355,19 @@ disk_type[] =
|
||||
{
|
||||
/* Class F Disc Devices */
|
||||
/* For MPX */
|
||||
#ifndef NOTFORMPX1X
|
||||
{"MH040", 5, 192, 20, 407, 411, 0x40}, /* 0 411 40M XXXX */
|
||||
{"MH080", 5, 192, 20, 819, 823, 0x40}, /* 1 823 80M 8138 */
|
||||
{"MH160", 10, 192, 20, 819, 823, 0x40}, /* 2 823 160M 8148 */
|
||||
{"MH300", 19, 192, 20, 819, 823, 0x40}, /* 3 823 300M 8127 */
|
||||
{"MH600", 40, 192, 20, 839, 843, 0x40}, /* 4 843 600M 8155 */
|
||||
#else
|
||||
{"MH040", 5, 192, 20, 400, 411, 0x40}, /* 0 411 40M XXXX */
|
||||
{"MH080", 5, 192, 20, 800, 823, 0x40}, /* 1 823 80M 8138 */
|
||||
{"MH160", 10, 192, 20, 800, 823, 0x40}, /* 2 823 160M 8148 */
|
||||
{"MH300", 19, 192, 20, 800, 823, 0x40}, /* 3 823 300M 8127 */
|
||||
{"MH600", 40, 192, 20, 800, 843, 0x40}, /* 4 843 600M 8155 */
|
||||
#endif
|
||||
/* For UTX */
|
||||
{"9342", 5, 256, 16, 819, 823, 0x41}, /* 5 823 80M XXXX */
|
||||
{"8148", 10, 256, 16, 819, 823, 0x41}, /* 6 823 160M 8148 */
|
||||
@@ -968,7 +1039,7 @@ t_stat disk_srv(UNIT *uptr)
|
||||
// sim_activate(uptr, 20); /* start things off */
|
||||
sim_activate(uptr, 15); /* start things off */
|
||||
#else
|
||||
sim_activate(uptr, 150);
|
||||
sim_activate(uptr, 150); /* start things off */
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
@@ -1600,7 +1671,8 @@ t_stat disk_srv(UNIT *uptr)
|
||||
buf[0] = (cyl >> 8) & 0xff; /* lcyl cyl upper 8 bits */
|
||||
buf[1] = cyl & 0xff; /* lcyl cyl lower 8 bits */
|
||||
buf[2] = trk & 0xff; /* ltkn trk */
|
||||
buf[3] = sec & 0xff; /* lid sector ID */
|
||||
// buf[3] = sec & 0xff; /* lid sector ID */
|
||||
buf[3] = 0xff; /* lid show as track label */
|
||||
buf[4] = 0x80; /* show good sector */
|
||||
|
||||
sim_debug(DEBUG_DETAIL, dptr,
|
||||
@@ -1682,7 +1754,8 @@ t_stat disk_srv(UNIT *uptr)
|
||||
sim_debug(DEBUG_DETAIL, dptr, "\n");
|
||||
|
||||
/* leave STAR "unnormalized" for diags */
|
||||
uptr->CHS += 0x10; /* bump to next track */
|
||||
if (uptr->CHS != 0) /* only incr address if not trk 0 */
|
||||
uptr->CHS += 0x10; /* bump to next track */
|
||||
|
||||
/* command done */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
|
||||
@@ -23,6 +23,11 @@
|
||||
|
||||
#include "sel32_defs.h"
|
||||
|
||||
/* uncomment to use fast sim_activate times when running UTX */
|
||||
/* UTX gets an ioi error for dm0801 if slow times are used */
|
||||
/* dm0801 is not even a valid unit number for UDP controller */
|
||||
#define FAST_FOR_UTX
|
||||
|
||||
#if NUM_DEVS_HSDP > 0
|
||||
|
||||
#define UNIT_HSDP UNIT_ATTABLE | UNIT_IDLE | UNIT_DISABLE
|
||||
@@ -246,20 +251,20 @@ Byte 1 bits 7-15
|
||||
#define SNS_DIAGMOD 0x08000000 /* Diagnostic Mode ECC Code generation and checking */
|
||||
#define SNS_RSVTRK 0x04000000 /* Reserve Track mode: 1=OK to write, 0=read only */
|
||||
#define SNS_FHDOPT 0x02000000 /* FHD or FHD option = 1 */
|
||||
#define SNS_RESERV 0x01000000 /* Reserved */
|
||||
#define SNS_RES1 0x01000000 /* Reserved */
|
||||
|
||||
/* Sense byte 1 */
|
||||
#define SNS_CMDREJ 0x800000 /* Command reject */
|
||||
#define SNS_INTVENT 0x400000 /* Unit intervention required */
|
||||
#define SNS_SPARE1 0x200000 /* Spare */
|
||||
#define SNS_USELE 0x200000 /* Unit Select Error */
|
||||
#define SNS_EQUCHK 0x100000 /* Equipment check */
|
||||
#define SNS_DATCHK 0x080000 /* Data Check */
|
||||
#define SNS_OVRRUN 0x040000 /* Data overrun/underrun */
|
||||
#define SNS_RES2 0x080000 /* Reserved */
|
||||
#define SNS_RES3 0x040000 /* Reserved */
|
||||
#define SNS_DSKFERR 0x020000 /* Disk format error */
|
||||
#define SNS_DEFTRK 0x010000 /* Defective track encountered */
|
||||
|
||||
/* Sense byte 2 */
|
||||
#define SNS_LAST 0x8000 /* Last track flag encountered */
|
||||
#define SNS_RES4 0x8000 /* Reserved */
|
||||
#define SNS_AATT 0x4000 /* At Alternate track */
|
||||
#define SNS_WPER 0x2000 /* Write protection error */
|
||||
#define SNS_WRL 0x1000 /* Write lock error */
|
||||
@@ -271,11 +276,11 @@ Byte 1 bits 7-15
|
||||
/* Sense byte 3 */
|
||||
#define SNS_REVL 0x80 /* Revolution lost */
|
||||
#define SNS_DADE 0x40 /* Disc addressing or seek error */
|
||||
#define SNS_BUCK 0x20 /* Buffer check */
|
||||
#define SNS_ECCS 0x10 /* ECC error in sector label */
|
||||
#define SNS_ECCD 0x08 /* ECC error iin data */
|
||||
#define SNS_ECCT 0x04 /* ECC error in track label */
|
||||
#define SNS_RTAE 0x02 /* Reserve track access error */
|
||||
#define SNS_RES5 0x20 /* Reserved */
|
||||
#define SNS_RES6 0x10 /* Reserved */
|
||||
#define SNS_ECCD 0x08 /* ECC error in data */
|
||||
#define SNS_RES7 0x04 /* Reserved */
|
||||
#define SNS_RES8 0x02 /* Reserved */
|
||||
#define SNS_UESS 0x01 /* Uncorrectable ECC error */
|
||||
|
||||
#define SNS2 us9
|
||||
@@ -345,17 +350,20 @@ hsdp_type[] =
|
||||
/* Class F Disc Devices */
|
||||
/* For MPX */
|
||||
{"MH040", 5, 192, 20, 407, 411, 0x40}, /* 0 411 40M XXXX */
|
||||
{"MH080", 5, 192, 20, 819, 823, 0x40}, /* 1 823 80M 8138 */
|
||||
// {"MH080", 5, 192, 20, 819, 823, 0x40}, /* 1 823 80M 8138 */
|
||||
{"MH080", 5, 192, 22, 819, 823, 0x40}, /* 1 823 80M 8138 */
|
||||
{"MH160", 10, 192, 20, 819, 823, 0x40}, /* 2 823 160M 8148 */
|
||||
{"MH300", 19, 192, 20, 819, 823, 0x40}, /* 3 823 300M 9346 */
|
||||
{"MH600", 40, 192, 20, 839, 843, 0x40}, /* 4 843 600M 8155 */
|
||||
{"MH689", 16, 192, 54, 861, 865, 0x40}, /* 5 823 674M 8888 DP689 */
|
||||
/* For UTX */
|
||||
{"9342", 5, 256, 16, 819, 823, 0x41}, /* 5 823 80M 9342 MH080 */
|
||||
{"8148", 10, 256, 16, 819, 823, 0x41}, /* 6 823 160M 8146 MH160 */
|
||||
{"9346", 19, 256, 16, 819, 823, 0x41}, /* 7 823 300M 9344 MH300 */
|
||||
{"8858", 24, 256, 16, 707, 711, 0x41}, /* 8 711 340M 8858 DC340 */
|
||||
{"8887", 10, 256, 35, 819, 823, 0x41}, /* 9 823 337M 8887 DP337 */
|
||||
{"8155", 40, 256, 16, 839, 843, 0x41}, /* 10 843 600M 8155 MH600 */
|
||||
{"9342", 5, 256, 16, 819, 823, 0x41}, /* 6 823 80M 9342 MH080 */
|
||||
{"8148", 10, 256, 16, 819, 823, 0x41}, /* 7 823 160M 8146 MH160 */
|
||||
{"9346", 19, 256, 16, 819, 823, 0x41}, /* 8 823 300M 9344 MH300 */
|
||||
{"8858", 24, 256, 16, 707, 711, 0x41}, /* 9 711 340M 8858 DC340 */
|
||||
{"8887", 10, 256, 35, 819, 823, 0x41}, /* 10 823 337M 8887 DP337 */
|
||||
{"8155", 40, 256, 16, 839, 843, 0x41}, /* 11 843 600M 8155 MH600 */
|
||||
{"8888", 16, 256, 43, 861, 865, 0x41}, /* 12 823 674M 8888 DP689 */
|
||||
{NULL, 0}
|
||||
};
|
||||
|
||||
@@ -386,15 +394,15 @@ MTAB hsdp_mod[] = {
|
||||
|
||||
UNIT dpa_unit[] = {
|
||||
/* SET_TYPE(3) DM300 */
|
||||
/* SET_TYPE(8) 8887 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x800)}, /* 0 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x802)}, /* 1 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x804)}, /* 2 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x806)}, /* 3 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x808)}, /* 4 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x80A)}, /* 5 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x80C)}, /* 6 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(8), 0), 0, UNIT_ADDR(0x80E)}, /* 7 */
|
||||
/* SET_TYPE(10) 8887 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x800)}, /* 0 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x802)}, /* 1 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x804)}, /* 2 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x806)}, /* 3 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x808)}, /* 4 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x80A)}, /* 5 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x80C)}, /* 6 */
|
||||
{UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x80E)}, /* 7 */
|
||||
};
|
||||
|
||||
DIB dpa_dib = {
|
||||
@@ -530,16 +538,27 @@ uint16 hsdp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
|
||||
uptr->SNS &= ~SNS_CMDREJ; /* not rejected yet */
|
||||
uptr->CMD |= DSK_INCH2; /* use 0xF0 for inch, just need int */
|
||||
sim_activate(uptr, 20); /* start things off */
|
||||
#ifdef FAST_FOR_UTX
|
||||
// sim_activate(uptr, 20); /* start things off */
|
||||
sim_activate(uptr, 30); /* start things off */
|
||||
#else
|
||||
sim_activate(uptr, 250); /* start things off */
|
||||
#endif
|
||||
return SCPE_OK; /* good to go */
|
||||
break;
|
||||
|
||||
case DSK_NOP: /* NOP 0x03 */
|
||||
#ifdef NOT4HSDP
|
||||
if ((cmd == DSK_NOP) &&
|
||||
(chp->chan_info & INFO_SIOCD)) { /* is NOP 1st IOCD? */
|
||||
chp->chan_caw -= 8; /* backup iocd address for diags */
|
||||
break; /* yes, can't be 1st */
|
||||
}
|
||||
#endif
|
||||
case DSK_INC: /* 0xFF Initialize controller */
|
||||
if ((cmd == DSK_INC) &&
|
||||
(chp->ccw_count != 0x20)) /* count must be 32 to be valid */
|
||||
break;
|
||||
case DSK_SCK: /* Seek command 0x07 */
|
||||
case DSK_XEZ: /* Rezero & Read IPL record 0x1f */
|
||||
case DSK_WD: /* Write command 0x01 */
|
||||
@@ -558,7 +577,12 @@ uint16 hsdp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"hsdp_startcmd starting disk cmd %02x chsa %04x\n",
|
||||
cmd, chsa);
|
||||
sim_activate(uptr, 20); /* start things off */
|
||||
#ifdef FAST_FOR_UTX
|
||||
// sim_activate(uptr, 20); /* start things off */
|
||||
sim_activate(uptr, 30); /* start things off */
|
||||
#else
|
||||
sim_activate(uptr, 250); /* start things off */
|
||||
#endif
|
||||
return SCPE_OK; /* good to go */
|
||||
break;
|
||||
|
||||
@@ -567,6 +591,8 @@ uint16 hsdp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"hsdp_startcmd done with hsdp_startcmd %02x chsa %04x SNS %08x\n",
|
||||
cmd, chsa, uptr->SNS);
|
||||
/* diags want the chan addr to point at bad command?? */
|
||||
chp->chan_caw -= 8; /* backup iocd address for diags */
|
||||
uptr->SNS |= SNS_CMDREJ; /* cmd rejected */
|
||||
return SNS_CHNEND|SNS_DEVEND|STATUS_PCHK; /* return error */
|
||||
}
|
||||
@@ -645,6 +671,49 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
case 0: /* No command, stop disk */
|
||||
break;
|
||||
|
||||
case DSK_INC: /* 0xFF Initialize controller */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
len = chp->ccw_count; /* INCH command count */
|
||||
mema = chp->ccw_addr; /* get inch or buffer addr */
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"disk_srv cmd CONT INC %06x chsa %04x addr %06x count %04x completed\n",
|
||||
chp->chan_inch_addr, chsa, mema, chp->ccw_count);
|
||||
/* to use this inch method, byte count must be 0x20 */
|
||||
if (len != 0x20) {
|
||||
/* we have invalid count, error, bail out */
|
||||
uptr->SNS |= SNS_CMDREJ;
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
}
|
||||
/* read all 32 bytes, stopping every 4 bytes to make words */
|
||||
/* the 8 words have drive data for each unit */
|
||||
/* WARNING 8 drives must be defined for this controller */
|
||||
/* so we will not have a map fault */
|
||||
for (i=0; i < 32; i++) {
|
||||
if (chan_read_byte(chsa, &buf[i])) {
|
||||
if (chp->chan_status & STATUS_PCHK) /* test for memory error */
|
||||
uptr->SNS |= SNS_INAD; /* invalid address */
|
||||
/* we have error, bail out */
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
uptr->SNS |= SNS_CMDREJ;
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
}
|
||||
if (((i+1)%4) == 0) { /* see if we have a word yet */
|
||||
/* drive attribute registers */
|
||||
/* may want to use this later */
|
||||
/* clear warning errors */
|
||||
tstart = (buf[i-3]<<24) | (buf[i-2]<<16)
|
||||
| (buf[i-1]<<8) | (buf[i]);
|
||||
}
|
||||
}
|
||||
uptr->CMD &= LMASK; /* remove old cmd */
|
||||
sim_debug(DEBUG_CMD, dptr,
|
||||
"hsdp_srv cmd INC chsa %04x chsa %06x count %04x completed\n",
|
||||
chsa, mema, chp->ccw_count);
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
|
||||
break;
|
||||
|
||||
case DSK_INCH2: /* use 0xF0 for inch, just need int */
|
||||
len = chp->ccw_count; /* INCH command count */
|
||||
mema = chp->ccw_addr; /* get inch or buffer addr */
|
||||
@@ -970,7 +1039,12 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
sim_debug(DEBUG_CMD, dptr, "hsdp_srv seek over on cylinder unit=%02x %04x %04x\n",
|
||||
unit, uptr->STAR >> 16, uptr->CHS >> 16);
|
||||
uptr->CHS = uptr->STAR; /* we are there */
|
||||
sim_activate(uptr, 15);
|
||||
#ifdef FAST_FOR_UTX
|
||||
// sim_activate(uptr, 15);
|
||||
sim_activate(uptr, 20); /* start things off */
|
||||
#else
|
||||
sim_activate(uptr, 150); /* start things off */
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -1092,8 +1166,14 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
sim_debug(DEBUG_DETAIL, dptr,
|
||||
"hsdp_srv seek unit=%02x cyl %04x trk %02x sec %02x\n",
|
||||
unit, cyl, trk, buf[3]);
|
||||
sim_activate(uptr, 20); /* start us off */
|
||||
#ifdef FAST_FOR_UTX
|
||||
// sim_activate(uptr, 15);
|
||||
sim_activate(uptr, 20); /* start things off */
|
||||
// sim_activate(uptr, 20+diff); /* start us off */
|
||||
#else
|
||||
// sim_activate(uptr, 150); /* start things off */
|
||||
sim_activate(uptr, 200+diff); /* start us off */
|
||||
#endif
|
||||
} else {
|
||||
/* we are on cylinder/track/sector, so go on */
|
||||
sim_debug(DEBUG_DETAIL, dptr,
|
||||
@@ -1236,9 +1316,6 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
break;
|
||||
}
|
||||
|
||||
/* get sector offset */
|
||||
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
|
||||
|
||||
/* see of over end of disk */
|
||||
if (tstart >= (uint32)CAP(type)) {
|
||||
/* EOM reached, abort */
|
||||
@@ -1264,7 +1341,13 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
sim_debug(DEBUG_DATA, dptr,
|
||||
"HSDP sector read complete, %x bytes to go from diskfile /%04x/%02x/%02x\n",
|
||||
chp->ccw_count, STAR2CYL(uptr->CHS), ((uptr->CHS) >> 8)&0xff, (uptr->CHS&0xff));
|
||||
sim_activate(uptr, 10); /* wait to read next sector */
|
||||
#ifdef FAST_FOR_UTX
|
||||
// sim_activate(uptr, 10); /* wait to read next sector */
|
||||
// sim_activate(uptr, 15); /* wait to read next sector */
|
||||
sim_activate(uptr, 20); /* wait to read next sector */
|
||||
#else
|
||||
sim_activate(uptr, 150); /* wait to read next sector */
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
@@ -1358,7 +1441,12 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
|
||||
break;
|
||||
}
|
||||
sim_activate(uptr, 10); /* keep writing */
|
||||
#ifdef FAST_FOR_UTX
|
||||
// sim_activate(uptr, 10); /* keep writing */
|
||||
sim_activate(uptr, 15); /* keep writing */
|
||||
#else
|
||||
sim_activate(uptr, 150); /* wait to read next sector */
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
@@ -1642,11 +1730,12 @@ t_stat hsdp_srv(UNIT *uptr)
|
||||
sim_debug(DEBUG_CMD, dptr, "invalid command %02x unit %02x\n", cmd, unit);
|
||||
uptr->SNS |= SNS_CMDREJ;
|
||||
uptr->CMD &= LMASK; /* remove old status bits & cmd */
|
||||
return SNS_CHNEND|STATUS_PCHK;
|
||||
chan_end(chsa, SNS_CHNEND|STATUS_PCHK); /* return prog check */
|
||||
break;
|
||||
}
|
||||
sim_debug(DEBUG_DETAIL, dptr, "hsdp_srv done cmd=%02x chsa %04x count %04x\n",
|
||||
cmd, chsa, chp->ccw_count);
|
||||
sim_debug(DEBUG_DETAIL, dptr,
|
||||
"hsdp_srv done cmd %02x chsa %04x chs %04x/%02x/%02x\n",
|
||||
cmd, chsa, ((uptr->CHS)>>16)&0xffff, ((uptr->CHS)>>8)&0xff, (uptr->CHS)&0xff);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user