mirror of
https://github.com/rcornwell/sims.git
synced 2026-01-30 13:27:26 +00:00
KA10: Minor fixes to try and get ITS to work.
This commit is contained in:
Richard Cornwell
@@ -268,6 +268,7 @@ uint64 spt;
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uint64 cst;
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uint64 cst_msk;
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uint64 cst_dat;
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uint64 hsb;
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#endif
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#if KS_ITS
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@@ -534,6 +535,8 @@ REG cpu_reg[] = {
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{ ORDATAD (EXTEND, extend, 1, "Execute Extend"), REG_HRO},
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{ ORDATAD (SPT, spt, 18, "Special Page table"),},
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{ ORDATAD (CST, cst, 18, "Memory status table"),},
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{ ORDATAD (PU, cst_dat, 36, "User data"),},
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{ ORDATAD (CSTM, cst_msk, 36, "Status mask"),},
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#endif
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#if KL
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{ ORDATAD (EXT_AC, ext_ac, 4, "Extended Instruction AC"), REG_HRO},
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@@ -1801,7 +1804,7 @@ load_tlb(int uf, int page, int wr)
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pg = 0;
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switch(data >> 16) {
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case 0:
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fault_data = (data >> 16) << 28;
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fault_data = 0;
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page_fault = 1;
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return 0; /* No access */
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case 2: /* R/W First */
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@@ -1809,7 +1812,7 @@ load_tlb(int uf, int page, int wr)
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/* Fall through */
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case 1: /* Read Only */
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if (wr) {
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fault_data = (data >> 16) << 28;
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fault_data = ((data >> 16) << 28) | (010000LL << 18);
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page_fault = 1;
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return 0;
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}
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@@ -2086,9 +2089,6 @@ int page_lookup(t_addr addr, int flag, t_addr *loc, int wr, int cur_context, int
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fault_data |= SMASK;
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#if KS_ITS
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if (QITS) {
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if (wr) {
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fault_data |= 010000LL << 18;
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}
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return 0;
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}
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#endif
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@@ -2147,6 +2147,7 @@ int page_lookup(t_addr addr, int flag, t_addr *loc, int wr, int cur_context, int
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} else {
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e_tlb[page] = 0;
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}
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if (wr) {
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/* Check if accessable */
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if ((data & KL_PAG_A) != 0) {
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if ((data & KL_PAG_S) != 0) {
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@@ -2159,6 +2160,7 @@ int page_lookup(t_addr addr, int flag, t_addr *loc, int wr, int cur_context, int
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if (wr) {
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fault_data |= 010000LL << 18;
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}
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}
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page_fault = 1;
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return 0;
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}
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@@ -4433,9 +4435,13 @@ no_fetch:
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/* Handle page fault and traps */
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if (page_enable && trap_flag == 0 && (FLAGS & (TRP1|TRP2))) {
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if (FLAGS & ADRFLT) {
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#if KL_ITS | KS_ITS
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#if KL_ITS
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if (QITS && (FLAGS & (TRP1|TRP2|ADRFLT)) == (TRP1|TRP2|ADRFLT))
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one_p_arm = 1;
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#endif
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#if KS_ITS
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if (QITS)
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one_p_arm = 1;
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#endif
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FLAGS &= ~ADRFLT;
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} else {
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@@ -6211,6 +6217,12 @@ unasign:
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FLAGS |= ONEP;
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one_p_arm = 0;
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}
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#endif
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#if KS_ITS
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if (QITS && one_p_arm) {
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FLAGS |= ADRFLT;
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one_p_arm = 0;
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}
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#endif
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f_load_pc = 0;
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#endif
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@@ -10875,9 +10887,20 @@ skip_op:
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case 002: /* CLRPT */
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f = (RMASK & AB) >> 9;
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#if KS_ITS
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if (QITS) {
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u_tlb[f & ~1] = 0;
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e_tlb[f & ~1] = 0;
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u_tlb[f | 1] = 0;
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e_tlb[f | 1] = 0;
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} else {
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#endif
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/* Map the page */
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u_tlb[f] = 0;
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e_tlb[f] = 0;
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#if KS_ITS
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}
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#endif
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/* If not user do exec mappping */
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if (!t20_page && (f & 0740) == 0340) {
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/* Pages 340-377 via UBT */
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@@ -11029,6 +11052,12 @@ skip_op:
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/* 70230 */
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case 006: /* RDHSB */
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MB = hsb;
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sim_debug(DEBUG_CONI, &cpu_dev, "RDHSB %012llo\n", MB);
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if (Mem_write(0, 0))
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goto last;
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AR = MB;
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break;
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/* 70234 */
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case 007: /* ITS SPM */
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@@ -11048,9 +11077,13 @@ skip_op:
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case 010: /* WRSPB */ /* ITS LDBR1 */
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#if KS_ITS
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if (QITS) {
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dbr1 = AB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR1 %012llo\n", dbr1);
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break;
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dbr1 = AB;
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for (f = 0; f < 512; f++) {
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u_tlb[f] = 0;
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e_tlb[f] = 0;
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}
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR1 %012llo\n", dbr1);
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break;
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}
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#endif
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if (Mem_read(0, 0, 0, 0))
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@@ -11063,13 +11096,17 @@ skip_op:
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case 011: /* WRCSB */ /* ITS LDBR2 */
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#if KS_ITS
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if (QITS) {
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dbr2 = AB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR2 %012llo\n", dbr2);
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break;
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dbr2 = AB;
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for (f = 0; f < 512; f++) {
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u_tlb[f] = 0;
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e_tlb[f] = 0;
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}
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR2 %012llo\n", dbr2);
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break;
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}
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#endif
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if (Mem_read(0, 0, 0, 0))
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goto last;
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goto last;
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cst = MB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRCSB %012llo\n", cst);
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break;
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@@ -11078,13 +11115,17 @@ skip_op:
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case 012: /* WRPUR */ /* ITS LDBR3 */
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#if KS_ITS
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if (QITS) {
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dbr3 = AB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR3 %012llo\n", dbr3);
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break;
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dbr3 = AB;
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for (f = 0; f < 512; f++) {
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u_tlb[f] = 0;
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e_tlb[f] = 0;
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}
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR3 %012llo\n", dbr3);
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break;
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}
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#endif
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if (Mem_read(0, 0, 0, 0))
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goto last;
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goto last;
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cst_dat = MB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRPUR %012llo\n", cst_dat);
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break;
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@@ -11093,13 +11134,17 @@ skip_op:
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case 013: /* WRCSTM */ /* ITS LDBR4 */
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#if KS_ITS
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if (QITS) {
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dbr4 = AB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR4 %012llo\n", dbr4);
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break;
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dbr4 = AB;
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for (f = 0; f < 512; f++) {
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u_tlb[f] = 0;
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e_tlb[f] = 0;
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}
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sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR4 %012llo\n", dbr4);
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break;
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}
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#endif
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if (Mem_read(0, 0, 0, 0))
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goto last;
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goto last;
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cst_msk = MB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRCSTM %012llo\n", cst_msk);
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break;
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@@ -11117,7 +11162,7 @@ skip_op:
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if (Mem_read(0, 0, 0, 0))
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goto last;
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tim_low = MB & ~07777;
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sim_debug(DEBUG_CONI, &cpu_dev, "RDTIME %012llo %012llo\n", MB, tim_high);
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sim_debug(DEBUG_CONI, &cpu_dev, "WRTIME %012llo %012llo\n", MB, tim_high);
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AB = (AB + 1) & RMASK;
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if (Mem_read(0, 0, 0, 0))
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goto last;
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@@ -11125,6 +11170,10 @@ skip_op:
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break;
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/* 70270 */
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case 016: /* WRHSB */
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if (Mem_read(0, 0, 0, 0))
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goto last;
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hsb = MB;
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sim_debug(DEBUG_CONI, &cpu_dev, "WRHSB %012llo\n", MB);
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break;
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/* 70274 */
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@@ -11754,6 +11803,9 @@ fprintf(stderr, "PIH = %03o\n\r", PIH);
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AB += 3;
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}
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}
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if (one_p_arm)
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FLAGS |= ADRFLT;
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one_p_arm = 0;
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} else
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#endif
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AB = ub_ptr + 0500;
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@@ -13321,6 +13373,9 @@ sect = cur_sect = pc_sect = 0;
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exec_map = 0;
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#endif
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for(i=0; i < 128; dev_irq[i++] = 0);
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#if KS | KL
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cst = 0;
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#endif
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#if KS
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int_cur = int_val = 0;
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uba_reset();
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