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KA10: Fixed KI10 paging, CPU support for WAITS
This commit is contained in:
Richard Cornwell
parent
cd8f6509c3
commit
faac9f1d72
128
PDP10/ka10_cpu.c
128
PDP10/ka10_cpu.c
@ -442,6 +442,10 @@ MTAB cpu_mod[] = {
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{ UNIT_M_PAGE, UNIT_BBNPAGE, "BBN", "BBN", NULL, NULL, NULL,
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"Paging hardware for TENEX"},
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#endif
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#if WAITS
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{ UNIT_M_PAGE, UNIT_WAITSPG, "WAITS", "WAITS", NULL, NULL, NULL,
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"Support for WAITS XCTR"},
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#endif
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#if MPX_DEV
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{ UNIT_M_MPX, UNIT_MPX, "MPX", "MPX", NULL, NULL, NULL,
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"MPX Device for ITS"},
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@ -790,6 +794,11 @@ int opflags[] = {
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#else
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#define QBBN 0
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#endif
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#if WAITS
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#define QWAITS (cpu_unit[0].flags & UNIT_WAITSPG)
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#else
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#define QWAITS 0
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#endif
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/*
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* Set device to interrupt on a given level 1-7
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@ -1351,7 +1360,6 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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int page = (RMASK & addr) >> 9;
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int uf = (FLAGS & USER) != 0;
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int upmp = 0;
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int wf = wr;
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if (page_fault)
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return 0;
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@ -1364,17 +1372,17 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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/* If fetching byte data, use write access */
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if (BYF5 && (IR & 06) == 6)
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wf = 1;
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wr = 1;
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/* If this is modify instruction use write access */
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wf |= modify;
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wr |= modify;
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/* Figure out if this is a user space access */
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if (flag)
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uf = 0;
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else if (xct_flag != 0 && !cur_context && !uf) {
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if (((xct_flag & 2) != 0 && wf != 0) ||
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((xct_flag & 1) != 0 && (wf == 0 || modify))) {
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if (((xct_flag & 2) != 0 && wr != 0) ||
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((xct_flag & 1) != 0 && (wr == 0 || modify))) {
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uf = (FLAGS & USERIO) != 0;
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}
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}
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@ -1449,7 +1457,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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}
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if (cur_context && ((data & 0200000) != 0))
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FLAGS |= PUBLIC;
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if ((data & RSIGN) == 0 || (wf & ((data & 0100000) == 0))) {
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if ((data & RSIGN) == 0 || (wr & ((data & 0100000) == 0))) {
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fault_data = ((((uint64)(addr))<<9) | ((uint64)(uf) << 27)) & LMASK;
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fault_data |= (data & 0400000) ? 010LL : 0LL; /* A */
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fault_data |= (data & 0100000) ? 004LL : 0LL; /* W */
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@ -2156,6 +2164,100 @@ int Mem_write_bbn(int flag, int cur_context) {
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}
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#endif
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#if WAITS
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int page_lookup_waits(int addr, int flag, int *loc, int wr, int cur_context, int fetch) {
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int uf = (FLAGS & USER) != 0;
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if (page_fault)
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return 0;
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/* If paging is not enabled, address is direct */
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if (!page_enable) {
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*loc = addr;
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return 1;
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}
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/* If this is modify instruction use write access */
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wr |= modify;
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/* Figure out if this is a user space access */
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if (flag)
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uf = 0;
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else if (xct_flag != 0) {
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if (xct_flag & 010 && cur_context) /* Indirect */
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uf = 1;
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if (xct_flag & 004 && wr == 0) /* XR */
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uf = 1;
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if (xct_flag & 001 && (wr == 1 || BYF5)) /* XW or XLB or XDB */
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uf = 1;
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}
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if (uf) {
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if (addr <= Pl) {
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*loc = (addr + Rl) & RMASK;
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return 1;
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}
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if ((addr & 0400000) != 0 && (addr <= Ph)) {
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if ((Pflag == 0) || (Pflag == 1 && wr == 0)) {
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*loc = (addr + Rh) & RMASK;
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return 1;
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}
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}
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mem_prot = 1;
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return 0;
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} else {
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*loc = addr;
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}
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return 1;
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}
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int Mem_read_waits(int flag, int cur_context, int fetch) {
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int addr;
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if (AB < 020) {
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MB = get_reg(AB);
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} else {
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sim_interval--;
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if (!page_lookup_waits(AB, flag, &addr, 0, cur_context, fetch))
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return 1;
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if (addr >= (int)MEMSIZE) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('R')))
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watch_stop = 1;
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MB = M[addr];
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}
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return 0;
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}
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/*
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* Write a location in memory.
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*
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* Return of 0 if successful, 1 if there was an error.
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*/
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int Mem_write_waits(int flag, int cur_context) {
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int addr;
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if (AB < 020) {
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set_reg(AB, MB);
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} else {
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sim_interval--;
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if (!page_lookup_waits(AB, flag, &addr, 1, cur_context, 0))
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return 1;
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if (addr >= (int)MEMSIZE) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('W')))
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watch_stop = 1;
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M[addr] = MB;
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}
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return 0;
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}
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#endif
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int page_lookup_ka(int addr, int flag, int *loc, int wr, int cur_context, int fetch) {
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if (!flag && (FLAGS & USER) != 0) {
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if (addr <= Pl) {
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@ -2525,7 +2627,7 @@ no_fetch:
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#if KI | KL
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/* Handle page fault and traps */
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if (pi_enable && page_enable && trap_flag == 0 && (FLAGS & (TRP1|TRP2))) {
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if (page_enable && trap_flag == 0 && (FLAGS & (TRP1|TRP2))) {
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AB = 0420 + ((FLAGS & (TRP1|TRP2)) >> 2);
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trap_flag = FLAGS & (TRP1|TRP2);
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FLAGS &= ~(TRP1|TRP2);
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@ -3453,7 +3555,7 @@ dpnorm:
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}
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#endif
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/* UUO */
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case 0105: case 0106: case 0107:
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case 0105: case 0106: case 0107:
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case 0110: case 0111: case 0112: case 0113:
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case 0114: case 0115: case 0116: case 0117:
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case 0120: case 0121: case 0122: case 0123:
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@ -4749,6 +4851,10 @@ left:
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if ((FLAGS & USER) == 0)
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xct_flag = AC;
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#endif
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#if WAITS
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if (QWAITS && (FLAGS & USER) == 0)
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xct_flag = AC;
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#endif
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#if ITS
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if (QITS && one_p_arm) {
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FLAGS |= ONEP;
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@ -5939,6 +6045,12 @@ if (QBBN) {
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Mem_write = &Mem_write_bbn;
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}
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#endif
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#if WAITS
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if (QWAITS) {
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Mem_read = &Mem_read_waits;
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Mem_write = &Mem_write_waits;
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}
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#endif
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#endif
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/* Clear device and interrupt table */
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@ -80,6 +80,11 @@
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#define BBN KA
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#endif
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/* Support for WAITS mods */
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#ifndef WAITS
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#define WAITS KA
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#endif
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/* MPX interrupt multiplexer for ITS systems */
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#define MPX_DEV ITS
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@ -305,8 +310,9 @@ extern DEBTAB crd_debug[];
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#define UNIT_TWOSEG (1 << UNIT_V_PAGE)
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#define UNIT_ITSPAGE (2 << UNIT_V_PAGE)
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#define UNIT_BBNPAGE (4 << UNIT_V_PAGE)
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#define UNIT_M_PAGE (7 << UNIT_V_PAGE)
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#define UNIT_V_MPX (UNIT_V_PAGE + 3)
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#define UNIT_WAITSPG (8 << UNIT_V_PAGE)
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#define UNIT_M_PAGE (017 << UNIT_V_PAGE)
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#define UNIT_V_MPX (UNIT_V_PAGE + 4)
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#define UNIT_MPX (1 << UNIT_V_MPX) /* MPX Device for ITS */
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#define UNIT_M_MPX (1 << UNIT_V_MPX)
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@ -450,7 +456,7 @@ int auxcpu_write (int addr, t_uint64);
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#define NUM_DEVS_RP 4
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#define NUM_DEVS_RS 1
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#define NUM_DEVS_TU 1
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#define NUM_DEVS_PMP 0
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#define NUM_DEVS_PMP WAITS
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#define NUM_DEVS_PD ITS
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#define NUM_DEVS_IMX ITS
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#define NUM_DEVS_STK ITS
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