github.com/rdolbeau.SBusFPGA
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not working, the DMA seems to fails at frame 3...

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This commit is contained in:
Romain Dolbeau
2021-06-19 11:40:36 -04:00
parent c649cc4440
commit 0297df0131
3 changed files with 82 additions and 32 deletions
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43
sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
View File

@@ -64,13 +64,12 @@ def siz_to_burst_size_m1(siz):
return 1
class LedDisplay(Module):
def __init__(self): #, pads
#n = len(pads)
n = 8
def __init__(self, pads):
n = len(pads)
self.value = Signal(32, reset = 0x18244281)
old_value = Signal(32)
self.display = Signal(8)
#self.comb += pads.eq(self.display)
self.comb += pads.eq(self.display)
self.submodules.fsm = fsm = FSM(reset_state="Reset")
time_counter = Signal(32, reset = 0)
@@ -165,6 +164,24 @@ class SBusFPGABus(Module):
#self.comb += SBUS_DATA_OE_LED_o.eq(~rd_fifo_addr.writable)
#self.comb += SBUS_DATA_OE_LED_2_o.eq(rd_fifo_data.readable)
#leds = Signal(7, reset=0x00)
#self.comb += platform.request("user_led", 0).eq(leds[0])
#self.comb += platform.request("user_led", 1).eq(leds[1])
#self.comb += platform.request("user_led", 2).eq(leds[2])
#self.comb += platform.request("user_led", 3).eq(leds[3])
#self.comb += platform.request("user_led", 4).eq(leds[4])
#self.comb += platform.request("user_led", 5).eq(leds[5])
#self.comb += platform.request("user_led", 6).eq(leds[6])
##self.comb += platform.request("user_led", 7).eq(leds[7])
#self.comb += leds[0].eq(self.wr_fifo.writable)
#self.comb += leds[1].eq(~self.rd_fifo_data.readable)
#self.comb += leds[2].eq(self.rd_fifo_addr.writable)
#self.comb += leds[4].eq(~self.master_wr_fifo.readable)
#self.comb += leds[5].eq(self.master_rd_fifo_data.writable)
#self.comb += leds[6].eq(~self.master_rd_fifo_addr.readable)
#pad_SBUS_3V3_CLK = platform.request("SBUS_3V3_CLK")
pad_SBUS_3V3_ASs = platform.request("SBUS_3V3_ASs")
@@ -243,7 +260,7 @@ class SBusFPGABus(Module):
master_we = Signal();
# self.submodules.led_display = LedDisplay()
self.submodules.led_display = LedDisplay(platform.request_all("user_led"))
# #self.comb += self.led_display.value.eq(Cat(Signal(2, reset=0), master_addr))
# self.comb += self.led_display.value.eq(p_data)
# old_display = Signal(8)
@@ -517,6 +534,8 @@ class SBusFPGABus(Module):
)
# ##### MASTER #####
slave_fsm.act("Master_Translation",
If(master_addr[22:30] == 0xFC,
NextValue(self.led_display.value, Cat(master_we, Signal(1, reset = 0), master_addr))),
If(master_we,
NextValue(sbus_oe_data, 1),
NextValue(SBUS_3V3_D_o, master_data)
@@ -559,14 +578,18 @@ class SBusFPGABus(Module):
ACK_IDLE:
[NextState("Master_Read") ## redundant
],
ACK_RERUN: ### dunno how to handle that yet, maybe delay the fifo re(1)?
[NextValue(sbus_oe_data, 0),
ACK_RERUN: ### burst not handled
[self.master_rd_fifo_data.we.eq(1),
NextValue(self.master_rd_fifo_data.din, Cat(0xDEADBEEF, Signal(1, reset = 1))),
NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextState("Idle")
],
"default": ## ACK_ERRS or other
[NextValue(sbus_oe_data, 0),
"default": ## ACK_ERRS or other ### burst not handled
[self.master_rd_fifo_data.we.eq(1),
NextValue(self.master_rd_fifo_data.din, Cat(0xDEADBEEF, Signal(1, reset = 1))),
NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextState("Idle")
@@ -575,7 +598,7 @@ class SBusFPGABus(Module):
)
slave_fsm.act("Master_Read_Ack",
self.master_rd_fifo_data.we.eq(1),
NextValue(self.master_rd_fifo_data.din, SBUS_3V3_D_i),
NextValue(self.master_rd_fifo_data.din, Cat(SBUS_3V3_D_i, Signal(1, reset = 0))),
NextValue(burst_counter, burst_counter + 1),
If(burst_counter == burst_limit_m1,
NextState("Master_Read_Finish")

28
sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
View File

@@ -45,11 +45,11 @@ _usb_io = [
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by SBus, SoC/Wishbone main clock
self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset)
self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by SBus (via pll), SoC/Wishbone main clock
self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset, we don't want the delay after a warm reset)
self.clock_domains.cd_sbus = ClockDomain() # 16.67-25 MHz SBus, reset'ed by SBus, native SBus clock domain
self.clock_domains.cd_por = ClockDomain() # 48 MHz native, reset'ed by SBus, power-on-reset timer
self.clock_domains.cd_usb = ClockDomain() # 48 MHZ PLL, reset'ed by SBus, for USB controller
# self.clock_domains.cd_por = ClockDomain() # 48 MHz native, reset'ed by SBus, power-on-reset timer
self.clock_domains.cd_usb = ClockDomain() # 48 MHZ PLL, reset'ed by SBus (via pll), for USB controller
# # #
clk48 = platform.request("clk48")
@@ -57,7 +57,6 @@ class _CRG(Module):
clk_sbus = platform.request("SBUS_3V3_CLK")
self.cd_sbus.clk = clk_sbus
rst_sbus = platform.request("SBUS_3V3_RSTs")
self.comb += self.cd_sbus.rst.eq(~rst_sbus)
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
@@ -70,18 +69,19 @@ class _CRG(Module):
platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_sys.clk)
# Power on reset, reset propagate from SBus to SYS
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
self.comb += pll.reset.eq(~por_done | ~rst_sbus)
# por_count = Signal(16, reset=2**16-1)
# por_done = Signal()
# self.comb += self.cd_por.clk.eq(clk48)
# self.comb += por_done.eq(por_count == 0)
# self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# self.comb += self.cd_por.rst.eq(~rst_sbus)
# self.comb += pll.reset.eq(~por_done | ~rst_sbus)
# USB
self.submodules.usb_pll = usb_pll = S7MMCM(speedgrade=-1)
self.comb += usb_pll.reset.eq(~por_done | ~rst_sbus)
usb_pll.register_clkin(clk48, 48e6)
usb_pll.create_clkout(self.cd_usb, 48e6, margin = 0)
self.comb += usb_pll.reset.eq(~rst_sbus) # | ~por_done
platform.add_false_path_constraints(self.cd_sys.clk, self.cd_usb.clk)
class SBusFPGA(SoCCore):
@@ -109,7 +109,7 @@ class SBusFPGA(SoCCore):
self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6) # SBus max
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
pads = platform.request("SBUS_DATA_OE_LED_2"), #platform.request("user_led", 7),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
@@ -186,7 +186,7 @@ class SBusFPGA(SoCCore):
wishbone_to_sbus_rd_fifo_addr = AsyncFIFOBuffered(width=30, depth=4)
wishbone_to_sbus_rd_fifo_addr = ClockDomainsRenamer({"write": "sys", "read": "sbus"})(wishbone_to_sbus_rd_fifo_addr)
self.submodules += wishbone_to_sbus_rd_fifo_addr
wishbone_to_sbus_rd_fifo_data = AsyncFIFOBuffered(width=32, depth=4)
wishbone_to_sbus_rd_fifo_data = AsyncFIFOBuffered(width=32+1, depth=4)
wishbone_to_sbus_rd_fifo_data = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(wishbone_to_sbus_rd_fifo_data)
self.submodules += wishbone_to_sbus_rd_fifo_data

43
sbus-to-ztex-gateware-migen/sbus_to_fpga_wishbone.py
View File

@@ -20,7 +20,7 @@ class SBusToWishbone(Module):
data = Signal(32)
adr = Signal(30)
timeout = Signal(7)
timeout = Signal(9)
# ##### FSM: read/write from/to WB #####
self.submodules.fsm = fsm = FSM(reset_state="Reset")
@@ -36,12 +36,12 @@ class SBusToWishbone(Module):
self.wr_fifo.re.eq(1),
NextValue(adr, self.wr_fifo.dout[0:30]),
NextValue(data, self.wr_fifo.dout[30:62]),
NextValue(timeout, 127),
NextValue(timeout, 511),
NextState("Write")
).Elif (rd_fifo_addr.readable & ~self.wishbone.cyc & self.rd_fifo_data.writable,
rd_fifo_addr.re.eq(1),
NextValue(adr, self.rd_fifo_addr.dout[0:30]),
NextValue(timeout, 127),
NextValue(timeout, 511),
NextState("Read")
)
)
@@ -105,6 +105,7 @@ class WishboneToSBus(Module):
data = Signal(32)
adr = Signal(30)
timeout = Signal(9)
# ##### FSM: read/write from/to SBus #####
self.submodules.fsm = fsm = FSM(reset_state="Reset")
@@ -117,6 +118,7 @@ class WishboneToSBus(Module):
self.wr_fifo.we.eq(1),
self.wr_fifo.din.eq(Cat(self.wishbone.adr[0:30], self.wishbone.dat_w[0:32]))
),
NextValue(timeout, 511),
NextState("WriteWait")
).Elif(self.wishbone.stb & self.wishbone.cyc & ~self.wishbone.we & self.rd_fifo_addr.writable,
If(self.wishbone.adr[24:30] == 0x3f, ## in our DMA range
@@ -124,6 +126,7 @@ class WishboneToSBus(Module):
self.rd_fifo_addr.we.eq(1),
self.rd_fifo_addr.din.eq(self.wishbone.adr[0:30])
),
NextValue(timeout, 511),
NextState("ReadWait"),
)
)
@@ -133,18 +136,30 @@ class WishboneToSBus(Module):
).Else(
self.wishbone.err.eq(1)
),
NextValue(timeout, timeout - 1),
If(~self.wishbone.stb,
NextState("Idle")
).Elif(timeout == 0, # fixme, what to do to signal a problem ?
NextState("Idle")
)
)
fsm.act("ReadWait",
NextValue(timeout, timeout - 1),
If(adr[24:30] == 0x3f, ## in our DMA range
If(self.rd_fifo_data.readable,
self.wishbone.ack.eq(1),
self.rd_fifo_data.re.eq(1),
NextValue(data, self.rd_fifo_data.dout),
self.wishbone.dat_r.eq(self.rd_fifo_data.dout),
NextState("ReadWait2")
If(self.rd_fifo_data.dout[32] == 0,
self.wishbone.ack.eq(1),
self.rd_fifo_data.re.eq(1),
NextValue(data, self.rd_fifo_data.dout),
self.wishbone.dat_r.eq(self.rd_fifo_data.dout[0:32]),
NextState("ReadWait2")
).Else(
self.wishbone.err.eq(1),
self.rd_fifo_data.re.eq(1),
NextState("ReadWaitErr")
)
).Elif(timeout == 0, # fixme, what to do to signal a problem ?
NextState("Idle")
)
).Else(
self.wishbone.err.eq(1),
@@ -154,9 +169,21 @@ class WishboneToSBus(Module):
)
)
fsm.act("ReadWait2",
NextValue(timeout, timeout - 1),
self.wishbone.ack.eq(1),
self.wishbone.dat_r.eq(data),
If(~self.wishbone.stb,
NextState("Idle")
).Elif(timeout == 0, # fixme, what to do to signal a problem ?
NextState("Idle")
)
)
fsm.act("ReadWaitErr",
NextValue(timeout, timeout - 1),
self.wishbone.err.eq(1),
If(~self.wishbone.stb,
NextState("Idle")
).Elif(timeout == 0, # fixme, what to do to signal a problem ?
NextState("Idle")
)
)