Oups forgot the DMA engine (this version with wishbone Converter)
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Romain Dolbeau
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cd9fa81a82
commit
0bd6b69dd9
176
sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py
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176
sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py
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from migen import *
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from migen.genlib.fifo import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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# width of towrite_fifo is '32'+'burst_size * 32' (vaddr + data)
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# so the SBus DMA has all the needed info
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# width of fromsbus_req_fifo is 'blk_addr_width' + 'vaddr' (blk_addr + vaddr)
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# width of fromsbus_fifo is 'blk_addr_width' + 'burst_size * 32' (blk_addr + data)
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# the blk_addr does the round-trip to accompany the data
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class ExchangeWithMem(Module, AutoCSR):
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def __init__(self, soc, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, burst_size = 8):
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self.wishbone_r_slave = wishbone.Interface(data_width=soc.bus.data_width)
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self.wishbone_w_slave = wishbone.Interface(data_width=soc.bus.data_width)
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self.tosbus_fifo = tosbus_fifo
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self.fromsbus_fifo = fromsbus_fifo
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self.fromsbus_req_fifo = fromsbus_req_fifo
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data_width = burst_size * 4
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data_width_bits = burst_size * 32
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blk_addr_width = 32 - log2_int(data_width) # 27 for burst_size == 8
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self.wishbone_r_master = wishbone.Interface(data_width=data_width_bits)
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self.wishbone_w_master = wishbone.Interface(data_width=data_width_bits)
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self.submodules += wishbone.Converter(self.wishbone_r_master, self.wishbone_r_slave)
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self.submodules += wishbone.Converter(self.wishbone_w_master, self.wishbone_w_slave)
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print("ExchangeWithMem: data_width = {}, data_width_bits = {}, blk_addr_width = {}\n".format(data_width, data_width_bits, blk_addr_width))
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print("ExchangeWithMem: tosbus_fifo width = {}, fromsbus_fifo width = {}, fromsbus_req_fifo width = {}\n".format(len(tosbus_fifo.din), len(fromsbus_fifo.dout), len(fromsbus_req_fifo.din)))
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local_r_addr = Signal(blk_addr_width)
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dma_r_addr = Signal(32)
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#local_r_widx = Signal(log2_int(burst_size)) # so width is 3 for burst_size == 8
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#local_r_buffer = Signal(data_width_bits)
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local_w_addr = Signal(blk_addr_width)
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dma_w_addr = Signal(32)
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#local_w_widx = Signal(log2_int(burst_size)) # so width is 3 for burst_size == 8
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#local_w_buffer = Signal(data_width_bits)
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max_block_bits=16
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# CSRConstant do not seem to appear in the CSR Map, but they need to be accessible to the OS driver
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#self.blk_size = CSRConstant(value=data_width) # report the block size to the SW layer
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#self.blk_base = CSRConstant(value=soc.wb_mem_map["main_ram"] >> log2_int(data_width)) # report where the blk starts
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self.blk_size = CSRStatus(32) # report the block size to the SW layer
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self.blk_base = CSRStatus(32) # report where the blk starts
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self.comb += self.blk_size.status.eq(data_width)
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self.comb += self.blk_base.status.eq(soc.wb_mem_map["main_ram"] >> log2_int(data_width))
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self.blk_addr = CSRStorage(32, description = "SDRAM Block address to read/write from Wishbone memory (block of size {})".format(data_width))
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self.dma_addr = CSRStorage(32, description = "Host Base address where to write/read data (i.e. SPARC Virtual addr)")
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self.blk_cnt = CSRStorage(32, write_from_dev=True, description = "How many blk to read/write (max 2^{}-1); bit 31 is RD".format(max_block_bits), reset = 0)
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self.last_blk = CSRStatus(32, description = "Last Blk addr finished on WB side")
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self.last_dma = CSRStatus(32, description = "Last DMA addr finished on WB side")
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self.blk_rem = CSRStatus(32, description = "How many block remaining; bit 31 is RD", reset = 0)
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self.dma_status = CSRStatus(32, description = "Status register")
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self.wr_tosdram = CSRStatus(32, description = "Last address written to SDRAM")
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self.submodules.req_r_fsm = req_r_fsm = FSM(reset_state="Reset")
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self.submodules.req_w_fsm = req_w_fsm = FSM(reset_state="Reset")
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self.comb += self.dma_status.status[0:1].eq(~req_r_fsm.ongoing("Idle")) # Read FSM Busy
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self.comb += self.dma_status.status[1:2].eq(~req_w_fsm.ongoing("Idle")) # Write FSM Busy
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self.comb += self.dma_status.status[2:3].eq(self.fromsbus_fifo.readable) # Some data available to write to memory
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self.comb += self.dma_status.status[8:9].eq(req_w_fsm.ongoing("ReqToMemory"))
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self.comb += self.dma_status.status[9:10].eq(req_w_fsm.ongoing("WaitForAck"))
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self.comb += self.dma_status.status[16:17].eq(self.wishbone_w_master.cyc) # show the WB iface status (W)
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self.comb += self.dma_status.status[17:18].eq(self.wishbone_w_master.stb)
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self.comb += self.dma_status.status[18:19].eq(self.wishbone_w_master.we)
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self.comb += self.dma_status.status[19:20].eq(self.wishbone_w_master.ack)
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self.comb += self.dma_status.status[20:21].eq(self.wishbone_w_master.err)
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self.comb += self.dma_status.status[24:25].eq(self.wishbone_r_master.cyc) # show the WB iface status (R)
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self.comb += self.dma_status.status[25:26].eq(self.wishbone_r_master.stb)
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self.comb += self.dma_status.status[26:27].eq(self.wishbone_r_master.we)
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self.comb += self.dma_status.status[27:28].eq(self.wishbone_r_master.ack)
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self.comb += self.dma_status.status[28:29].eq(self.wishbone_r_master.err)
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req_r_fsm.act("Reset",
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NextState("Idle")
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)
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req_r_fsm.act("Idle",
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If(((self.blk_cnt.storage[0:max_block_bits] != 0) & # checking self.blk_cnt.re might be too transient ? -> need to auto-reset
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(~self.blk_cnt.storage[31:32])), # !read -> write
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NextValue(local_r_addr, self.blk_addr.storage),
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NextValue(dma_r_addr, self.dma_addr.storage),
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NextValue(self.blk_rem.status, Cat(self.blk_cnt.storage[0:max_block_bits], Signal(32-max_block_bits, reset = 0))),
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NextState("ReqFromMemory")
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).Elif(((self.blk_cnt.storage[0:max_block_bits] != 0) & # checking self.blk_cnt.re might be too transient ? -> need to auto-reset
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(self.blk_cnt.storage[31:32])), # read
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NextValue(local_r_addr, self.blk_addr.storage),
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NextValue(dma_r_addr, self.dma_addr.storage),
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NextValue(self.blk_rem.status, Cat(self.blk_cnt.storage[0:max_block_bits], Signal(32-max_block_bits, reset = 0))),
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NextState("QueueReqToMemory")
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)
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)
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req_r_fsm.act("ReqFromMemory",
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If(~self.wishbone_r_master.ack,
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NextValue(self.wishbone_r_master.cyc, 1),
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NextValue(self.wishbone_r_master.stb, 1),
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NextValue(self.wishbone_r_master.sel, 2**len(self.wishbone_r_master.sel)-1),
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NextValue(self.wishbone_r_master.we, 0),
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NextValue(self.wishbone_r_master.adr, local_r_addr),
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NextState("WaitForData")
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)
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)
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req_r_fsm.act("WaitForData",
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If(self.wishbone_r_master.ack &
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self.tosbus_fifo.writable,
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NextValue(self.wishbone_r_master.cyc, 0),
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NextValue(self.wishbone_r_master.stb, 0),
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tosbus_fifo.we.eq(1),
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tosbus_fifo.din.eq(Cat(dma_r_addr, self.wishbone_r_master.dat_r)),
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NextValue(self.last_blk.status, local_r_addr),
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NextValue(self.last_dma.status, dma_r_addr),
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NextValue(self.blk_rem.status, self.blk_rem.status - 1),
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If(self.blk_rem.status[0:max_block_bits] <= 1,
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self.blk_cnt.we.eq(1), ## auto-reset
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self.blk_cnt.dat_w.eq(0),
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NextState("Idle"),
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).Else(
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NextValue(local_r_addr, local_r_addr + 1),
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NextValue(dma_r_addr, dma_r_addr + data_width),
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NextState("ReqFromMemory"),
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)
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)
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)
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req_r_fsm.act("QueueReqToMemory",
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If(self.fromsbus_req_fifo.writable,
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self.fromsbus_req_fifo.we.eq(1),
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self.fromsbus_req_fifo.din.eq(Cat(local_r_addr, dma_r_addr)),
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NextValue(self.last_blk.status, local_r_addr),
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NextValue(self.last_dma.status, dma_r_addr),
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NextValue(self.blk_rem.status, self.blk_rem.status - 1),
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If(self.blk_rem.status[0:max_block_bits] <= 1,
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self.blk_cnt.we.eq(1), ## auto-reset
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self.blk_cnt.dat_w.eq(0),
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NextState("Idle"),
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).Else(
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NextValue(local_r_addr, local_r_addr + 1),
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NextValue(dma_r_addr, dma_r_addr + data_width),
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NextValue(self.blk_rem.status, self.blk_rem.status - 1),
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NextState("QueueReqToMemory"), #redundant
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)
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)
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)
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req_w_fsm.act("Reset",
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NextState("Idle")
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)
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req_w_fsm.act("Idle",
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If(self.fromsbus_fifo.readable &
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~self.wishbone_w_master.ack,
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self.fromsbus_fifo.re.eq(1),
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NextValue(self.wishbone_w_master.cyc, 1),
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NextValue(self.wishbone_w_master.stb, 1),
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NextValue(self.wishbone_w_master.sel, 2**len(self.wishbone_w_master.sel)-1),
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NextValue(self.wishbone_w_master.we, 1),
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NextValue(self.wishbone_w_master.adr, self.fromsbus_fifo.dout[0:blk_addr_width]),
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NextValue(self.wishbone_w_master.dat_w, self.fromsbus_fifo.dout[blk_addr_width:(blk_addr_width + data_width_bits)]),
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NextValue(self.wr_tosdram.status, self.fromsbus_fifo.dout[0:blk_addr_width]),
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NextState("WaitForAck")
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)
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)
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req_w_fsm.act("WaitForAck",
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If(self.wishbone_w_master.ack,
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NextValue(self.wishbone_w_master.cyc, 0),
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NextValue(self.wishbone_w_master.stb, 0),
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NextState("Idle"),
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)
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)
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