CG3 is usable as console and with X11, despite the ugly colors
This commit is contained in:
Romain Dolbeau
parent
df7f1e819f
commit
11cfd3ba40
@ -198,6 +198,22 @@ dma_init(struct sbusfpga_sdram_softc *sc);
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int
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dma_memtest(struct sbusfpga_sdram_softc *sc);
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int
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init_last_blocks(struct sbusfpga_sdram_softc *sc);
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int
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init_last_blocks(struct sbusfpga_sdram_softc *sc) {
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u_int32_t data[512];
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u_int32_t i;
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int res = 0;
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for (i = 0 ; i < 512 ; i++) {
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data[i] = 0x00FF00FF;
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}
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for (i = 254*1024*2 ; i < 256*1024*2 && !res; i+=4) {
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res = sbusfpga_sdram_write_block(sc, i, 4, data);
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}
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return res;
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}
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/*
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* Attach all the sub-devices we can find
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*/
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@ -366,6 +382,11 @@ sbusfpga_sdram_attach(device_t parent, device_t self, void *aux)
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lp->d_checksum = dkcksum(lp);
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}
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/*
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// initialize some blocks were the FB lives to test the output
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init_last_blocks(sc);
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*/
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/*
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aprint_normal_dev(self, "sc->dk.sc_dkdev.dk_blkshift = %d\n", sc->dk.sc_dkdev.dk_blkshift);
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aprint_normal_dev(self, "sc->dk.sc_dkdev.dk_byteshift = %d\n", sc->dk.sc_dkdev.dk_byteshift);
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131
sbus-to-ztex-gateware-migen/cg3.fth
Normal file
131
sbus-to-ztex-gateware-migen/cg3.fth
Normal file
@ -0,0 +1,131 @@
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\ simplified version of the OpenBIOS cgthree code
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: openbios-video-width
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h# SBUSFPGA_CG3_WIDTH
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;
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: openbios-video-height
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h# SBUSFPGA_CG3_HEIGHT
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;
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: depth-bits
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h# 8
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;
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: line-bytes
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h# SBUSFPGA_CG3_WIDTH
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;
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h# 400000 constant cg3-off-dac
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h# 20 constant /cg3-off-dac
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h# 800000 constant cg3-off-fb
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h# SBUSFPGA_CG3_BUFSIZE constant /cg3-off-fb
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: >cg3-reg-spec ( offset size -- encoded-reg )
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>r 0 my-address d+ my-space encode-phys r> encode-int encode+
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;
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: cg3-reg
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\ A real cg3 rom appears to just map the entire region with a
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\ single entry
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h# 0 h# 1000000 >cg3-reg-spec
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" reg" property
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;
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: do-map-in ( offset size -- virt )
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>r my-space r> " map-in" $call-parent
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;
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: do-map-out ( virt size )
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" map-out" $call-parent
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;
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\
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\ DAC
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\
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-1 value cg3-dac
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-1 value fb-addr
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: dac! ( data reg# -- )
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cg3-dac + c!
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;
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external
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: color! ( r g b c# -- )
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0 dac! ( r g b )
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swap rot ( b g r )
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4 dac! ( b g )
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4 dac! ( b )
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4 dac! ( )
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;
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headerless
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\
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\ Mapping
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\
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: dac-map
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cg3-off-dac /cg3-off-dac do-map-in to cg3-dac
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;
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: fb-map
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cg3-off-fb /cg3-off-fb do-map-in to fb-addr
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;
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: map-regs
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dac-map fb-map
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;
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\
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\ Installation
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\
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" cgthree" device-name
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" display" device-type
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" SUNW,501-1415" model
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: qemu-cg3-driver-install ( -- )
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cg3-dac -1 = if
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map-regs
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\ Initial pallette taken from Sun's "Writing FCode Programs"
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h# ff h# ff h# ff h# 0 color! \ Background white
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h# 0 h# 0 h# 0 h# ff color! \ Foreground black
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h# 64 h# 41 h# b4 h# 1 color! \ SUN-blue logo
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fb-addr to frame-buffer-adr
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default-font set-font
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frame-buffer-adr encode-int " address" property
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openbios-video-width openbios-video-height over char-width / over char-height /
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fb8-install
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then
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;
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: qemu-cg3-driver-init
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cg3-reg
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openbios-video-height encode-int " height" property
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openbios-video-width encode-int " width" property
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line-bytes encode-int " linebytes" property
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h# 39 encode-int 0 encode-int encode+ " intr" property
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\ Monitor sense. Some searching suggests that this is
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\ 5 for 1024x768 and 7 for 1152x900
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h# 5 encode-int " monitor-sense" property
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" RDOL" encode-string " manufacturer" property
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" ISO8859-1" encode-string " character-set" property
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h# c encode-int " cursorshift" property
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['] qemu-cg3-driver-install is-install
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;
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qemu-cg3-driver-init
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@ -10,6 +10,8 @@ from litex.build.io import SDROutput, DDROutput
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from litex.soc.cores.video import *
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from math import ceil;
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# " 108000000,71808,76,32,128,192,1152,2,8,33,900,COLOR,0OFFSET"
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cg3_timings = {
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"1152x900@76Hz": {
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@ -25,10 +27,15 @@ cg3_timings = {
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},
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}
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def cg3_rounded_size(hres, vres):
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return int(1048576 * ceil(((hres * vres) + 262144) / 1048576))
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class VideoFrameBuffer256c(Module, AutoCSR):
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"""Video FrameBuffer256c"""
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def __init__(self, dram_port, upd_clut_fifo, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False):
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clut = Array(Array(Signal(8) for i in range(0, 256)) for j in range(0, 3))
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def __init__(self, dram_port, upd_clut_fifo = None, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False):
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clut = Array(Array(Signal(8, reset = (255-i)) for i in range(0, 256)) for j in range(0, 3))
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print(f"FRAMEBUFFER: dram_port.data_width = {dram_port.data_width}, {hres}x{vres}, 0x{base:x}, in {clock_domain}, clock_faster_than_sys={clock_faster_than_sys}")
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vga_sync = getattr(self.sync, clock_domain)
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vga_sync += [
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@ -62,7 +69,7 @@ class VideoFrameBuffer256c(Module, AutoCSR):
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self.submodules.cdc = stream.ClockDomainCrossing([("data", dram_port.data_width)], cd_from="sys", cd_to=clock_domain)
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self.comb += self.dma.source.connect(self.cdc.sink)
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# ... and then Data-Width Conversion.
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self.submodules.conv = stream.Converter(dram_port.data_width, 8)
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self.submodules.conv = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 8))
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self.comb += self.cdc.source.connect(self.conv.sink)
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video_pipe_source = self.conv.source
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# Elsif DRAM Data Widt < 8-bit or Video clock is slower than sys_clk:
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@ -75,30 +82,56 @@ class VideoFrameBuffer256c(Module, AutoCSR):
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self.comb += self.conv.source.connect(self.cdc.sink)
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video_pipe_source = self.cdc.source
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#counter = Signal(11)
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#vga_sync += If(vtg_sink.de,
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# If(counter == (hres-1),
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# counter.eq(0)
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# ).Else(
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# counter.eq(counter + 1))).Else(
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# counter.eq(0))
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# Video Generation.
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self.comb += [
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#vtg_sink.ready.eq(1),
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#vtg_sink.connect(source, keep={"de", "hsync", "vsync"}),
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#If(vtg_sink.de,
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# source.r.eq(Cat(Signal(6, reset = 0), counter[2:4])),
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# source.g.eq(Cat(Signal(6, reset = 0), counter[4:6])),
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# source.b.eq(Cat(Signal(6, reset = 0), counter[6:8])),
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#).Else(source.r.eq(0),
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# source.g.eq(0),
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# source.b.eq(0),)
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vtg_sink.ready.eq(1),
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If(vtg_sink.valid & vtg_sink.de,
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video_pipe_source.connect(source, keep={"valid", "ready"}),
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vtg_sink.ready.eq(source.valid & source.ready),
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),
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vtg_sink.connect(source, keep={"de", "hsync", "vsync"}),
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source.r.eq(clut[0][video_pipe_source.data]),
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source.g.eq(clut[1][video_pipe_source.data]),
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source.b.eq(clut[2][video_pipe_source.data]),
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If(vtg_sink.de,
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source.r.eq(clut[0][video_pipe_source.data]),
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source.g.eq(clut[1][video_pipe_source.data]),
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source.b.eq(clut[2][video_pipe_source.data])
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#source.r.eq(video_pipe_source.data),
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#source.g.eq(video_pipe_source.data),
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#source.b.eq(video_pipe_source.data),
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).Else(
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source.r.eq(0),
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source.g.eq(0),
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source.b.eq(0)
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)
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]
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# Underflow.
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self.comb += self.underflow.eq(~source.valid)
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class cg3(Module):
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class cg3(Module, AutoCSR):
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def __init__(self, soc, phy=None, timings = None, clock_domain="sys"):
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# 2 bits for color (0/r, 1/g, 2/b), 8 for @ and 8 for value
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self.submodules.upd_cmap_fifo = upd_cmap_fifo = ClockDomainsRenamer({"read": "vga", "write": "sys"})(AsyncFIFOBuffered(width=2+8+8, depth=8))
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name = "cg3_pixels"
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name = "video_framebuffer"
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# near duplicate of plaform.add_video_framebuffer
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# Video Timing Generator.
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vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
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@ -111,8 +144,9 @@ class cg3(Module):
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print(f"CG3: visible memory at {base:x}")
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hres = int(timings.split("@")[0].split("x")[0])
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vres = int(timings.split("@")[0].split("x")[1])
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print(f"CG3: using {hres} x {vres}")
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vfb = VideoFrameBuffer256c(soc.sdram.crossbar.get_port(),
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freq = vtg.video_timings["pix_clk"]
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print(f"CG3: using {hres} x {vres}, {freq/1e6} MHz pixclk")
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vfb = VideoFrameBuffer256c(dram_port = soc.sdram.crossbar.get_port(),
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upd_clut_fifo = upd_cmap_fifo,
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hres = hres,
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vres = vres,
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24
sbus-to-ztex-gateware-migen/cg3_init.fth
Normal file
24
sbus-to-ztex-gateware-migen/cg3_init.fth
Normal file
@ -0,0 +1,24 @@
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: cg3_vid_fb_vtg_enable_rd ( -- csr_value)
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cg3-virt h# 0000 + l@
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;
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: cg3_vid_fb_dma_enable_rd ( -- csr_value)
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cg3-virt h# 002c + l@
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;
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: cg3_vid_fb_vtg_enable_wr ( value -- )
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cg3-virt h# 0000 + l!
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;
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: cg3_vid_fb_dma_enable_wr ( value -- )
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cg3-virt h# 002c + l!
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;
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: cg3_init!
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map-in-cg3extraregs
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0 cg3_vid_fb_vtg_enable_wr
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0 cg3_vid_fb_dma_enable_wr
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1 cg3_vid_fb_vtg_enable_wr
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1 cg3_vid_fb_dma_enable_wr
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map-out-cg3extraregs
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;
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@ -127,9 +127,9 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
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def get_csr_forth_header(csr_regions, mem_regions, device_irq_map, constants, csr_base=None):
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r = "\\ auto-generated base regions for CSRs in the PROM\n"
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for name, region in csr_regions.items():
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_csraddr_{}".format(name) + "\n"
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_csraddr_{}".format(name.replace("video_framebuffer", "vid_fb")) + "\n"
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for name, region in mem_regions.items():
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_regionaddr_{}".format(name) + "\n"
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_regionaddr_{}".format(name.replace("video_framebuffer", "vid_fb")) + "\n"
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for device, irq in device_irq_map.items():
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if ((irq < 7) and (irq > 0)):
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r += "h# " + hex(irq).replace("0x", "") + " constant " + "sbusfpga_irq_{}".format(device) + "\n"
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@ -28,11 +28,18 @@ ADDR_PFX_LENGTH = 12 #(1 + ADDR_PFX_HIGH - ADDR_PFX_LOW)
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ROM_ADDR_PFX = Signal(12, reset = 0x000) # read only
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WISHBONE_CSR_ADDR_PFX = Signal(12, reset = 0x004)
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USBOHCI_ADDR_PFX = Signal(12, reset = 0x008)
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SRAM_ADDR_PFX = Signal(12, reset = 0x009) # unmapped
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SRAM_ADDR_PFX = Signal(12, reset = 0x009) # unmapped ; LE
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ENGINE_ADDR_PFXA = Signal(12, reset = 0x00a)
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ENGINE_ADDR_PFXB = Signal(12, reset = 0x00b)
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CG3_REGISTERS_ADDR_PFX = Signal(12, reset = 0x040)
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CG3_PIXELS_ADDR_PFX = Signal(12, reset = 0x080)
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ADDR_BIGPFX_HIGH = ADDR_PHYS_HIGH
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ADDR_BIGPFX_LOW = 20 ## 1 MiB per bigprefix
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ADDR_BIGPFX_LENGTH = 8 #(1 + ADDR_BIGPFX_HIGH - ADDR_BIGPFX_LOW)
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CG3_PIXELS_ADDR_BIGPFX = Signal(8, reset = 0x08) # cg3_pixels, remapped, first MiB, LE
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CG3_PIXELS_ADDR_BIGVAL = 0x08
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CG3_PIXELS_ADDR2_BIGPFX = Signal(8, reset = 0x09) # cg3_pixels, remapped, second MiB, LE
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CG3_PIXELS_ADDR2_BIGVAL = 0x09
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wishbone_default_timeout = 120 ##
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sbus_default_timeout = 50 ## must be below 255
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@ -207,9 +214,10 @@ class SBusFPGABus(Module):
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fifo_blk_addr = Signal(blk_addr_width)
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fifo_buffer = Signal(data_width_bits)
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pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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SBUS_DATA_OE_LED_o = Signal()
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self.comb += pad_SBUS_DATA_OE_LED.eq(SBUS_DATA_OE_LED_o)
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#pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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#SBUS_DATA_OE_LED_o = Signal()
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#self.comb += pad_SBUS_DATA_OE_LED.eq(SBUS_DATA_OE_LED_o)
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##pad_SBUS_DATA_OE_LED_2 = platform.request("SBUS_DATA_OE_LED_2")
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##SBUS_DATA_OE_LED_2_o = Signal()
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##self.comb += pad_SBUS_DATA_OE_LED_2.eq(SBUS_DATA_OE_LED_2_o)
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@ -341,7 +349,7 @@ class SBusFPGABus(Module):
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#self.sync += platform.request("user_led", 5).eq(self.wishbone_slave.cyc)
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#self.sync += platform.request("user_led", 6).eq(~SBUS_3V3_BRs_o)
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#self.sync += platform.request("user_led", 7).eq(~SBUS_3V3_BGs_i)
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self.sync += SBUS_DATA_OE_LED_o.eq(~SBUS_3V3_BGs_i),
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#self.sync += SBUS_DATA_OE_LED_o.eq(~SBUS_3V3_BGs_i),
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#cycle_counter = Signal(8, reset = 0)
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#self.sync += cycle_counter.eq(cycle_counter + 1)
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@ -461,22 +469,30 @@ class SBusFPGABus(Module):
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXA) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXB) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_REGISTERS_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_PIXELS_ADDR_PFX)),
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
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NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
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NextValue(SBUS_3V3_ERRs_o, 1),
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NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
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NextValue(sbus_wishbone_le,
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
If(self.wishbone_master.cyc == 0,
|
||||
NextValue(self.wishbone_master.cyc, 1),
|
||||
NextValue(self.wishbone_master.stb, 1),
|
||||
NextValue(self.wishbone_master.sel, 2**len(self.wishbone_master.sel)-1),
|
||||
NextValue(self.wishbone_master.we, 0),
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
@ -486,11 +502,14 @@ class SBusFPGABus(Module):
|
||||
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
NextState("Slave_Ack_Read_Reg_Burst_Wait_For_Data")
|
||||
).Else(
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
@ -514,22 +533,30 @@ class SBusFPGABus(Module):
|
||||
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_REGISTERS_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_PIXELS_ADDR_PFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
If(self.wishbone_master.cyc == 0,
|
||||
NextValue(self.wishbone_master.cyc, 1),
|
||||
NextValue(self.wishbone_master.stb, 1),
|
||||
NextValue(self.wishbone_master.sel, 2**len(self.wishbone_master.sel)-1),
|
||||
NextValue(self.wishbone_master.we, 0),
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
@ -539,11 +566,14 @@ class SBusFPGABus(Module):
|
||||
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
NextState("Slave_Ack_Read_Reg_Byte_Wait_For_Data")
|
||||
).Else(
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
@ -573,22 +603,30 @@ class SBusFPGABus(Module):
|
||||
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_REGISTERS_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_PIXELS_ADDR_PFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
If(self.wishbone_master.cyc == 0,
|
||||
NextValue(self.wishbone_master.cyc, 1),
|
||||
NextValue(self.wishbone_master.stb, 1),
|
||||
NextValue(self.wishbone_master.sel, 2**len(self.wishbone_master.sel)-1),
|
||||
NextValue(self.wishbone_master.we, 0),
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
@ -598,11 +636,14 @@ class SBusFPGABus(Module):
|
||||
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
NextState("Slave_Ack_Read_Reg_HWord_Wait_For_Data")
|
||||
).Else(
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
@ -643,14 +684,21 @@ class SBusFPGABus(Module):
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXA) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXB) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_REGISTERS_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_PIXELS_ADDR_PFX)),
|
||||
NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
@ -682,14 +730,21 @@ class SBusFPGABus(Module):
|
||||
NextValue(sbus_oe_master_in, 1),
|
||||
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_REGISTERS_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_PIXELS_ADDR_PFX)),
|
||||
NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
@ -727,14 +782,21 @@ class SBusFPGABus(Module):
|
||||
NextState("Slave_Error")
|
||||
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_REGISTERS_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_PIXELS_ADDR_PFX)),
|
||||
NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
Case(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH], {
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM
|
||||
0x080: [
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
|
||||
@ -6,17 +6,20 @@ from sysconfig import get_platform
|
||||
|
||||
from migen import *
|
||||
|
||||
from math import ceil
|
||||
import cg3_fb
|
||||
|
||||
def get_header_map_stuff(name, size, type="csr"):
|
||||
r = f"my-address sbusfpga_{type}addr_{name} + my-space h# {size:x} reg\n"
|
||||
|
||||
def get_header_map_stuff(gname, name, size, type="csr", reg=True):
|
||||
r = ""
|
||||
if (reg):
|
||||
r += f"my-address sbusfpga_{type}addr_{name} + my-space h# {size:x} reg\n"
|
||||
r += "h# 7f xdrint \" slave-burst-sizes\" attribute\n" # fixme: burst-sizes
|
||||
r += "h# 7f xdrint \" burst-sizes\" attribute\n" # fixme: burst-sizes
|
||||
r += "headers\n"
|
||||
r += f"-1 instance value {name}-virt\nmy-address constant my-sbus-address\nmy-space constant my-sbus-space\n"
|
||||
r += ": map-in ( adr space size -- virt ) \" map-in\" $call-parent ;\n: map-out ( virt size -- ) \" map-out\" $call-parent ;\n";
|
||||
r += f": map-in-{name} ( -- ) my-sbus-address sbusfpga_{type}addr_{name} + my-sbus-space h# {size:x} map-in is {name}-virt ;\n"
|
||||
r += f": map-out-{name} ( -- ) {name}-virt h# {size:x} map-out ;\n"
|
||||
r += f": map-in-{gname} ( -- ) my-sbus-address sbusfpga_{type}addr_{name} + my-sbus-space h# {size:x} map-in is {name}-virt ;\n"
|
||||
r += f": map-out-{gname} ( -- ) {name}-virt h# {size:x} map-out ;\n"
|
||||
return r
|
||||
|
||||
def get_header_map2_stuff(gname, name1, name2, size1, size2, type1="csr", type2="csr"):
|
||||
@ -78,16 +81,16 @@ def get_prom(soc,
|
||||
|
||||
if (version == "V1.0"):
|
||||
r += "\" RDOL,led\" device-name\n"
|
||||
r += get_header_map_stuff("leds", 4)
|
||||
r += get_header_map_stuff("leds", "leds", 4)
|
||||
r += ": setled! ( pattern -- )\nmap-in-leds\nleds-virt l! ( pattern virt -- )\nmap-out-leds\n;\n"
|
||||
r += "finish-device\nnew-device\n"
|
||||
|
||||
r += "\" RDOL,sbusstat\" device-name\n"
|
||||
r += get_header_map_stuff("sbus_bus_stat", 256)
|
||||
r += get_header_map_stuff("sbus_bus_stat", "sbus_bus_stat", 256)
|
||||
r += "finish-device\nnew-device\n"
|
||||
|
||||
r += "\" RDOL,neorv32trng\" device-name\n"
|
||||
r += get_header_map_stuff("trng", 8)
|
||||
r += get_header_map_stuff("trng", "trng", 8)
|
||||
r += ": disabletrng! ( -- )\n"
|
||||
r += " map-in-trng\n"
|
||||
r += " 1 trng-virt l! ( pattern virt -- )\n"
|
||||
@ -100,7 +103,7 @@ def get_prom(soc,
|
||||
if (usb):
|
||||
r += "\" generic-ohci\" device-name\n"
|
||||
r += "sbusfpga_irq_usb_host xdrint \" interrupts\" attribute\n"
|
||||
r += get_header_map_stuff("usb_host_ctrl", 4096, type="region")
|
||||
r += get_header_map_stuff("usb_host_ctrl", "usb_host_ctrl", 4096, type="region")
|
||||
r += ": my-reset! ( -- )\n"
|
||||
r += " map-in-usb_host_ctrl\n"
|
||||
r += " 00000001 usb_host_ctrl-virt h# 4 + l! ( -- ) ( reset the HC )\n"
|
||||
@ -134,7 +137,7 @@ def get_prom(soc,
|
||||
|
||||
if (i2c):
|
||||
r += "\" RDOL,i2c\" device-name\n"
|
||||
r += get_header_map_stuff("i2c", 64)
|
||||
r += get_header_map_stuff("i2c", "i2c", 64)
|
||||
if (cg3):
|
||||
r += "finish-device\nnew-device\n"
|
||||
|
||||
@ -145,11 +148,17 @@ def get_prom(soc,
|
||||
vres_h=(f"{vres:x}").replace("0x", "")
|
||||
cg3_file = open("cg3.fth")
|
||||
cg3_lines = cg3_file.readlines()
|
||||
buf_size=int(ceil(hres*vres)/1048576)
|
||||
buf_size=cg3_fb.cg3_rounded_size(hres, vres)
|
||||
for line in cg3_lines:
|
||||
r += line.replace("SBUSFPGA_CG3_WIDTH", hres_h).replace("SBUSFPGA_CG3_HEIGHT", vres_h).replace("SBUSFPGA_CG3_BUFSIZE", f"{buf_size*1048576:x}")
|
||||
r += get_header_map2_stuff("cg3extraregs", "video_framebuffer", "video_framebuffer_vtg", 4096, 4096)
|
||||
|
||||
r += line.replace("SBUSFPGA_CG3_WIDTH", hres_h).replace("SBUSFPGA_CG3_HEIGHT", vres_h).replace("SBUSFPGA_CG3_BUFSIZE", f"{buf_size:x}")
|
||||
#r += "\" LITEX,fb\" device-name\n"
|
||||
#r += get_header_map2_stuff("cg3extraregs", "vid_fb", "vid_fb_vtg", 4096, 4096)
|
||||
#r += "fload fb_init.fth\nfb_init!\n"
|
||||
|
||||
r += "\n"
|
||||
r += get_header_map_stuff("cg3extraregs", "cg3", 4096, reg=False)
|
||||
r += "fload cg3_init.fth\ncg3_init!\n"
|
||||
|
||||
r += "end0\n"
|
||||
|
||||
return r
|
||||
|
||||
@ -113,8 +113,8 @@ class _CRG(Module):
|
||||
platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
|
||||
num_clk = num_clk + 1
|
||||
self.comb += pll.reset.eq(~rst_sbus) # | ~por_done
|
||||
platform.add_false_path_constraints(self.cd_native.clk, self.cd_sbus.clk)
|
||||
platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_native.clk)
|
||||
platform.add_false_path_constraints(self.cd_native.clk, self.cd_sbus.clk) # FIXME?
|
||||
platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_native.clk) # FIXME?
|
||||
#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_sbus.clk)
|
||||
#platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_sys.clk)
|
||||
##platform.add_false_path_constraints(self.cd_native.clk, self.cd_sys.clk)
|
||||
@ -167,7 +167,7 @@ class _CRG(Module):
|
||||
platform.add_platform_command("create_generated_clock -name usbclk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
|
||||
num_clk = num_clk + 1
|
||||
self.comb += usb_pll.reset.eq(~rst_sbus) # | ~por_done
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, self.cd_usb.clk)
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, self.cd_usb.clk) # FIXME?
|
||||
num_adv = num_adv + 1
|
||||
num_clk = 0
|
||||
|
||||
@ -190,7 +190,8 @@ class _CRG(Module):
|
||||
platform.add_platform_command("create_generated_clock -name vga_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
|
||||
num_clk = num_clk + 1
|
||||
self.comb += video_pll.reset.eq(~rst_sbus)
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, self.cd_vga.clk)
|
||||
#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_vga.clk)
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, video_pll.clkin)
|
||||
num_adv = num_adv + 1
|
||||
num_clk = 0
|
||||
|
||||
@ -226,7 +227,7 @@ class SBusFPGA(SoCCore):
|
||||
if (cg3):
|
||||
hres = int(cg3_res.split("@")[0].split("x")[0])
|
||||
vres = int(cg3_res.split("@")[0].split("x")[1])
|
||||
cg3_fb_size = int(1048576 * ceil((hres * vres) / 1048576))
|
||||
cg3_fb_size = cg3_fb.cg3_rounded_size(hres, vres)
|
||||
print(f"Reserving {cg3_fb_size} bytes ({cg3_fb_size//1048576} MiB) for the CG3")
|
||||
else:
|
||||
hres = 0
|
||||
@ -256,13 +257,13 @@ class SBusFPGA(SoCCore):
|
||||
"usb_host": 0x00080000, # OHCI registers are here, not in CSR
|
||||
#"usb_shared_mem": 0x00090000, # unused ATM
|
||||
"curve25519engine": 0x000a0000, # includes microcode (4 KiB@0) and registers (16 KiB @ 64 KiB)
|
||||
#"cgtroisengine": 0x000c0000, # includes microcode (4 KiB@0) and registers (?? KiB @ 64 KiB)
|
||||
"cg3_registers": 0x00400000, # required for compatibility
|
||||
"fb_accel_rom": 0x00410000,
|
||||
"fb_accel_ram": 0x00420000,
|
||||
"cg6_fbc": 0x00700000, # required for compatibility
|
||||
"cg3_pixels": 0x00800000, # required for compatibility
|
||||
"main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible)
|
||||
#"cg6_fbc": 0x00700000, # required for compatibility
|
||||
"cg3_pixels": 0x00800000, # required for compatibility, 1-2 MiB for now (2nd MiB is 0x00900000)
|
||||
"main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible),
|
||||
"video_framebuffer":0x80000000 + 0x10000000 - cg3_fb_size, # FIXME
|
||||
"usb_fake_dma": 0xfc000000, # required to match DVMA virtual addresses
|
||||
}
|
||||
self.mem_map.update(wb_mem_map)
|
||||
@ -294,7 +295,7 @@ class SBusFPGA(SoCCore):
|
||||
|
||||
if (usb):
|
||||
self.add_usb_host_custom(pads=platform.request("usb"), usb_clk_freq=48e6)
|
||||
pad_usb_interrupt = platform.get_irq(irq_req=1, device="usb_host", next_down=True, next_up=True)
|
||||
pad_usb_interrupt = platform.get_irq(irq_req=4, device="usb_host", next_down=True, next_up=False)
|
||||
if (pad_usb_interrupt is None):
|
||||
print(" ***** ERROR ***** USB requires an interrupt")
|
||||
sig_usb_interrupt = Signal(reset=1)
|
||||
@ -346,7 +347,7 @@ class SBusFPGA(SoCCore):
|
||||
# don't enable anything on the SBus side for 20 seconds after power up
|
||||
# this avoids FPGA initialization messing with the cold boot process
|
||||
# requires us to reset the SPARCstation afterward so the FPGA board
|
||||
# is properly identified
|
||||
# is properly identified - or to 'probe-slot'
|
||||
# This is in the 'native' ClockDomain that is never reset
|
||||
hold_reset_ctr = Signal(30, reset=960000000)
|
||||
self.sync.native += If(hold_reset_ctr>0, hold_reset_ctr.eq(hold_reset_ctr - 1))
|
||||
@ -438,7 +439,15 @@ class SBusFPGA(SoCCore):
|
||||
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
|
||||
self.submodules.cg3 = cg3_fb.cg3(soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga") # clock_domain for the VGA side, cg3 is running in cd_sys
|
||||
self.bus.add_slave("cg3_registers", self.cg3.bus, SoCRegion(origin=self.mem_map.get("cg3_registers", None), size=0x1000, cached=False))
|
||||
#self.submodules.cgtrois = ClockDomainsRenamer({"eng_clk":"clk50", "rf_clk":"clk200", "mul_clk":"clk100_gated"})(cgtrois.CGTrois(platform=platform,prefix=self.mem_map.get("curve25519engine", None), hres=hres, vres=vres, base=(self.wb_mem_map["main_ram"] + avail_sdram)))
|
||||
##self.submodules.cgtrois = ClockDomainsRenamer({"eng_clk":"clk50", "rf_clk":"clk200", "mul_clk":"clk100_gated"})(cgtrois.CGTrois(platform=platform,prefix=self.mem_map.get("curve25519engine", None), hres=hres, vres=vres, base=(self.wb_mem_map["main_ram"] + avail_sdram)))
|
||||
##self.add_video_framebuffer(phy=self.videophy, timings=cg3_res, clock_domain="vga")
|
||||
pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
|
||||
#self.comb += pad_SBUS_DATA_OE_LED.eq(~self.cg3.video_framebuffer.dma.source.valid)
|
||||
#self.comb += pad_SBUS_DATA_OE_LED.eq(~self.cg3.video_framebuffer.conv.source.valid)
|
||||
#self.comb += pad_SBUS_DATA_OE_LED.eq(~self.cg3.video_framebuffer.cdc.source.valid)
|
||||
self.comb += pad_SBUS_DATA_OE_LED.eq(~self.cg3.video_framebuffer_vtg.source.valid)
|
||||
#self.comb += pad_SBUS_DATA_OE_LED.eq(self.cg3.video_framebuffer.underflow)
|
||||
##self.comb += pad_SBUS_DATA_OE_LED.eq(self.video_framebuffer.underflow)
|
||||
|
||||
print("IRQ to Device map:\n")
|
||||
print(platform.irq_device_map)
|
||||
|
||||
@ -208,8 +208,8 @@ _i2c_v1_2 = [
|
||||
def vga_rgb222_pmod_io(pmod):
|
||||
return [
|
||||
("vga", 0,
|
||||
Subsignal("hsync_n", Pins(f"{pmod}:3")),
|
||||
Subsignal("vsync_n", Pins(f"{pmod}:7")),
|
||||
Subsignal("hsync", Pins(f"{pmod}:3")),
|
||||
Subsignal("vsync", Pins(f"{pmod}:7")),
|
||||
Subsignal("b", Pins(f"{pmod}:0 {pmod}:4")),
|
||||
Subsignal("g", Pins(f"{pmod}:1 {pmod}:5")),
|
||||
Subsignal("r", Pins(f"{pmod}:2 {pmod}:6")),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user