Update more stuff to V1.2
This commit is contained in:
Romain Dolbeau
parent
625b4185a8
commit
12f239fbce
426
sbus-to-ztex-gateware/sbus-to-ztex-V1_2.xdc
Normal file
426
sbus-to-ztex-gateware/sbus-to-ztex-V1_2.xdc
Normal file
@ -0,0 +1,426 @@
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# !!! Constraint files are application specific !!!
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# !!! This is a template only !!!
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# on-board signals
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# CLKOUT/FXCLK
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create_clock -name fxclk_in -period 20.833 [get_ports fxclk_in]
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set_property PACKAGE_PIN P15 [get_ports fxclk_in]
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set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
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# IFCLK
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#create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in]
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#set_property PACKAGE_PIN P17 [get_ports ifclk_in]
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#set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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#set_property PACKAGE_PIN M16 [get_ports {PB[0]}] ;# PB0/FD0
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[0]}]
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#set_property PACKAGE_PIN L16 [get_ports {PB[1]}] ;# PB1/FD1
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[1]}]
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#set_property PACKAGE_PIN L14 [get_ports {PB[2]}] ;# PB2/FD2
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[2]}]
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#set_property PACKAGE_PIN M14 [get_ports {PB[3]}] ;# PB3/FD3
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[3]}]
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#set_property PACKAGE_PIN L18 [get_ports {PB[4]}] ;# PB4/FD4
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[4]}]
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#set_property PACKAGE_PIN M18 [get_ports {PB[5]}] ;# PB5/FD5
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[5]}]
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#set_property PACKAGE_PIN R12 [get_ports {PB[6]}] ;# PB6/FD6
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[6]}]
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#set_property PACKAGE_PIN R13 [get_ports {PB[7]}] ;# PB7/FD7
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#set_property IOSTANDARD LVCMOS33 [get_ports {PB[7]}]
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#set_property PACKAGE_PIN T9 [get_ports {PD[0]}] ;# PD0/FD8
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[0]}]
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#set_property PACKAGE_PIN V10 [get_ports {PD[1]}] ;# PD1/FD9
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[1]}]
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#set_property PACKAGE_PIN U11 [get_ports {PD[2]}] ;# PD2/FD10
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[2]}]
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#set_property PACKAGE_PIN V11 [get_ports {PD[3]}] ;# PD3/FD11
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[3]}]
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#set_property PACKAGE_PIN V12 [get_ports {PD[4]}] ;# PD4/FD12
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[4]}]
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#set_property PACKAGE_PIN U13 [get_ports {PD[5]}] ;# PD5/FD13
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[5]}]
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#set_property PACKAGE_PIN U14 [get_ports {PD[6]}] ;# PD6/FD14
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[6]}]
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#set_property PACKAGE_PIN V14 [get_ports {PD[7]}] ;# PD7/FD15
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#set_property IOSTANDARD LVCMOS33 [get_ports {PD[7]}]
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#set_property PACKAGE_PIN R15 [get_ports {PA[0]}] ;# PA0/INT0#
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}]
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#set_property PACKAGE_PIN T15 [get_ports {PA[1]}] ;# PA1/INT1#
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}]
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#set_property PACKAGE_PIN T14 [get_ports {PA[2]}] ;# PA2/SLOE
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}]
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#set_property PACKAGE_PIN T13 [get_ports {PA[3]}] ;# PA3/WU2
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}]
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#set_property PACKAGE_PIN R11 [get_ports {PA[4]}] ;# PA4/FIFOADR0
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}]
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#set_property PACKAGE_PIN T11 [get_ports {PA[5]}] ;# PA5/FIFOADR1
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}]
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#set_property PACKAGE_PIN R10 [get_ports {PA[6]}] ;# PA6/PKTEND
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}]
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#set_property PACKAGE_PIN T10 [get_ports {PA[7]}] ;# PA7/FLAGD/SLCS#
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#set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}]
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#set_property PACKAGE_PIN R17 [get_ports {PC[0]}] ;# PC0/GPIFADR0
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#set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
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#set_property PACKAGE_PIN R18 [get_ports {PC[1]}] ;# PC1/GPIFADR1
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#set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
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#set_property PACKAGE_PIN P18 [get_ports {PC[2]}] ;# PC2/GPIFADR2
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#set_property IOSTANDARD LVCMOS33 [get_ports {PC[2]}]
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#set_property PACKAGE_PIN P14 [get_ports {PC[3]}] ;# PC3/GPIFADR3
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#set_property IOSTANDARD LVCMOS33 [get_ports {PC[3]}]
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#set_property PACKAGE_PIN K18 [get_ports {FLASH_DO}] ;# PC4/GPIFADR4
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#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DO}]
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#set_property PACKAGE_PIN L13 [get_ports {FLASH_CS}] ;# PC5/GPIFADR5
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#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CS}]
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#set_property PACKAGE_PIN E9 [get_ports {FLASH_CLK}] ;# PC6/GPIFADR6
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#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CLK}]
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#set_property PACKAGE_PIN K17 [get_ports {FLASH_DI}] ;# PC7/GPIFADR7
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#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DI}]
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#set_property PACKAGE_PIN P10 [get_ports {PE[0]}] ;# PE0/T0OUT
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#set_property IOSTANDARD LVCMOS33 [get_ports {PE[0]}]
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#set_property PACKAGE_PIN P7 [get_ports {PE[1]}] ;# PE1/T1OUT
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#set_property IOSTANDARD LVCMOS33 [get_ports {PE[1]}]
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#set_property PACKAGE_PIN V15 [get_ports {PE[2]}] ;# PE2/T2OUT
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#set_property IOSTANDARD LVCMOS33 [get_ports {PE[2]}]
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#set_property PACKAGE_PIN R16 [get_ports {PE[5]}] ;# PE5/INT6
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#set_property IOSTANDARD LVCMOS33 [get_ports {PE[5]}]
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#set_property PACKAGE_PIN T16 [get_ports {PE[6]}] ;# PE6/T2EX
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#set_property IOSTANDARD LVCMOS33 [get_ports {PE[6]}]
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#set_property PACKAGE_PIN V16 [get_ports {SLRD}] ;# RDY0/SLRD
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#set_property IOSTANDARD LVCMOS33 [get_ports {SLRD}]
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#set_property PACKAGE_PIN U16 [get_ports {SLWR}] ;# RDY1/SLWR
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#set_property IOSTANDARD LVCMOS33 [get_ports {SLWR}]
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#set_property PACKAGE_PIN V17 [get_ports {RDY2}] ;# RDY2
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#set_property IOSTANDARD LVCMOS33 [get_ports {RDY2}]
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#set_property PACKAGE_PIN U17 [get_ports {RDY3}] ;# RDY3
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#set_property IOSTANDARD LVCMOS33 [get_ports {RDY3}]
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#set_property PACKAGE_PIN U18 [get_ports {RDY4}] ;# RDY4
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#set_property IOSTANDARD LVCMOS33 [get_ports {RDY4}]
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#set_property PACKAGE_PIN T18 [get_ports {RDY5}] ;# RDY5
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#set_property IOSTANDARD LVCMOS33 [get_ports {RDY5}]
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#set_property PACKAGE_PIN N16 [get_ports {FLAGA}] ;# CTL0/FLAGA
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#set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}]
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#set_property PACKAGE_PIN N15 [get_ports {FLAGB}] ;# CTL1/FLAGB
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#set_property IOSTANDARD LVCMOS33 [get_ports {FLAGB}]
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#set_property PACKAGE_PIN N14 [get_ports {FLAGC}] ;# CTL2/FLAGC
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#set_property IOSTANDARD LVCMOS33 [get_ports {FLAGC}]
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#set_property PACKAGE_PIN N17 [get_ports {CTL3}] ;# CTL3
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#set_property IOSTANDARD LVCMOS33 [get_ports {CTL3}]
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#set_property PACKAGE_PIN M13 [get_ports {CTL4}] ;# CTL4
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#set_property IOSTANDARD LVCMOS33 [get_ports {CTL4}]
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#set_property PACKAGE_PIN D10 [get_ports {INT4}] ;# INT4
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#set_property IOSTANDARD LVCMOS33 [get_ports {INT4}]
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#set_property PACKAGE_PIN U12 [get_ports {INT5_N}] ;# INT5#
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#set_property IOSTANDARD LVCMOS33 [get_ports {INT5_N}]
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#set_property PACKAGE_PIN M17 [get_ports {T0}] ;# T0
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#set_property IOSTANDARD LVCMOS33 [get_ports {T0}]
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#set_property PACKAGE_PIN B8 [get_ports {SCL}] ;# SCL
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#set_property IOSTANDARD LVCMOS33 [get_ports {SCL}]
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#set_property PACKAGE_PIN A10 [get_ports {SDA}] ;# SDA
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#set_property IOSTANDARD LVCMOS33 [get_ports {SDA}]
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#set_property PACKAGE_PIN A8 [get_ports {RxD0}] ;# RxD0
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#set_property IOSTANDARD LVCMOS33 [get_ports {RxD0}]
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#set_property PACKAGE_PIN A9 [get_ports {TxD0}] ;# TxD0
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#set_property IOSTANDARD LVCMOS33 [get_ports {TxD0}]
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# external I/O
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create_clock -name SBUS_3V3_CLK -period 40 [get_ports SBUS_3V3_CLK]
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# COPY/PASTE here then fix
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# * -> s
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# ]s -> s earlier (ACK ; INT have no brackets)
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# leading 0 in [0x (but not [0]!)
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# comment out TX, RX, SD_*
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# PMOD-x -> PMODx
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# EER -> ERR
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set_property PACKAGE_PIN K16 [get_ports {SBUS_3V3_D[1]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[1]}]
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set_property PACKAGE_PIN J18 [get_ports {SBUS_3V3_D[0]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[0]}]
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set_property PACKAGE_PIN K15 [get_ports {SBUS_3V3_D[3]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[3]}]
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set_property PACKAGE_PIN J17 [get_ports {SBUS_3V3_D[2]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[2]}]
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set_property PACKAGE_PIN J15 [get_ports {SBUS_3V3_D[5]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[5]}]
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set_property PACKAGE_PIN K13 [get_ports {SBUS_3V3_D[4]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[4]}]
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set_property PACKAGE_PIN H15 [get_ports {SBUS_3V3_INT2s}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT2s}]
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set_property PACKAGE_PIN J13 [get_ports {SBUS_3V3_D[6]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[6]}]
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set_property PACKAGE_PIN J14 [get_ports {SBUS_3V3_D[7]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[7]}]
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set_property PACKAGE_PIN H14 [get_ports {SBUS_3V3_D[8]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[8]}]
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set_property PACKAGE_PIN H17 [get_ports {SBUS_3V3_D[9]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[9]}]
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set_property PACKAGE_PIN G14 [get_ports {SBUS_3V3_D[10]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[10]}]
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set_property PACKAGE_PIN G17 [get_ports {SBUS_3V3_D[11]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[11]}]
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set_property PACKAGE_PIN G16 [get_ports {SBUS_3V3_D[12]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[12]}]
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set_property PACKAGE_PIN G18 [get_ports {SBUS_3V3_D[13]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[13]}]
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set_property PACKAGE_PIN H16 [get_ports {SBUS_3V3_D[14]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[14]}]
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set_property PACKAGE_PIN F18 [get_ports {SBUS_3V3_D[15]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[15]}]
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set_property PACKAGE_PIN F16 [get_ports {SBUS_3V3_D[16]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[16]}]
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set_property PACKAGE_PIN E18 [get_ports {SBUS_3V3_D[17]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[17]}]
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set_property PACKAGE_PIN F15 [get_ports {SBUS_3V3_D[18]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[18]}]
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set_property PACKAGE_PIN D18 [get_ports {SBUS_3V3_D[19]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[19]}]
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set_property PACKAGE_PIN E17 [get_ports {SBUS_3V3_D[20]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[20]}]
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set_property PACKAGE_PIN G13 [get_ports {SBUS_3V3_D[21]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[21]}]
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set_property PACKAGE_PIN D17 [get_ports {SBUS_3V3_D[22]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[22]}]
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set_property PACKAGE_PIN F13 [get_ports {SBUS_3V3_D[23]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[23]}]
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set_property PACKAGE_PIN F14 [get_ports {SBUS_3V3_D[24]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[24]}]
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set_property PACKAGE_PIN E16 [get_ports {SBUS_3V3_D[25]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[25]}]
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set_property PACKAGE_PIN E15 [get_ports {SBUS_3V3_D[26]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[26]}]
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set_property PACKAGE_PIN C17 [get_ports {SBUS_3V3_D[27]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[27]}]
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set_property PACKAGE_PIN C16 [get_ports {SBUS_3V3_D[28]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[28]}]
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set_property PACKAGE_PIN A18 [get_ports {SBUS_3V3_D[29]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[29]}]
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set_property PACKAGE_PIN B18 [get_ports {SBUS_3V3_D[30]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[30]}]
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set_property PACKAGE_PIN C15 [get_ports {SBUS_3V3_D[31]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[31]}]
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set_property PACKAGE_PIN D15 [get_ports {SBUS_3V3_CLK}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_CLK}]
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set_property PACKAGE_PIN B17 [get_ports {SBUS_3V3_PA[1]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[1]}]
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set_property PACKAGE_PIN B16 [get_ports {SBUS_3V3_PA[0]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[0]}]
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set_property PACKAGE_PIN C14 [get_ports {SBUS_3V3_PA[3]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[3]}]
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set_property PACKAGE_PIN D14 [get_ports {SBUS_3V3_PA[2]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[2]}]
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set_property PACKAGE_PIN D13 [get_ports {SBUS_3V3_ERRs}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ERRs}]
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set_property PACKAGE_PIN D12 [get_ports {SBUS_3V3_PA[4]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[4]}]
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set_property PACKAGE_PIN A16 [get_ports {SBUS_3V3_PA[5]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[5]}]
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set_property PACKAGE_PIN A15 [get_ports {SBUS_3V3_PA[6]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[6]}]
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set_property PACKAGE_PIN B14 [get_ports {SBUS_3V3_PA[7]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[7]}]
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set_property PACKAGE_PIN B13 [get_ports {SBUS_3V3_PA[8]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[8]}]
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set_property PACKAGE_PIN B12 [get_ports {SBUS_3V3_PA[9]}]
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set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[9]}]
|
||||
set_property PACKAGE_PIN C12 [get_ports {SBUS_3V3_PA[10]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[10]}]
|
||||
set_property PACKAGE_PIN A14 [get_ports {SBUS_3V3_PA[11]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[11]}]
|
||||
set_property PACKAGE_PIN A13 [get_ports {SBUS_3V3_PA[12]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[12]}]
|
||||
set_property PACKAGE_PIN B11 [get_ports {SBUS_3V3_PA[13]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[13]}]
|
||||
set_property PACKAGE_PIN A11 [get_ports {SBUS_3V3_PA[14]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[14]}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_property PACKAGE_PIN U9 [get_ports {RX}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {RX}]
|
||||
set_property PACKAGE_PIN V9 [get_ports {TX}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {TX}]
|
||||
set_property PACKAGE_PIN U8 [get_ports {USBH0_D+}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {USBH0_D+}]
|
||||
set_property PACKAGE_PIN V7 [get_ports {SD_D2}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SD_D2}]
|
||||
set_property PACKAGE_PIN U7 [get_ports {USBH0_D-}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {USBH0_D-}]
|
||||
set_property PACKAGE_PIN V6 [get_ports {SD_D3}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SD_D3}]
|
||||
set_property PACKAGE_PIN U6 [get_ports {PMOD12}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD12}]
|
||||
set_property PACKAGE_PIN V5 [get_ports {SD_D0}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SD_D0}]
|
||||
set_property PACKAGE_PIN T8 [get_ports {PMOD11}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD11}]
|
||||
set_property PACKAGE_PIN V4 [get_ports {SD_D1}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SD_D1}]
|
||||
set_property PACKAGE_PIN R8 [get_ports {SD_CLK}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SD_CLK}]
|
||||
set_property PACKAGE_PIN T5 [get_ports {SD_CMD}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SD_CMD}]
|
||||
set_property PACKAGE_PIN R7 [get_ports {SBUS_3V3_BGs}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_BGs}]
|
||||
set_property PACKAGE_PIN T4 [get_ports {SBUS_3V3_ASs}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ASs}]
|
||||
set_property PACKAGE_PIN T6 [get_ports {SBUS_3V3_SIZ[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[0]}]
|
||||
set_property PACKAGE_PIN U4 [get_ports {PMOD8}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD8}]
|
||||
set_property PACKAGE_PIN R6 [get_ports {SBUS_3V3_BRs}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_BRs}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {SBUS_3V3_SIZ[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[1]}]
|
||||
set_property PACKAGE_PIN R5 [get_ports {SBUS_3V3_INT1s}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT1s}]
|
||||
set_property PACKAGE_PIN V1 [get_ports {SBUS_3V3_SIZ[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[2]}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {SBUS_3V3_INT6s}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT6s}]
|
||||
set_property PACKAGE_PIN U1 [get_ports {SBUS_DATA_OE_LED}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_DATA_OE_LED}]
|
||||
set_property PACKAGE_PIN U2 [get_ports {SBUS_3V3_RSTs}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_RSTs}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {PMOD6}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD6}]
|
||||
set_property PACKAGE_PIN K6 [get_ports {SBUS_3V3_SELs}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SELs}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {SBUS_3V3_INT3s}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT3s}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_property PACKAGE_PIN N6 [get_ports {SBUS_3V3_PPRD}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PPRD}]
|
||||
set_property PACKAGE_PIN P5 [get_ports {SBUS_OE}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_OE}]
|
||||
set_property PACKAGE_PIN M6 [get_ports {SBUS_3V3_ACKs[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ACKs[0]}]
|
||||
set_property PACKAGE_PIN N5 [get_ports {SBUS_3V3_INT4s}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT4s}]
|
||||
set_property PACKAGE_PIN L6 [get_ports {SBUS_3V3_ACKs[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ACKs[1]}]
|
||||
set_property PACKAGE_PIN P4 [get_ports {PMOD10}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD10}]
|
||||
set_property PACKAGE_PIN L5 [get_ports {SBUS_3V3_INT5s}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT5s}]
|
||||
set_property PACKAGE_PIN P3 [get_ports {PMOD9}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD9}]
|
||||
set_property PACKAGE_PIN N4 [get_ports {SBUS_3V3_ACKs[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ACKs[2]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {PMOD7}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD7}]
|
||||
set_property PACKAGE_PIN M4 [get_ports {SBUS_3V3_PA[15]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[15]}]
|
||||
set_property PACKAGE_PIN R1 [get_ports {PMOD5}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {PMOD5}]
|
||||
set_property PACKAGE_PIN M3 [get_ports {SBUS_3V3_PA[17]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[17]}]
|
||||
set_property PACKAGE_PIN R2 [get_ports {SBUS_3V3_PA[16]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[16]}]
|
||||
set_property PACKAGE_PIN M2 [get_ports {SBUS_3V3_PA[19]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[19]}]
|
||||
set_property PACKAGE_PIN P2 [get_ports {SBUS_3V3_PA[18]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[18]}]
|
||||
set_property PACKAGE_PIN K5 [get_ports {SBUS_3V3_PA[21]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[21]}]
|
||||
set_property PACKAGE_PIN N2 [get_ports {SBUS_3V3_PA[20]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[20]}]
|
||||
set_property PACKAGE_PIN L4 [get_ports {SBUS_3V3_PA[23]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[23]}]
|
||||
set_property PACKAGE_PIN N1 [get_ports {SBUS_3V3_PA[22]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[22]}]
|
||||
set_property PACKAGE_PIN L3 [get_ports {SBUS_3V3_PA[25]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[25]}]
|
||||
set_property PACKAGE_PIN M1 [get_ports {SBUS_3V3_PA[24]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[24]}]
|
||||
set_property PACKAGE_PIN K3 [get_ports {SBUS_3V3_PA[27]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[27]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {SBUS_3V3_PA[26]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[26]}]
|
||||
279
sbus-to-ztex-gateware/sbus-to-ztex-timings-V1_2.xdc
Normal file
279
sbus-to-ztex-gateware/sbus-to-ztex-timings-V1_2.xdc
Normal file
@ -0,0 +1,279 @@
|
||||
# keep those for which timings are irrelevant
|
||||
# timing doesn't matter for LEDs
|
||||
set_false_path -from * -to [get_ports { SBUS_DATA_OE_LED } ]
|
||||
# timing doesn't matter for INTs, slow and async
|
||||
set_false_path -from * -to [get_ports { SBUS_3V3_INT1s } ]
|
||||
set_false_path -from * -to [get_ports { SBUS_3V3_INT2s } ]
|
||||
set_false_path -from * -to [get_ports { SBUS_3V3_INT3s } ]
|
||||
set_false_path -from * -to [get_ports { SBUS_3V3_INT4s } ]
|
||||
set_false_path -from * -to [get_ports { SBUS_3V3_INT5s } ]
|
||||
set_false_path -from * -to [get_ports { SBUS_3V3_INT6s } ]
|
||||
# slow
|
||||
set_false_path -from * -to [get_ports { TX } ]
|
||||
# unrelated
|
||||
set_clock_groups -asynchronous -group [get_clocks SBUS_3V3_CLK] -group [get_clocks fxclk_in]
|
||||
# timing doesn't matter for RST, very long hold
|
||||
set_false_path -from [get_ports { SBUS_3V3_RSTs } ] -to *
|
||||
# changes just once at start-up time, timing is irrelevant
|
||||
set_false_path -from * -to [get_ports { SBUS_OE } ]
|
||||
# shut up the warning for the LEDs (the set_false_path already lower severity)
|
||||
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { SBUS_DATA_OE_LED } ]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { SBUS_DATA_OE_LED } ]
|
||||
|
||||
# COPY/PASTE here, same fixes needed as in the other XDC file
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.838 [get_ports {SBUS_3V3_D[1]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.368 [get_ports {SBUS_3V3_D[1]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.738 [get_ports {SBUS_3V3_D[1]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.516 [get_ports {SBUS_3V3_D[1]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.874 [get_ports {SBUS_3V3_D[0]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.415 [get_ports {SBUS_3V3_D[0]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.702 [get_ports {SBUS_3V3_D[0]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.564 [get_ports {SBUS_3V3_D[0]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.841 [get_ports {SBUS_3V3_D[3]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.371 [get_ports {SBUS_3V3_D[3]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.736 [get_ports {SBUS_3V3_D[3]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.519 [get_ports {SBUS_3V3_D[3]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.838 [get_ports {SBUS_3V3_D[2]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.368 [get_ports {SBUS_3V3_D[2]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.738 [get_ports {SBUS_3V3_D[2]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.516 [get_ports {SBUS_3V3_D[2]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.842 [get_ports {SBUS_3V3_D[5]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.373 [get_ports {SBUS_3V3_D[5]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.734 [get_ports {SBUS_3V3_D[5]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.522 [get_ports {SBUS_3V3_D[5]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.882 [get_ports {SBUS_3V3_D[4]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.426 [get_ports {SBUS_3V3_D[4]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.694 [get_ports {SBUS_3V3_D[4]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.575 [get_ports {SBUS_3V3_D[4]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.695 [get_ports {SBUS_3V3_INT2s}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.573 [get_ports {SBUS_3V3_INT2s}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.839 [get_ports {SBUS_3V3_D[6]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.369 [get_ports {SBUS_3V3_D[6]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.737 [get_ports {SBUS_3V3_D[6]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.517 [get_ports {SBUS_3V3_D[6]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.810 [get_ports {SBUS_3V3_D[7]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.330 [get_ports {SBUS_3V3_D[7]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.766 [get_ports {SBUS_3V3_D[7]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.478 [get_ports {SBUS_3V3_D[7]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.810 [get_ports {SBUS_3V3_D[8]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.330 [get_ports {SBUS_3V3_D[8]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.766 [get_ports {SBUS_3V3_D[8]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.479 [get_ports {SBUS_3V3_D[8]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.751 [get_ports {SBUS_3V3_D[9]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.251 [get_ports {SBUS_3V3_D[9]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.825 [get_ports {SBUS_3V3_D[9]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.400 [get_ports {SBUS_3V3_D[9]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.804 [get_ports {SBUS_3V3_D[10]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.322 [get_ports {SBUS_3V3_D[10]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.772 [get_ports {SBUS_3V3_D[10]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.470 [get_ports {SBUS_3V3_D[10]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.756 [get_ports {SBUS_3V3_D[11]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.258 [get_ports {SBUS_3V3_D[11]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.820 [get_ports {SBUS_3V3_D[11]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.407 [get_ports {SBUS_3V3_D[11]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.778 [get_ports {SBUS_3V3_D[12]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.287 [get_ports {SBUS_3V3_D[12]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.798 [get_ports {SBUS_3V3_D[12]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.436 [get_ports {SBUS_3V3_D[12]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.729 [get_ports {SBUS_3V3_D[13]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.222 [get_ports {SBUS_3V3_D[13]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.847 [get_ports {SBUS_3V3_D[13]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.371 [get_ports {SBUS_3V3_D[13]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.750 [get_ports {SBUS_3V3_D[14]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.250 [get_ports {SBUS_3V3_D[14]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.826 [get_ports {SBUS_3V3_D[14]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.398 [get_ports {SBUS_3V3_D[14]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.708 [get_ports {SBUS_3V3_D[15]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.193 [get_ports {SBUS_3V3_D[15]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.869 [get_ports {SBUS_3V3_D[15]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.342 [get_ports {SBUS_3V3_D[15]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.817 [get_ports {SBUS_3V3_D[16]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.339 [get_ports {SBUS_3V3_D[16]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.759 [get_ports {SBUS_3V3_D[16]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.488 [get_ports {SBUS_3V3_D[16]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.707 [get_ports {SBUS_3V3_D[17]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.192 [get_ports {SBUS_3V3_D[17]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.870 [get_ports {SBUS_3V3_D[17]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.341 [get_ports {SBUS_3V3_D[17]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.724 [get_ports {SBUS_3V3_D[18]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.215 [get_ports {SBUS_3V3_D[18]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.852 [get_ports {SBUS_3V3_D[18]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.364 [get_ports {SBUS_3V3_D[18]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.711 [get_ports {SBUS_3V3_D[19]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.198 [get_ports {SBUS_3V3_D[19]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.865 [get_ports {SBUS_3V3_D[19]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.347 [get_ports {SBUS_3V3_D[19]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.705 [get_ports {SBUS_3V3_D[20]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.191 [get_ports {SBUS_3V3_D[20]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.871 [get_ports {SBUS_3V3_D[20]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.339 [get_ports {SBUS_3V3_D[20]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.758 [get_ports {SBUS_3V3_D[21]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.261 [get_ports {SBUS_3V3_D[21]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.818 [get_ports {SBUS_3V3_D[21]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.410 [get_ports {SBUS_3V3_D[21]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.707 [get_ports {SBUS_3V3_D[22]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.192 [get_ports {SBUS_3V3_D[22]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.869 [get_ports {SBUS_3V3_D[22]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.341 [get_ports {SBUS_3V3_D[22]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.695 [get_ports {SBUS_3V3_D[23]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.177 [get_ports {SBUS_3V3_D[23]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.881 [get_ports {SBUS_3V3_D[23]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.325 [get_ports {SBUS_3V3_D[23]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.654 [get_ports {SBUS_3V3_D[24]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.122 [get_ports {SBUS_3V3_D[24]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.922 [get_ports {SBUS_3V3_D[24]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.271 [get_ports {SBUS_3V3_D[24]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.682 [get_ports {SBUS_3V3_D[25]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.159 [get_ports {SBUS_3V3_D[25]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.894 [get_ports {SBUS_3V3_D[25]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.308 [get_ports {SBUS_3V3_D[25]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.633 [get_ports {SBUS_3V3_D[26]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.094 [get_ports {SBUS_3V3_D[26]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.943 [get_ports {SBUS_3V3_D[26]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.243 [get_ports {SBUS_3V3_D[26]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.655 [get_ports {SBUS_3V3_D[27]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.123 [get_ports {SBUS_3V3_D[27]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.921 [get_ports {SBUS_3V3_D[27]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.272 [get_ports {SBUS_3V3_D[27]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.632 [get_ports {SBUS_3V3_D[28]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.093 [get_ports {SBUS_3V3_D[28]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.944 [get_ports {SBUS_3V3_D[28]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.241 [get_ports {SBUS_3V3_D[28]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.662 [get_ports {SBUS_3V3_D[29]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.133 [get_ports {SBUS_3V3_D[29]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.914 [get_ports {SBUS_3V3_D[29]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.281 [get_ports {SBUS_3V3_D[29]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.618 [get_ports {SBUS_3V3_D[30]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.074 [get_ports {SBUS_3V3_D[30]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.958 [get_ports {SBUS_3V3_D[30]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.222 [get_ports {SBUS_3V3_D[30]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.688 [get_ports {SBUS_3V3_D[31]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.168 [get_ports {SBUS_3V3_D[31]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.888 [get_ports {SBUS_3V3_D[31]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.316 [get_ports {SBUS_3V3_D[31]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.645 [get_ports {SBUS_3V3_PA[1]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.109 [get_ports {SBUS_3V3_PA[1]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.649 [get_ports {SBUS_3V3_PA[0]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.116 [get_ports {SBUS_3V3_PA[0]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.658 [get_ports {SBUS_3V3_PA[3]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.127 [get_ports {SBUS_3V3_PA[3]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.656 [get_ports {SBUS_3V3_PA[2]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.125 [get_ports {SBUS_3V3_PA[2]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.688 [get_ports {SBUS_3V3_EERs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.167 [get_ports {SBUS_3V3_EERs}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.888 [get_ports {SBUS_3V3_EERs}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.316 [get_ports {SBUS_3V3_EERs}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.679 [get_ports {SBUS_3V3_PA[4]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.155 [get_ports {SBUS_3V3_PA[4]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.666 [get_ports {SBUS_3V3_PA[5]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.138 [get_ports {SBUS_3V3_PA[5]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.680 [get_ports {SBUS_3V3_PA[6]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.157 [get_ports {SBUS_3V3_PA[6]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.682 [get_ports {SBUS_3V3_PA[7]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.160 [get_ports {SBUS_3V3_PA[7]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.685 [get_ports {SBUS_3V3_PA[8]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.164 [get_ports {SBUS_3V3_PA[8]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.714 [get_ports {SBUS_3V3_PA[9]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.202 [get_ports {SBUS_3V3_PA[9]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.703 [get_ports {SBUS_3V3_PA[10]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.188 [get_ports {SBUS_3V3_PA[10]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.714 [get_ports {SBUS_3V3_PA[11]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.201 [get_ports {SBUS_3V3_PA[11]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.715 [get_ports {SBUS_3V3_PA[12]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.203 [get_ports {SBUS_3V3_PA[12]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.733 [get_ports {SBUS_3V3_PA[13]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.227 [get_ports {SBUS_3V3_PA[13]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.729 [get_ports {SBUS_3V3_PA[14]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.221 [get_ports {SBUS_3V3_PA[14]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 1.016 [get_ports {SBUS_3V3_BGs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.605 [get_ports {SBUS_3V3_BGs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.936 [get_ports {SBUS_3V3_ASs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.497 [get_ports {SBUS_3V3_ASs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.981 [get_ports {SBUS_3V3_SIZ[0]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.558 [get_ports {SBUS_3V3_SIZ[0]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.595 [get_ports {SBUS_3V3_SIZ[0]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.706 [get_ports {SBUS_3V3_SIZ[0]}]
|
||||
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.625 [get_ports {SBUS_3V3_BRs}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.667 [get_ports {SBUS_3V3_BRs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.921 [get_ports {SBUS_3V3_SIZ[1]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.478 [get_ports {SBUS_3V3_SIZ[1]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.655 [get_ports {SBUS_3V3_SIZ[1]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.627 [get_ports {SBUS_3V3_SIZ[1]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.604 [get_ports {SBUS_3V3_INT1s}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.695 [get_ports {SBUS_3V3_INT1s}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.932 [get_ports {SBUS_3V3_SIZ[2]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.493 [get_ports {SBUS_3V3_SIZ[2]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.644 [get_ports {SBUS_3V3_SIZ[2]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.641 [get_ports {SBUS_3V3_SIZ[2]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.895 [get_ports {SBUS_3V3_INT6s}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.443 [get_ports {SBUS_3V3_INT6s}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.681 [get_ports {SBUS_3V3_INT6s}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.592 [get_ports {SBUS_3V3_INT6s}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 1.100 [get_ports {SBUS_3V3_RSTs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.717 [get_ports {SBUS_3V3_RSTs}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.931 [get_ports {SBUS_3V3_SELs}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.491 [get_ports {SBUS_3V3_SELs}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.492 [get_ports {SBUS_3V3_INT3s}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.845 [get_ports {SBUS_3V3_INT3s}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.831 [get_ports {SBUS_3V3_PPRD}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.358 [get_ports {SBUS_3V3_PPRD}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.745 [get_ports {SBUS_3V3_PPRD}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.507 [get_ports {SBUS_3V3_PPRD}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.833 [get_ports {SBUS_3V3_ACKs[0]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.361 [get_ports {SBUS_3V3_ACKs[0]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.743 [get_ports {SBUS_3V3_ACKs[0]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.510 [get_ports {SBUS_3V3_ACKs[0]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.641 [get_ports {SBUS_3V3_INT4s}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.645 [get_ports {SBUS_3V3_INT4s}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.829 [get_ports {SBUS_3V3_ACKs[1]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.355 [get_ports {SBUS_3V3_ACKs[1]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.747 [get_ports {SBUS_3V3_ACKs[1]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.504 [get_ports {SBUS_3V3_ACKs[1]}]
|
||||
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.717 [get_ports {SBUS_3V3_INT5s}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.544 [get_ports {SBUS_3V3_INT5s}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.799 [get_ports {SBUS_3V3_ACKs[2]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.315 [get_ports {SBUS_3V3_ACKs[2]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -min -1.778 [get_ports {SBUS_3V3_ACKs[2]}]
|
||||
set_output_delay -clock SBUS_3V3_CLK -max 21.463 [get_ports {SBUS_3V3_ACKs[2]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.788 [get_ports {SBUS_3V3_PA[15]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.301 [get_ports {SBUS_3V3_PA[15]}]
|
||||
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.797 [get_ports {SBUS_3V3_PA[17]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.313 [get_ports {SBUS_3V3_PA[17]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.855 [get_ports {SBUS_3V3_PA[16]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.389 [get_ports {SBUS_3V3_PA[16]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.811 [get_ports {SBUS_3V3_PA[19]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.332 [get_ports {SBUS_3V3_PA[19]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.852 [get_ports {SBUS_3V3_PA[18]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.386 [get_ports {SBUS_3V3_PA[18]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.812 [get_ports {SBUS_3V3_PA[21]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.332 [get_ports {SBUS_3V3_PA[21]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.849 [get_ports {SBUS_3V3_PA[20]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.382 [get_ports {SBUS_3V3_PA[20]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.818 [get_ports {SBUS_3V3_PA[23]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.340 [get_ports {SBUS_3V3_PA[23]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.859 [get_ports {SBUS_3V3_PA[22]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.395 [get_ports {SBUS_3V3_PA[22]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.827 [get_ports {SBUS_3V3_PA[25]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.352 [get_ports {SBUS_3V3_PA[25]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.863 [get_ports {SBUS_3V3_PA[24]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.401 [get_ports {SBUS_3V3_PA[24]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.824 [get_ports {SBUS_3V3_PA[27]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.348 [get_ports {SBUS_3V3_PA[27]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -min 0.871 [get_ports {SBUS_3V3_PA[26]}]
|
||||
set_input_delay -clock SBUS_3V3_CLK -max 25.412 [get_ports {SBUS_3V3_PA[26]}]
|
||||
@ -116,7 +116,7 @@ Text GLabel 4100 2850 2 60 Input ~ 0
|
||||
SBUS_3V3_D[24]
|
||||
Text GLabel 6650 5700 2 60 Input ~ 0
|
||||
SBUS_3V3_INT[7]*
|
||||
Text GLabel 1600 3550 0 60 Input ~ 0
|
||||
Text GLabel 7400 2350 0 60 Input ~ 0
|
||||
SBUS_3V3_INT[6]*
|
||||
Text GLabel 7400 3250 0 60 Input ~ 0
|
||||
SBUS_3V3_INT[5]*
|
||||
@ -210,7 +210,7 @@ Text GLabel 7400 3050 0 60 Input ~ 0
|
||||
SBUS_3V3_ACK[0]*
|
||||
Text GLabel 7400 2950 0 60 Input ~ 0
|
||||
SBUS_3V3_PPRD
|
||||
Text GLabel 7400 2350 0 60 Input ~ 0
|
||||
Text GLabel 1600 3550 0 60 Input ~ 0
|
||||
SBUS_3V3_EER*
|
||||
Wire Wire Line
|
||||
1800 5850 1650 5850
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Drill report for /home/dolbeau/SPARC/SBusFPGA/sbus-to-ztex/sbus-to-ztex.kicad_pcb
|
||||
Created on Sat Aug 28 15:33:48 2021
|
||||
Created on Sat Aug 28 17:01:10 2021
|
||||
|
||||
Copper Layer Stackup:
|
||||
=============================================================
|
||||
@ -12,7 +12,7 @@ Copper Layer Stackup:
|
||||
Drill file 'sbus-to-ztex-PTH.drl' contains
|
||||
plated through holes:
|
||||
=============================================================
|
||||
T1 0.40mm 0.016" (123 holes)
|
||||
T1 0.40mm 0.016" (122 holes)
|
||||
T2 0.60mm 0.024" (2 holes) (with 2 slots)
|
||||
T3 0.80mm 0.031" (96 holes)
|
||||
T4 0.85mm 0.033" (2 holes)
|
||||
@ -22,7 +22,7 @@ Drill file 'sbus-to-ztex-PTH.drl' contains
|
||||
T8 1.19mm 0.047" (12 holes)
|
||||
T9 1.20mm 0.047" (3 holes)
|
||||
|
||||
Total plated holes count 386
|
||||
Total plated holes count 385
|
||||
|
||||
|
||||
Drill file 'sbus-to-ztex-NPTH.drl' contains
|
||||
|
||||
@ -17,7 +17,7 @@ DOE1,LTST-C170KRKT,1,
|
||||
FB1,PZ2012U221-2R0TF,1,
|
||||
J1,PZ254R-11-06P,1,https://lcsc.com/product-detail/Pin-Header-Female-Header_XFCN-PZ254R-11-06P_C492414.html
|
||||
U5,SN65220DBVR,1,
|
||||
"U1,U2,U3",SN74CB3T16211DGGR,3,
|
||||
"U1,U2,U3",SN74CB3T16211DGGR,3,https://lcsc.com/product-detail/Signal-Switches-Encoders-Decoders-Multiplexers_Texas-Instruments-SN74CB3T16211DGGR_C2653275.html
|
||||
U4,SN74CB3T3125PW,1,
|
||||
"U_INT1,U_INT2,U_INT3",SN74LVC2G07DBVR,3,
|
||||
U7,TPS2051CDBVR,1,https://www.mouser.fr/ProductDetail/Texas-Instruments/TPS2051CDBVR?qs=PF3AD18CSE5vi2HeWLJCmw%3D%3D
|
||||
|
||||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
(export (version D)
|
||||
(design
|
||||
(source /home/dolbeau/SPARC/SBusFPGA/sbus-to-ztex/sbus-to-ztex.sch)
|
||||
(date "Sat Aug 28 15:05:36 2021")
|
||||
(date "Sat Aug 28 16:15:15 2021")
|
||||
(tool "Eeschema 5.0.2+dfsg1-1~bpo9+1")
|
||||
(sheet (number 1) (name /) (tstamps /)
|
||||
(title_block
|
||||
@ -184,7 +184,9 @@
|
||||
(value SN74CB3T16211DGGR)
|
||||
(footprint For_SeeedStudio:TSSOP-56_6.1x14mm_P0.5mm_For_SeeedStudio)
|
||||
(fields
|
||||
(field (name MPN) SN74CB3T16211DGGR))
|
||||
(field (name MPN) SN74CB3T16211DGGR)
|
||||
(field (name URL) https://lcsc.com/product-detail/Signal-Switches-Encoders-Decoders-Multiplexers_Texas-Instruments-SN74CB3T16211DGGR_C2653275.html)
|
||||
(field (name URL-alt) https://www.mouser.fr/ProductDetail/Texas-Instruments/SN74CB3T16211DGGR?qs=%2Fha2pyFadujLgV8PJqueL5aUGpX9%252BbECTuUAq6EU8VAiPml4qcD9lw%3D%3D))
|
||||
(libsource (lib ul_SN74CB3T16211DGGR) (part SN74CB3T16211DGGR) (description ""))
|
||||
(sheetpath (names /sbus/) (tstamps /5F679B53/))
|
||||
(tstamp 5F8F42F3))
|
||||
@ -1162,7 +1164,7 @@
|
||||
(node (ref U2) (pin 30)))
|
||||
(net (code 3) (name SBUS_3V3_EER*)
|
||||
(node (ref U1) (pin 54))
|
||||
(node (ref JCD1) (pin 25)))
|
||||
(node (ref JAB1) (pin 49)))
|
||||
(net (code 4) (name SBUS_OE)
|
||||
(node (ref U4) (pin 10))
|
||||
(node (ref U1) (pin 55))
|
||||
@ -1171,15 +1173,16 @@
|
||||
(node (ref U2) (pin 55))
|
||||
(node (ref JCD1) (pin 38))
|
||||
(node (ref U4) (pin 1))
|
||||
(node (ref U3) (pin 55))
|
||||
(node (ref U3) (pin 56))
|
||||
(node (ref R13) (pin 2))
|
||||
(node (ref U3) (pin 55)))
|
||||
(node (ref R13) (pin 2)))
|
||||
(net (code 5) (name GND)
|
||||
(node (ref SBus1) (pin 92))
|
||||
(node (ref C9) (pin 2))
|
||||
(node (ref SBus1) (pin 84))
|
||||
(node (ref J5) (pin 3))
|
||||
(node (ref J5) (pin 4))
|
||||
(node (ref SBus1) (pin 01))
|
||||
(node (ref C1) (pin 2))
|
||||
(node (ref J2) (pin 6))
|
||||
(node (ref J2) (pin G1))
|
||||
@ -1189,7 +1192,7 @@
|
||||
(node (ref SBus1) (pin 76))
|
||||
(node (ref C2) (pin 2))
|
||||
(node (ref SBus1) (pin 68))
|
||||
(node (ref SBus1) (pin 01))
|
||||
(node (ref J6) (pin 1))
|
||||
(node (ref SBus1) (pin 60))
|
||||
(node (ref U3) (pin 19))
|
||||
(node (ref U3) (pin 49))
|
||||
@ -1202,7 +1205,6 @@
|
||||
(node (ref U4) (pin 7))
|
||||
(node (ref C6) (pin 2))
|
||||
(node (ref SBus1) (pin 52))
|
||||
(node (ref J6) (pin 1))
|
||||
(node (ref C13) (pin 2))
|
||||
(node (ref U4) (pin 12))
|
||||
(node (ref U4) (pin 11))
|
||||
@ -1247,11 +1249,11 @@
|
||||
(node (ref U1) (pin 8))
|
||||
(node (ref U7) (pin 2))
|
||||
(node (ref U2) (pin 38))
|
||||
(node (ref U2) (pin 8))
|
||||
(node (ref C11) (pin 2))
|
||||
(node (ref J4) (pin 6))
|
||||
(node (ref J4) (pin 5))
|
||||
(node (ref J4) (pin 4))
|
||||
(node (ref U2) (pin 8))
|
||||
(node (ref C5) (pin 2))
|
||||
(node (ref R15) (pin 2))
|
||||
(node (ref R14) (pin 1))
|
||||
@ -1268,38 +1270,38 @@
|
||||
(node (ref JAB1) (pin 41))
|
||||
(node (ref U2) (pin 44)))
|
||||
(net (code 10) (name SBUS_3V3_PA[04])
|
||||
(node (ref U2) (pin 32))
|
||||
(node (ref JAB1) (pin 50)))
|
||||
(node (ref JAB1) (pin 50))
|
||||
(node (ref U2) (pin 32)))
|
||||
(net (code 11) (name SBUS_3V3_PA[03])
|
||||
(node (ref U2) (pin 33))
|
||||
(node (ref JAB1) (pin 47)))
|
||||
(node (ref JAB1) (pin 47))
|
||||
(node (ref U2) (pin 33)))
|
||||
(net (code 12) (name SBUS_3V3_PA[02])
|
||||
(node (ref JAB1) (pin 48))
|
||||
(node (ref U2) (pin 34)))
|
||||
(net (code 13) (name SBUS_3V3_PA[01])
|
||||
(node (ref U2) (pin 35))
|
||||
(node (ref JAB1) (pin 45)))
|
||||
(node (ref JAB1) (pin 45))
|
||||
(node (ref U2) (pin 35)))
|
||||
(net (code 14) (name SBUS_3V3_PA[00])
|
||||
(node (ref JAB1) (pin 46))
|
||||
(node (ref U2) (pin 36)))
|
||||
(node (ref U2) (pin 36))
|
||||
(node (ref JAB1) (pin 46)))
|
||||
(net (code 15) (name SBUS_3V3_PPRD)
|
||||
(node (ref U2) (pin 37))
|
||||
(node (ref JCD1) (pin 37)))
|
||||
(node (ref JCD1) (pin 37))
|
||||
(node (ref U2) (pin 37)))
|
||||
(net (code 16) (name SBUS_3V3_SIZ[2])
|
||||
(node (ref JCD1) (pin 24))
|
||||
(node (ref U2) (pin 39)))
|
||||
(node (ref U2) (pin 39))
|
||||
(node (ref JCD1) (pin 24)))
|
||||
(net (code 17) (name SBUS_3V3_SIZ[1])
|
||||
(node (ref JCD1) (pin 22))
|
||||
(node (ref U2) (pin 40)))
|
||||
(net (code 18) (name SBUS_3V3_SIZ[0])
|
||||
(node (ref U2) (pin 41))
|
||||
(node (ref JCD1) (pin 19)))
|
||||
(node (ref JCD1) (pin 19))
|
||||
(node (ref U2) (pin 41)))
|
||||
(net (code 19) (name SBUS_3V3_D[31])
|
||||
(node (ref U2) (pin 42))
|
||||
(node (ref JAB1) (pin 43)))
|
||||
(net (code 20) (name SBUS_3V3_D[30])
|
||||
(node (ref JAB1) (pin 42))
|
||||
(node (ref U2) (pin 43)))
|
||||
(node (ref U2) (pin 43))
|
||||
(node (ref JAB1) (pin 42)))
|
||||
(net (code 21) (name SBUS_3V3_PA[08])
|
||||
(node (ref U1) (pin 53))
|
||||
(node (ref JAB1) (pin 54)))
|
||||
@ -1316,27 +1318,28 @@
|
||||
(node (ref U2) (pin 48))
|
||||
(node (ref JAB1) (pin 37)))
|
||||
(net (code 26) (name SBUS_3V3_D[24])
|
||||
(node (ref JAB1) (pin 36))
|
||||
(node (ref U2) (pin 50)))
|
||||
(node (ref U2) (pin 50))
|
||||
(node (ref JAB1) (pin 36)))
|
||||
(net (code 27) (name SBUS_3V3_D[23])
|
||||
(node (ref U2) (pin 51))
|
||||
(node (ref JAB1) (pin 35)))
|
||||
(node (ref JAB1) (pin 35))
|
||||
(node (ref U2) (pin 51)))
|
||||
(net (code 28) (name SBUS_3V3_D[22])
|
||||
(node (ref JAB1) (pin 28))
|
||||
(node (ref U2) (pin 52)))
|
||||
(node (ref U2) (pin 52))
|
||||
(node (ref JAB1) (pin 28)))
|
||||
(net (code 29) (name SBUS_3V3_D[21])
|
||||
(node (ref JAB1) (pin 27))
|
||||
(node (ref U2) (pin 53)))
|
||||
(node (ref U2) (pin 53))
|
||||
(node (ref JAB1) (pin 27)))
|
||||
(net (code 30) (name SBUS_3V3_D[20])
|
||||
(node (ref JAB1) (pin 26))
|
||||
(node (ref U2) (pin 54)))
|
||||
(node (ref U2) (pin 54))
|
||||
(node (ref JAB1) (pin 26)))
|
||||
(net (code 31) (name +3V3)
|
||||
(node (ref U2) (pin 17))
|
||||
(node (ref C31) (pin 1))
|
||||
(node (ref C1) (pin 1))
|
||||
(node (ref J2) (pin 4))
|
||||
(node (ref R31) (pin 1))
|
||||
(node (ref R30) (pin 1))
|
||||
(node (ref R31) (pin 1))
|
||||
(node (ref C31) (pin 1))
|
||||
(node (ref JCD1) (pin 31))
|
||||
(node (ref U2) (pin 17))
|
||||
(node (ref J2) (pin 4))
|
||||
(node (ref C1) (pin 1))
|
||||
(node (ref JCD1) (pin 36))
|
||||
(node (ref C12) (pin 1))
|
||||
(node (ref JCD1) (pin 32))
|
||||
@ -1344,7 +1347,6 @@
|
||||
(node (ref U_INT1) (pin 5))
|
||||
(node (ref JCD1) (pin 35))
|
||||
(node (ref JAB1) (pin 30))
|
||||
(node (ref JCD1) (pin 31))
|
||||
(node (ref JAB1) (pin 34))
|
||||
(node (ref JAB1) (pin 29))
|
||||
(node (ref JAB1) (pin 33))
|
||||
@ -1416,20 +1418,20 @@
|
||||
(node (ref U1) (pin 36))
|
||||
(node (ref JCD1) (pin 54)))
|
||||
(net (code 46) (name SBUS_3V3_PA[19])
|
||||
(node (ref JCD1) (pin 51))
|
||||
(node (ref U1) (pin 37)))
|
||||
(node (ref U1) (pin 37))
|
||||
(node (ref JCD1) (pin 51)))
|
||||
(net (code 47) (name SBUS_3V3_PA[18])
|
||||
(node (ref JCD1) (pin 52))
|
||||
(node (ref U1) (pin 39)))
|
||||
(node (ref U1) (pin 39))
|
||||
(node (ref JCD1) (pin 52)))
|
||||
(net (code 48) (name SBUS_3V3_PA[17])
|
||||
(node (ref JCD1) (pin 49))
|
||||
(node (ref U1) (pin 40)))
|
||||
(node (ref U1) (pin 40))
|
||||
(node (ref JCD1) (pin 49)))
|
||||
(net (code 49) (name SBUS_3V3_ACK[2]*)
|
||||
(node (ref U1) (pin 42))
|
||||
(node (ref JCD1) (pin 45)))
|
||||
(node (ref JCD1) (pin 45))
|
||||
(node (ref U1) (pin 42)))
|
||||
(net (code 50) (name SBUS_3V3_PA[15])
|
||||
(node (ref JCD1) (pin 47))
|
||||
(node (ref U1) (pin 43)))
|
||||
(node (ref U1) (pin 43))
|
||||
(node (ref JCD1) (pin 47)))
|
||||
(net (code 51) (name SBUS_3V3_PA[14])
|
||||
(node (ref U1) (pin 44))
|
||||
(node (ref JAB1) (pin 60)))
|
||||
@ -1437,11 +1439,11 @@
|
||||
(node (ref U1) (pin 45))
|
||||
(node (ref JAB1) (pin 59)))
|
||||
(net (code 53) (name SBUS_3V3_ACK[1]*)
|
||||
(node (ref JCD1) (pin 41))
|
||||
(node (ref U1) (pin 46)))
|
||||
(node (ref U1) (pin 46))
|
||||
(node (ref JCD1) (pin 41)))
|
||||
(net (code 54) (name SBUS_3V3_PA[12])
|
||||
(node (ref U1) (pin 47))
|
||||
(node (ref JAB1) (pin 58)))
|
||||
(node (ref JAB1) (pin 58))
|
||||
(node (ref U1) (pin 47)))
|
||||
(net (code 55) (name SBUS_3V3_PA[11])
|
||||
(node (ref U1) (pin 48))
|
||||
(node (ref JAB1) (pin 57)))
|
||||
@ -1455,9 +1457,9 @@
|
||||
(node (ref JAB1) (pin 55))
|
||||
(node (ref U1) (pin 52)))
|
||||
(net (code 59) (name SBUS_3V3_INT[1]*)
|
||||
(node (ref JCD1) (pin 23))
|
||||
(node (ref R2) (pin 2))
|
||||
(node (ref U_INT2) (pin 3)))
|
||||
(node (ref U_INT2) (pin 3))
|
||||
(node (ref JCD1) (pin 23)))
|
||||
(net (code 60) (name SBUS_3V3_INT[2]*)
|
||||
(node (ref R1) (pin 2))
|
||||
(node (ref JAB1) (pin 11))
|
||||
@ -1476,21 +1478,21 @@
|
||||
(node (ref SBus1) (pin 04)))
|
||||
(net (code 65) (name SBUS_3V3_INT[5]*)
|
||||
(node (ref R6) (pin 2))
|
||||
(node (ref U_INT3) (pin 3))
|
||||
(node (ref JCD1) (pin 43)))
|
||||
(node (ref JCD1) (pin 43))
|
||||
(node (ref U_INT3) (pin 3)))
|
||||
(net (code 66) (name SBUS_3V3_INT[6]*)
|
||||
(node (ref U_INT3) (pin 1))
|
||||
(node (ref JCD1) (pin 25))
|
||||
(node (ref R5) (pin 2))
|
||||
(node (ref JAB1) (pin 49)))
|
||||
(node (ref U_INT3) (pin 1)))
|
||||
(net (code 67) (name SBUS_3V3_D[03])
|
||||
(node (ref JAB1) (pin 7))
|
||||
(node (ref U3) (pin 47)))
|
||||
(net (code 68) (name SBUS_3V3_D[13])
|
||||
(node (ref JAB1) (pin 19))
|
||||
(node (ref U3) (pin 35)))
|
||||
(node (ref U3) (pin 35))
|
||||
(node (ref JAB1) (pin 19)))
|
||||
(net (code 69) (name SBUS_3V3_D[12])
|
||||
(node (ref JAB1) (pin 18))
|
||||
(node (ref U3) (pin 36)))
|
||||
(node (ref U3) (pin 36))
|
||||
(node (ref JAB1) (pin 18)))
|
||||
(net (code 70) (name SBUS_3V3_D[11])
|
||||
(node (ref U3) (pin 37))
|
||||
(node (ref JAB1) (pin 17)))
|
||||
@ -1513,20 +1515,20 @@
|
||||
(node (ref U3) (pin 44))
|
||||
(node (ref JAB1) (pin 10)))
|
||||
(net (code 77) (name SBUS_3V3_D[05])
|
||||
(node (ref U3) (pin 45))
|
||||
(node (ref JAB1) (pin 9)))
|
||||
(node (ref JAB1) (pin 9))
|
||||
(node (ref U3) (pin 45)))
|
||||
(net (code 78) (name SBUS_3V3_D[02])
|
||||
(node (ref JAB1) (pin 8))
|
||||
(node (ref U3) (pin 46)))
|
||||
(net (code 79) (name SBUS_3V3_D[14])
|
||||
(node (ref JAB1) (pin 20))
|
||||
(node (ref U3) (pin 34)))
|
||||
(node (ref U3) (pin 34))
|
||||
(node (ref JAB1) (pin 20)))
|
||||
(net (code 80) (name SBUS_3V3_D[00])
|
||||
(node (ref JAB1) (pin 6))
|
||||
(node (ref U3) (pin 48)))
|
||||
(net (code 81) (name SBUS_3V3_D[01])
|
||||
(node (ref U3) (pin 50))
|
||||
(node (ref JAB1) (pin 5)))
|
||||
(node (ref JAB1) (pin 5))
|
||||
(node (ref U3) (pin 50)))
|
||||
(net (code 82) (name SBUS_3V3_CLK)
|
||||
(node (ref JAB1) (pin 44))
|
||||
(node (ref U3) (pin 51)))
|
||||
@ -1534,26 +1536,26 @@
|
||||
(node (ref JCD1) (pin 18))
|
||||
(node (ref U3) (pin 52)))
|
||||
(net (code 84) (name SBUS_3V3_SEL*)
|
||||
(node (ref JCD1) (pin 29))
|
||||
(node (ref U3) (pin 53)))
|
||||
(node (ref U3) (pin 53))
|
||||
(node (ref JCD1) (pin 29)))
|
||||
(net (code 85) (name SBUS_3V3_RST*)
|
||||
(node (ref U3) (pin 54))
|
||||
(node (ref JCD1) (pin 27)))
|
||||
(node (ref JCD1) (pin 27))
|
||||
(node (ref U3) (pin 54)))
|
||||
(net (code 86) (name SBUS_3V3_D[19])
|
||||
(node (ref JAB1) (pin 25))
|
||||
(node (ref U3) (pin 29)))
|
||||
(node (ref U3) (pin 29))
|
||||
(node (ref JAB1) (pin 25)))
|
||||
(net (code 87) (name SBUS_3V3_D[18])
|
||||
(node (ref JAB1) (pin 24))
|
||||
(node (ref U3) (pin 30)))
|
||||
(node (ref U3) (pin 30))
|
||||
(node (ref JAB1) (pin 24)))
|
||||
(net (code 88) (name SBUS_3V3_D[17])
|
||||
(node (ref JAB1) (pin 23))
|
||||
(node (ref U3) (pin 31)))
|
||||
(node (ref U3) (pin 31))
|
||||
(node (ref JAB1) (pin 23)))
|
||||
(net (code 89) (name SBUS_3V3_D[16])
|
||||
(node (ref JAB1) (pin 22))
|
||||
(node (ref U3) (pin 32)))
|
||||
(node (ref U3) (pin 32))
|
||||
(node (ref JAB1) (pin 22)))
|
||||
(net (code 90) (name SBUS_3V3_D[15])
|
||||
(node (ref JAB1) (pin 21))
|
||||
(node (ref U3) (pin 33)))
|
||||
(node (ref U3) (pin 33))
|
||||
(node (ref JAB1) (pin 21)))
|
||||
(net (code 91) (name SBUS_3V3_BR*)
|
||||
(node (ref U4) (pin 3))
|
||||
(node (ref JCD1) (pin 21)))
|
||||
@ -1570,8 +1572,8 @@
|
||||
(node (ref SBus1) (pin 31))
|
||||
(node (ref U2) (pin 25)))
|
||||
(net (code 96) (name SBUS_5V_EER*)
|
||||
(node (ref SBus1) (pin 32))
|
||||
(node (ref U1) (pin 2)))
|
||||
(node (ref U1) (pin 2))
|
||||
(node (ref SBus1) (pin 32)))
|
||||
(net (code 97) (name SBUS_5V_PA[06])
|
||||
(node (ref SBus1) (pin 33))
|
||||
(node (ref U2) (pin 27)))
|
||||
@ -1582,8 +1584,8 @@
|
||||
(node (ref U1) (pin 6))
|
||||
(node (ref SBus1) (pin 35)))
|
||||
(net (code 100) (name SBUS_5V_ACK[0]*)
|
||||
(node (ref SBus1) (pin 36))
|
||||
(node (ref U1) (pin 5)))
|
||||
(node (ref U1) (pin 5))
|
||||
(node (ref SBus1) (pin 36)))
|
||||
(net (code 101) (name SBUS_5V_PA[12])
|
||||
(node (ref SBus1) (pin 37))
|
||||
(node (ref U1) (pin 9)))
|
||||
@ -1594,14 +1596,14 @@
|
||||
(node (ref U1) (pin 15))
|
||||
(node (ref SBus1) (pin 39)))
|
||||
(net (code 104) (name SBUS_5V_ACK[1]*)
|
||||
(node (ref U1) (pin 10))
|
||||
(node (ref SBus1) (pin 40)))
|
||||
(node (ref SBus1) (pin 40))
|
||||
(node (ref U1) (pin 10)))
|
||||
(net (code 105) (name SBUS_5V_PA[18])
|
||||
(node (ref U1) (pin 18))
|
||||
(node (ref SBus1) (pin 41)))
|
||||
(net (code 106) (name SBUS_5V_PA[00])
|
||||
(node (ref SBus1) (pin 29))
|
||||
(node (ref U2) (pin 21)))
|
||||
(node (ref U2) (pin 21))
|
||||
(node (ref SBus1) (pin 29)))
|
||||
(net (code 107) (name SBUS_5V_PA[22])
|
||||
(node (ref SBus1) (pin 43))
|
||||
(node (ref U1) (pin 23)))
|
||||
@ -1612,8 +1614,8 @@
|
||||
(node (ref SBus1) (pin 45))
|
||||
(node (ref U1) (pin 25)))
|
||||
(net (code 110) (name SBUS_5V_PA[26])
|
||||
(node (ref U1) (pin 28))
|
||||
(node (ref SBus1) (pin 46)))
|
||||
(node (ref SBus1) (pin 46))
|
||||
(node (ref U1) (pin 28)))
|
||||
(net (code 111) (name SBUS_5V_DP)
|
||||
(node (ref SBus1) (pin 47)))
|
||||
(net (code 112) (name SBUS_5V_-12V)
|
||||
@ -1628,8 +1630,8 @@
|
||||
(node (ref U3) (pin 4))
|
||||
(node (ref SBus1) (pin 51)))
|
||||
(net (code 116) (name SBUS_5V_D[01])
|
||||
(node (ref SBus1) (pin 53))
|
||||
(node (ref U3) (pin 6)))
|
||||
(node (ref U3) (pin 6))
|
||||
(node (ref SBus1) (pin 53)))
|
||||
(net (code 117) (name SBUS_5V_D[19])
|
||||
(node (ref U3) (pin 28))
|
||||
(node (ref SBus1) (pin 17)))
|
||||
@ -1637,17 +1639,17 @@
|
||||
(node (ref U3) (pin 7))
|
||||
(node (ref SBus1) (pin 05)))
|
||||
(net (code 119) (name SBUS_5V_D[02])
|
||||
(node (ref SBus1) (pin 06))
|
||||
(node (ref U3) (pin 10)))
|
||||
(node (ref U3) (pin 10))
|
||||
(node (ref SBus1) (pin 06)))
|
||||
(net (code 120) (name SBUS_5V_D[04])
|
||||
(node (ref SBus1) (pin 07))
|
||||
(node (ref U3) (pin 12)))
|
||||
(node (ref U3) (pin 12))
|
||||
(node (ref SBus1) (pin 07)))
|
||||
(net (code 121) (name SBUS_5V_D[06])
|
||||
(node (ref U3) (pin 13))
|
||||
(node (ref SBus1) (pin 09)))
|
||||
(node (ref SBus1) (pin 09))
|
||||
(node (ref U3) (pin 13)))
|
||||
(net (code 122) (name SBUS_5V_D[08])
|
||||
(node (ref U3) (pin 15))
|
||||
(node (ref SBus1) (pin 10)))
|
||||
(node (ref SBus1) (pin 10))
|
||||
(node (ref U3) (pin 15)))
|
||||
(net (code 123) (name SBUS_5V_D[10])
|
||||
(node (ref U3) (pin 18))
|
||||
(node (ref SBus1) (pin 11)))
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
update=22/05/2015 07:44:53
|
||||
update=Sat Aug 28 17:02:24 2021
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
@ -31,3 +31,13 @@ NetIExt=net
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
<export version="D">
|
||||
<design>
|
||||
<source>/home/dolbeau/SPARC/SBusFPGA/sbus-to-ztex/sbus-to-ztex.sch</source>
|
||||
<date>Sat Aug 28 15:36:11 2021</date>
|
||||
<date>Sat Aug 28 17:02:28 2021</date>
|
||||
<tool>Eeschema 5.0.2+dfsg1-1~bpo9+1</tool>
|
||||
<sheet number="1" name="/" tstamps="/">
|
||||
<title_block>
|
||||
@ -219,6 +219,8 @@
|
||||
<footprint>For_SeeedStudio:TSSOP-56_6.1x14mm_P0.5mm_For_SeeedStudio</footprint>
|
||||
<fields>
|
||||
<field name="MPN">SN74CB3T16211DGGR</field>
|
||||
<field name="URL">https://lcsc.com/product-detail/Signal-Switches-Encoders-Decoders-Multiplexers_Texas-Instruments-SN74CB3T16211DGGR_C2653275.html</field>
|
||||
<field name="URL-alt">https://www.mouser.fr/ProductDetail/Texas-Instruments/SN74CB3T16211DGGR?qs=%2Fha2pyFadujLgV8PJqueL5aUGpX9%252BbECTuUAq6EU8VAiPml4qcD9lw%3D%3D</field>
|
||||
</fields>
|
||||
<libsource lib="ul_SN74CB3T16211DGGR" part="SN74CB3T16211DGGR" description=""/>
|
||||
<sheetpath names="/sbus/" tstamps="/5F679B53/"/>
|
||||
@ -1367,7 +1369,7 @@
|
||||
</net>
|
||||
<net code="3" name="SBUS_3V3_EER*">
|
||||
<node ref="U1" pin="54"/>
|
||||
<node ref="JCD1" pin="25"/>
|
||||
<node ref="JAB1" pin="49"/>
|
||||
</net>
|
||||
<net code="4" name="SBUS_OE">
|
||||
<node ref="U4" pin="10"/>
|
||||
@ -1377,9 +1379,9 @@
|
||||
<node ref="U2" pin="55"/>
|
||||
<node ref="JCD1" pin="38"/>
|
||||
<node ref="U4" pin="1"/>
|
||||
<node ref="U3" pin="55"/>
|
||||
<node ref="U3" pin="56"/>
|
||||
<node ref="R13" pin="2"/>
|
||||
<node ref="U3" pin="55"/>
|
||||
</net>
|
||||
<net code="5" name="GND">
|
||||
<node ref="SBus1" pin="92"/>
|
||||
@ -1387,6 +1389,7 @@
|
||||
<node ref="SBus1" pin="84"/>
|
||||
<node ref="J5" pin="3"/>
|
||||
<node ref="J5" pin="4"/>
|
||||
<node ref="SBus1" pin="01"/>
|
||||
<node ref="C1" pin="2"/>
|
||||
<node ref="J2" pin="6"/>
|
||||
<node ref="J2" pin="G1"/>
|
||||
@ -1396,7 +1399,7 @@
|
||||
<node ref="SBus1" pin="76"/>
|
||||
<node ref="C2" pin="2"/>
|
||||
<node ref="SBus1" pin="68"/>
|
||||
<node ref="SBus1" pin="01"/>
|
||||
<node ref="J6" pin="1"/>
|
||||
<node ref="SBus1" pin="60"/>
|
||||
<node ref="U3" pin="19"/>
|
||||
<node ref="U3" pin="49"/>
|
||||
@ -1409,7 +1412,6 @@
|
||||
<node ref="U4" pin="7"/>
|
||||
<node ref="C6" pin="2"/>
|
||||
<node ref="SBus1" pin="52"/>
|
||||
<node ref="J6" pin="1"/>
|
||||
<node ref="C13" pin="2"/>
|
||||
<node ref="U4" pin="12"/>
|
||||
<node ref="U4" pin="11"/>
|
||||
@ -1454,11 +1456,11 @@
|
||||
<node ref="U1" pin="8"/>
|
||||
<node ref="U7" pin="2"/>
|
||||
<node ref="U2" pin="38"/>
|
||||
<node ref="U2" pin="8"/>
|
||||
<node ref="C11" pin="2"/>
|
||||
<node ref="J4" pin="6"/>
|
||||
<node ref="J4" pin="5"/>
|
||||
<node ref="J4" pin="4"/>
|
||||
<node ref="U2" pin="8"/>
|
||||
<node ref="C5" pin="2"/>
|
||||
<node ref="R15" pin="2"/>
|
||||
<node ref="R14" pin="1"/>
|
||||
@ -1480,48 +1482,48 @@
|
||||
<node ref="U2" pin="44"/>
|
||||
</net>
|
||||
<net code="10" name="SBUS_3V3_PA[04]">
|
||||
<node ref="U2" pin="32"/>
|
||||
<node ref="JAB1" pin="50"/>
|
||||
<node ref="U2" pin="32"/>
|
||||
</net>
|
||||
<net code="11" name="SBUS_3V3_PA[03]">
|
||||
<node ref="U2" pin="33"/>
|
||||
<node ref="JAB1" pin="47"/>
|
||||
<node ref="U2" pin="33"/>
|
||||
</net>
|
||||
<net code="12" name="SBUS_3V3_PA[02]">
|
||||
<node ref="JAB1" pin="48"/>
|
||||
<node ref="U2" pin="34"/>
|
||||
</net>
|
||||
<net code="13" name="SBUS_3V3_PA[01]">
|
||||
<node ref="U2" pin="35"/>
|
||||
<node ref="JAB1" pin="45"/>
|
||||
<node ref="U2" pin="35"/>
|
||||
</net>
|
||||
<net code="14" name="SBUS_3V3_PA[00]">
|
||||
<node ref="JAB1" pin="46"/>
|
||||
<node ref="U2" pin="36"/>
|
||||
<node ref="JAB1" pin="46"/>
|
||||
</net>
|
||||
<net code="15" name="SBUS_3V3_PPRD">
|
||||
<node ref="U2" pin="37"/>
|
||||
<node ref="JCD1" pin="37"/>
|
||||
<node ref="U2" pin="37"/>
|
||||
</net>
|
||||
<net code="16" name="SBUS_3V3_SIZ[2]">
|
||||
<node ref="JCD1" pin="24"/>
|
||||
<node ref="U2" pin="39"/>
|
||||
<node ref="JCD1" pin="24"/>
|
||||
</net>
|
||||
<net code="17" name="SBUS_3V3_SIZ[1]">
|
||||
<node ref="JCD1" pin="22"/>
|
||||
<node ref="U2" pin="40"/>
|
||||
</net>
|
||||
<net code="18" name="SBUS_3V3_SIZ[0]">
|
||||
<node ref="U2" pin="41"/>
|
||||
<node ref="JCD1" pin="19"/>
|
||||
<node ref="U2" pin="41"/>
|
||||
</net>
|
||||
<net code="19" name="SBUS_3V3_D[31]">
|
||||
<node ref="U2" pin="42"/>
|
||||
<node ref="JAB1" pin="43"/>
|
||||
</net>
|
||||
<net code="20" name="SBUS_3V3_D[30]">
|
||||
<node ref="JAB1" pin="42"/>
|
||||
<node ref="U2" pin="43"/>
|
||||
<node ref="JAB1" pin="42"/>
|
||||
</net>
|
||||
<net code="21" name="SBUS_3V3_PA[08]">
|
||||
<node ref="U1" pin="53"/>
|
||||
@ -1544,32 +1546,33 @@
|
||||
<node ref="JAB1" pin="37"/>
|
||||
</net>
|
||||
<net code="26" name="SBUS_3V3_D[24]">
|
||||
<node ref="JAB1" pin="36"/>
|
||||
<node ref="U2" pin="50"/>
|
||||
<node ref="JAB1" pin="36"/>
|
||||
</net>
|
||||
<net code="27" name="SBUS_3V3_D[23]">
|
||||
<node ref="U2" pin="51"/>
|
||||
<node ref="JAB1" pin="35"/>
|
||||
<node ref="U2" pin="51"/>
|
||||
</net>
|
||||
<net code="28" name="SBUS_3V3_D[22]">
|
||||
<node ref="JAB1" pin="28"/>
|
||||
<node ref="U2" pin="52"/>
|
||||
<node ref="JAB1" pin="28"/>
|
||||
</net>
|
||||
<net code="29" name="SBUS_3V3_D[21]">
|
||||
<node ref="JAB1" pin="27"/>
|
||||
<node ref="U2" pin="53"/>
|
||||
<node ref="JAB1" pin="27"/>
|
||||
</net>
|
||||
<net code="30" name="SBUS_3V3_D[20]">
|
||||
<node ref="JAB1" pin="26"/>
|
||||
<node ref="U2" pin="54"/>
|
||||
<node ref="JAB1" pin="26"/>
|
||||
</net>
|
||||
<net code="31" name="+3V3">
|
||||
<node ref="U2" pin="17"/>
|
||||
<node ref="C31" pin="1"/>
|
||||
<node ref="C1" pin="1"/>
|
||||
<node ref="J2" pin="4"/>
|
||||
<node ref="R31" pin="1"/>
|
||||
<node ref="R30" pin="1"/>
|
||||
<node ref="R31" pin="1"/>
|
||||
<node ref="C31" pin="1"/>
|
||||
<node ref="JCD1" pin="31"/>
|
||||
<node ref="U2" pin="17"/>
|
||||
<node ref="J2" pin="4"/>
|
||||
<node ref="C1" pin="1"/>
|
||||
<node ref="JCD1" pin="36"/>
|
||||
<node ref="C12" pin="1"/>
|
||||
<node ref="JCD1" pin="32"/>
|
||||
@ -1577,7 +1580,6 @@
|
||||
<node ref="U_INT1" pin="5"/>
|
||||
<node ref="JCD1" pin="35"/>
|
||||
<node ref="JAB1" pin="30"/>
|
||||
<node ref="JCD1" pin="31"/>
|
||||
<node ref="JAB1" pin="34"/>
|
||||
<node ref="JAB1" pin="29"/>
|
||||
<node ref="JAB1" pin="33"/>
|
||||
@ -1664,24 +1666,24 @@
|
||||
<node ref="JCD1" pin="54"/>
|
||||
</net>
|
||||
<net code="46" name="SBUS_3V3_PA[19]">
|
||||
<node ref="JCD1" pin="51"/>
|
||||
<node ref="U1" pin="37"/>
|
||||
<node ref="JCD1" pin="51"/>
|
||||
</net>
|
||||
<net code="47" name="SBUS_3V3_PA[18]">
|
||||
<node ref="JCD1" pin="52"/>
|
||||
<node ref="U1" pin="39"/>
|
||||
<node ref="JCD1" pin="52"/>
|
||||
</net>
|
||||
<net code="48" name="SBUS_3V3_PA[17]">
|
||||
<node ref="JCD1" pin="49"/>
|
||||
<node ref="U1" pin="40"/>
|
||||
<node ref="JCD1" pin="49"/>
|
||||
</net>
|
||||
<net code="49" name="SBUS_3V3_ACK[2]*">
|
||||
<node ref="U1" pin="42"/>
|
||||
<node ref="JCD1" pin="45"/>
|
||||
<node ref="U1" pin="42"/>
|
||||
</net>
|
||||
<net code="50" name="SBUS_3V3_PA[15]">
|
||||
<node ref="JCD1" pin="47"/>
|
||||
<node ref="U1" pin="43"/>
|
||||
<node ref="JCD1" pin="47"/>
|
||||
</net>
|
||||
<net code="51" name="SBUS_3V3_PA[14]">
|
||||
<node ref="U1" pin="44"/>
|
||||
@ -1692,12 +1694,12 @@
|
||||
<node ref="JAB1" pin="59"/>
|
||||
</net>
|
||||
<net code="53" name="SBUS_3V3_ACK[1]*">
|
||||
<node ref="JCD1" pin="41"/>
|
||||
<node ref="U1" pin="46"/>
|
||||
<node ref="JCD1" pin="41"/>
|
||||
</net>
|
||||
<net code="54" name="SBUS_3V3_PA[12]">
|
||||
<node ref="U1" pin="47"/>
|
||||
<node ref="JAB1" pin="58"/>
|
||||
<node ref="U1" pin="47"/>
|
||||
</net>
|
||||
<net code="55" name="SBUS_3V3_PA[11]">
|
||||
<node ref="U1" pin="48"/>
|
||||
@ -1716,9 +1718,9 @@
|
||||
<node ref="U1" pin="52"/>
|
||||
</net>
|
||||
<net code="59" name="SBUS_3V3_INT[1]*">
|
||||
<node ref="JCD1" pin="23"/>
|
||||
<node ref="R2" pin="2"/>
|
||||
<node ref="U_INT2" pin="3"/>
|
||||
<node ref="JCD1" pin="23"/>
|
||||
</net>
|
||||
<net code="60" name="SBUS_3V3_INT[2]*">
|
||||
<node ref="R1" pin="2"/>
|
||||
@ -1743,25 +1745,25 @@
|
||||
</net>
|
||||
<net code="65" name="SBUS_3V3_INT[5]*">
|
||||
<node ref="R6" pin="2"/>
|
||||
<node ref="U_INT3" pin="3"/>
|
||||
<node ref="JCD1" pin="43"/>
|
||||
<node ref="U_INT3" pin="3"/>
|
||||
</net>
|
||||
<net code="66" name="SBUS_3V3_INT[6]*">
|
||||
<node ref="U_INT3" pin="1"/>
|
||||
<node ref="JCD1" pin="25"/>
|
||||
<node ref="R5" pin="2"/>
|
||||
<node ref="JAB1" pin="49"/>
|
||||
<node ref="U_INT3" pin="1"/>
|
||||
</net>
|
||||
<net code="67" name="SBUS_3V3_D[03]">
|
||||
<node ref="JAB1" pin="7"/>
|
||||
<node ref="U3" pin="47"/>
|
||||
</net>
|
||||
<net code="68" name="SBUS_3V3_D[13]">
|
||||
<node ref="JAB1" pin="19"/>
|
||||
<node ref="U3" pin="35"/>
|
||||
<node ref="JAB1" pin="19"/>
|
||||
</net>
|
||||
<net code="69" name="SBUS_3V3_D[12]">
|
||||
<node ref="JAB1" pin="18"/>
|
||||
<node ref="U3" pin="36"/>
|
||||
<node ref="JAB1" pin="18"/>
|
||||
</net>
|
||||
<net code="70" name="SBUS_3V3_D[11]">
|
||||
<node ref="U3" pin="37"/>
|
||||
@ -1792,24 +1794,24 @@
|
||||
<node ref="JAB1" pin="10"/>
|
||||
</net>
|
||||
<net code="77" name="SBUS_3V3_D[05]">
|
||||
<node ref="U3" pin="45"/>
|
||||
<node ref="JAB1" pin="9"/>
|
||||
<node ref="U3" pin="45"/>
|
||||
</net>
|
||||
<net code="78" name="SBUS_3V3_D[02]">
|
||||
<node ref="JAB1" pin="8"/>
|
||||
<node ref="U3" pin="46"/>
|
||||
</net>
|
||||
<net code="79" name="SBUS_3V3_D[14]">
|
||||
<node ref="JAB1" pin="20"/>
|
||||
<node ref="U3" pin="34"/>
|
||||
<node ref="JAB1" pin="20"/>
|
||||
</net>
|
||||
<net code="80" name="SBUS_3V3_D[00]">
|
||||
<node ref="JAB1" pin="6"/>
|
||||
<node ref="U3" pin="48"/>
|
||||
</net>
|
||||
<net code="81" name="SBUS_3V3_D[01]">
|
||||
<node ref="U3" pin="50"/>
|
||||
<node ref="JAB1" pin="5"/>
|
||||
<node ref="U3" pin="50"/>
|
||||
</net>
|
||||
<net code="82" name="SBUS_3V3_CLK">
|
||||
<node ref="JAB1" pin="44"/>
|
||||
@ -1820,32 +1822,32 @@
|
||||
<node ref="U3" pin="52"/>
|
||||
</net>
|
||||
<net code="84" name="SBUS_3V3_SEL*">
|
||||
<node ref="JCD1" pin="29"/>
|
||||
<node ref="U3" pin="53"/>
|
||||
<node ref="JCD1" pin="29"/>
|
||||
</net>
|
||||
<net code="85" name="SBUS_3V3_RST*">
|
||||
<node ref="U3" pin="54"/>
|
||||
<node ref="JCD1" pin="27"/>
|
||||
<node ref="U3" pin="54"/>
|
||||
</net>
|
||||
<net code="86" name="SBUS_3V3_D[19]">
|
||||
<node ref="JAB1" pin="25"/>
|
||||
<node ref="U3" pin="29"/>
|
||||
<node ref="JAB1" pin="25"/>
|
||||
</net>
|
||||
<net code="87" name="SBUS_3V3_D[18]">
|
||||
<node ref="JAB1" pin="24"/>
|
||||
<node ref="U3" pin="30"/>
|
||||
<node ref="JAB1" pin="24"/>
|
||||
</net>
|
||||
<net code="88" name="SBUS_3V3_D[17]">
|
||||
<node ref="JAB1" pin="23"/>
|
||||
<node ref="U3" pin="31"/>
|
||||
<node ref="JAB1" pin="23"/>
|
||||
</net>
|
||||
<net code="89" name="SBUS_3V3_D[16]">
|
||||
<node ref="JAB1" pin="22"/>
|
||||
<node ref="U3" pin="32"/>
|
||||
<node ref="JAB1" pin="22"/>
|
||||
</net>
|
||||
<net code="90" name="SBUS_3V3_D[15]">
|
||||
<node ref="JAB1" pin="21"/>
|
||||
<node ref="U3" pin="33"/>
|
||||
<node ref="JAB1" pin="21"/>
|
||||
</net>
|
||||
<net code="91" name="SBUS_3V3_BR*">
|
||||
<node ref="U4" pin="3"/>
|
||||
@ -1868,8 +1870,8 @@
|
||||
<node ref="U2" pin="25"/>
|
||||
</net>
|
||||
<net code="96" name="SBUS_5V_EER*">
|
||||
<node ref="SBus1" pin="32"/>
|
||||
<node ref="U1" pin="2"/>
|
||||
<node ref="SBus1" pin="32"/>
|
||||
</net>
|
||||
<net code="97" name="SBUS_5V_PA[06]">
|
||||
<node ref="SBus1" pin="33"/>
|
||||
@ -1884,8 +1886,8 @@
|
||||
<node ref="SBus1" pin="35"/>
|
||||
</net>
|
||||
<net code="100" name="SBUS_5V_ACK[0]*">
|
||||
<node ref="SBus1" pin="36"/>
|
||||
<node ref="U1" pin="5"/>
|
||||
<node ref="SBus1" pin="36"/>
|
||||
</net>
|
||||
<net code="101" name="SBUS_5V_PA[12]">
|
||||
<node ref="SBus1" pin="37"/>
|
||||
@ -1900,16 +1902,16 @@
|
||||
<node ref="SBus1" pin="39"/>
|
||||
</net>
|
||||
<net code="104" name="SBUS_5V_ACK[1]*">
|
||||
<node ref="U1" pin="10"/>
|
||||
<node ref="SBus1" pin="40"/>
|
||||
<node ref="U1" pin="10"/>
|
||||
</net>
|
||||
<net code="105" name="SBUS_5V_PA[18]">
|
||||
<node ref="U1" pin="18"/>
|
||||
<node ref="SBus1" pin="41"/>
|
||||
</net>
|
||||
<net code="106" name="SBUS_5V_PA[00]">
|
||||
<node ref="SBus1" pin="29"/>
|
||||
<node ref="U2" pin="21"/>
|
||||
<node ref="SBus1" pin="29"/>
|
||||
</net>
|
||||
<net code="107" name="SBUS_5V_PA[22]">
|
||||
<node ref="SBus1" pin="43"/>
|
||||
@ -1924,8 +1926,8 @@
|
||||
<node ref="U1" pin="25"/>
|
||||
</net>
|
||||
<net code="110" name="SBUS_5V_PA[26]">
|
||||
<node ref="U1" pin="28"/>
|
||||
<node ref="SBus1" pin="46"/>
|
||||
<node ref="U1" pin="28"/>
|
||||
</net>
|
||||
<net code="111" name="SBUS_5V_DP">
|
||||
<node ref="SBus1" pin="47"/>
|
||||
@ -1946,8 +1948,8 @@
|
||||
<node ref="SBus1" pin="51"/>
|
||||
</net>
|
||||
<net code="116" name="SBUS_5V_D[01]">
|
||||
<node ref="SBus1" pin="53"/>
|
||||
<node ref="U3" pin="6"/>
|
||||
<node ref="SBus1" pin="53"/>
|
||||
</net>
|
||||
<net code="117" name="SBUS_5V_D[19]">
|
||||
<node ref="U3" pin="28"/>
|
||||
@ -1958,20 +1960,20 @@
|
||||
<node ref="SBus1" pin="05"/>
|
||||
</net>
|
||||
<net code="119" name="SBUS_5V_D[02]">
|
||||
<node ref="SBus1" pin="06"/>
|
||||
<node ref="U3" pin="10"/>
|
||||
<node ref="SBus1" pin="06"/>
|
||||
</net>
|
||||
<net code="120" name="SBUS_5V_D[04]">
|
||||
<node ref="SBus1" pin="07"/>
|
||||
<node ref="U3" pin="12"/>
|
||||
<node ref="SBus1" pin="07"/>
|
||||
</net>
|
||||
<net code="121" name="SBUS_5V_D[06]">
|
||||
<node ref="U3" pin="13"/>
|
||||
<node ref="SBus1" pin="09"/>
|
||||
<node ref="U3" pin="13"/>
|
||||
</net>
|
||||
<net code="122" name="SBUS_5V_D[08]">
|
||||
<node ref="U3" pin="15"/>
|
||||
<node ref="SBus1" pin="10"/>
|
||||
<node ref="U3" pin="15"/>
|
||||
</net>
|
||||
<net code="123" name="SBUS_5V_D[10]">
|
||||
<node ref="U3" pin="18"/>
|
||||
|
||||
Binary file not shown.
@ -981,6 +981,8 @@ F 1 "SN74CB3T16211DGGR" H 10350 2481 60 0000 C CNN
|
||||
F 2 "For_SeeedStudio:TSSOP-56_6.1x14mm_P0.5mm_For_SeeedStudio" H 10350 2440 60 0001 C CNN
|
||||
F 3 "" H 9550 2200 60 0000 C CNN
|
||||
F 4 "SN74CB3T16211DGGR" H 9550 2200 50 0001 C CNN "MPN"
|
||||
F 5 "https://www.mouser.fr/ProductDetail/Texas-Instruments/SN74CB3T16211DGGR?qs=%2Fha2pyFadujLgV8PJqueL5aUGpX9%252BbECTuUAq6EU8VAiPml4qcD9lw%3D%3D" H 9550 2200 50 0001 C CNN "URL-alt"
|
||||
F 6 "https://lcsc.com/product-detail/Signal-Switches-Encoders-Decoders-Multiplexers_Texas-Instruments-SN74CB3T16211DGGR_C2653275.html" H 9550 2200 50 0001 C CNN "URL"
|
||||
1 9550 2200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
|
||||
Binary file not shown.
Loading…
x
Reference in New Issue
Block a user