github.com/rdolbeau.SBusFPGA
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add an SBus statistics module (and discover a bug in the sbus lave timeouts and a lot of slave re-run)

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This commit is contained in:
Romain Dolbeau
2021-08-21 07:41:02 -04:00
parent 67ad40c65e
commit 2111020a0c
9 changed files with 237 additions and 16 deletions
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2
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_curve25519engine.c
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@@ -596,6 +596,7 @@ sbusfpga_curve25519engine_attach(device_t parent, device_t self, void *aux)
//#define CSR_CURVE25519ENGINE_BASE
#define CSR_DDRPHY_BASE
#define CSR_EXCHANGE_WITH_MEM_BASE
#define CSR_SBUS_BUS_STAT_BASE
#define CSR_SDRAM_BASE
#define CSR_SDBLOCK2MEM_BASE
#define CSR_SDCORE_BASE
@@ -608,6 +609,7 @@ sbusfpga_curve25519engine_attach(device_t parent, device_t self, void *aux)
//#undef CSR_CURVE25519ENGINE_BASE
#undef CSR_DDRPHY_BASE
#undef CSR_EXCHANGE_WITH_MEM_BASE
#undef CSR_SBUS_BUS_STAT_BASE
#undef CSR_SDRAM_BASE
#undef CSR_SDBLOCK2MEM_BASE
#undef CSR_SDCORE_BASE

2
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c
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@@ -547,6 +547,7 @@ sbusfpga_sdram_diskstart(device_t self, struct buf *bp)
//#define CSR_DDRPHY_BASE
//#define CSR_SDRAM_BASE
//#define CSR_EXCHANGE_WITH_MEM_BASE
#define CSR_SBUS_BUS_STAT_BASE
#define CSR_SDBLOCK2MEM_BASE
#define CSR_SDCORE_BASE
#define CSR_SDIRQ_BASE
@@ -564,6 +565,7 @@ sbusfpga_sdram_diskstart(device_t self, struct buf *bp)
//#undef CSR_DDRPHY_BASE
//#undef CSR_SDRAM_BASE
//#undef CSR_EXCHANGE_WITH_MEM_BASE
#undef CSR_SBUS_BUS_STAT_BASE
#undef CSR_SDBLOCK2MEM_BASE
#undef CSR_SDCORE_BASE
#undef CSR_SDIRQ_BASE

6
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_trng.c
View File

@@ -112,6 +112,7 @@ sbusfpga_trng_match(device_t parent, cfdata_t cf, void *aux)
#define CSR_CURVE25519ENGINE_BASE
#define CSR_DDRPHY_BASE
#define CSR_EXCHANGE_WITH_MEM_BASE
#define CSR_SBUS_BUS_STAT_BASE
#define CSR_SDRAM_BASE
#define CSR_SDBLOCK2MEM_BASE
#define CSR_SDCORE_BASE
@@ -124,6 +125,7 @@ sbusfpga_trng_match(device_t parent, cfdata_t cf, void *aux)
#undef CSR_CURVE25519ENGINE_BASE
#undef CSR_DDRPHY_BASE
#undef CSR_EXCHANGE_WITH_MEM_BASE
#undef CSR_SBUS_BUS_STAT_BASE
#undef CSR_SDRAM_BASE
#undef CSR_SDBLOCK2MEM_BASE
#undef CSR_SDCORE_BASE
@@ -145,7 +147,7 @@ sbusfpga_trng_getentropy(size_t nbytes, void *cookie) {
} else {
failure ++;
if (failure > (1+(dbytes/4))) { // something going on
aprint_normal_dev(sc->sc_dev, "out of entropy after %zd / %zd bytes\n", dbytes, nbytes);
device_printf(sc->sc_dev, "out of entropy after %zd / %zd bytes\n", dbytes, nbytes);
return;
}
delay(1);
@@ -153,7 +155,7 @@ sbusfpga_trng_getentropy(size_t nbytes, void *cookie) {
if (((dbytes%32)==0) && (nbytes > dbytes))
delay(1); // let the hardware breathes if the OS needs a lof of bytes
}
aprint_normal_dev(sc->sc_dev, "gathered %zd bytes [%d]\n", dbytes, failure);
device_printf(sc->sc_dev, "gathered %zd bytes [%d]\n", dbytes, failure);
}
/*