commit patch for newer Litex

2026-01-11 23:42:59 +00:00 · 2022-11-04 09:52:03 +01:00 · 2022-11-04 09:52:03 +01:00 · 260f513e2c
commit 260f513e2c
parent a25adb4ed7
2 changed files with 2 additions and 1 deletions
--- a/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common
+++ b/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common
@ -1 +1 @@
-Subproject commit c7d117677ecd10b4990ccf42187265c53a46c1e2
+Subproject commit 342358535e10c4efc1660a442aba68c79ae7d166
--- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
+++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
@ -262,6 +262,7 @@ class SBusFPGA(SoCCore):
                         sys_clk_freq=sys_clk_freq,
                         clk_freq=sys_clk_freq,
                         csr_paging=0x1000, #  default is 0x800
+                         bus_interconnect = "crossbar",
                         **kwargs)

        # *** This mem-map is also exposed in the FSM (matched prefixes) ***