commit patch for newer Litex

2026-03-09 03:49:24 +00:00 · 2022-11-04 09:52:03 +01:00
parent a25adb4ed7
commit 260f513e2c
2 changed files with 2 additions and 1 deletions
--- a/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common
+++ b/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common
--- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
+++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
@@ -262,6 +262,7 @@ class SBusFPGA(SoCCore):
                         sys_clk_freq=sys_clk_freq,
                         clk_freq=sys_clk_freq,
                         csr_paging=0x1000, #  default is 0x800
+                         bus_interconnect = "crossbar",
                         **kwargs)

        # *** This mem-map is also exposed in the FSM (matched prefixes) ***