github.com/rdolbeau.SBusFPGA
1
0
Fork 0
mirror of synced 2026-03-10 04:11:01 +00:00
Code Issues Projects Releases Wiki Activity

cleanup, preliminary sdcard driver

Browse Source
This commit is contained in:
Romain Dolbeau
2021-11-13 12:40:34 +01:00
parent 893e5a7c67
commit 334759951b
4 changed files with 1531 additions and 240 deletions
Download Patch File Download Diff File Expand all files Collapse all files

213
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_csr_common.h Normal file
View File

@@ -0,0 +1,213 @@
#ifndef __SBUSFPGA_CSR_COMMON_H__
#define __SBUSFPGA_CSR_COMMON_H__
/* from hw/common.h, +sc */
/* CSR data width (subreg. width) in bytes, for direct comparson to sizeof() */
#define CSR_DW_BYTES (CONFIG_CSR_DATA_WIDTH/8)
#define CSR_OFFSET_BYTES 4
/* Number of subregs required for various total byte sizes, by subreg width:
* NOTE: 1, 2, 4, and 8 bytes represent uint[8|16|32|64]_t C types; However,
* CSRs of intermediate byte sizes (24, 40, 48, and 56) are NOT padded
* (with extra unallocated subregisters) to the next valid C type!
* +-----+-----------------+
* | csr | bytes |
* | _dw | 1 2 3 4 5 6 7 8 |
* | |-----=---=-=-=---|
* | 1 | 1 2 3 4 5 6 7 8 |
* | 2 | 1 1 2 2 3 3 4 4 |
* | 4 | 1 1 1 1 2 2 2 2 |
* | 8 | 1 1 1 1 1 1 1 1 |
* +-----+-----------------+ */
static inline int num_subregs(int csr_bytes)
{
return (csr_bytes - 1) / CSR_DW_BYTES + 1;
}
/* Read a CSR of size 'csr_bytes' located at address 'a'. */
static inline uint64_t _csr_rd(struct sbusfpga_common_softc *sc, unsigned long a, int csr_bytes)
{
uint64_t r = bus_space_read_4(sc->sc_bustag, 0, a);
for (int i = 1; i < num_subregs(csr_bytes); i++) {
r <<= CONFIG_CSR_DATA_WIDTH;
a += CSR_OFFSET_BYTES;
r |= bus_space_read_4(sc->sc_bustag, 0, a);
}
return r;
}
/* Write value 'v' to a CSR of size 'csr_bytes' located at address 'a'. */
static inline void _csr_wr(struct sbusfpga_common_softc *sc, unsigned long a, uint64_t v, int csr_bytes)
{
int ns = num_subregs(csr_bytes);
for (int i = 0; i < ns; i++) {
bus_space_write_4(sc->sc_bustag, 0, a , v >> (CONFIG_CSR_DATA_WIDTH * (ns - 1 - i)));
a += CSR_OFFSET_BYTES;
}
}
// FIXME: - should we provide 24, 40, 48, and 56 bit csr_[rd|wr] methods?
static inline uint8_t csr_rd_uint8(struct sbusfpga_common_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint8_t));
}
static inline void csr_wr_uint8(struct sbusfpga_common_softc *sc, uint8_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint8_t));
}
static inline uint16_t csr_rd_uint16(struct sbusfpga_common_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint16_t));
}
static inline void csr_wr_uint16(struct sbusfpga_common_softc *sc, uint16_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint16_t));
}
static inline uint32_t csr_rd_uint32(struct sbusfpga_common_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint32_t));
}
static inline void csr_wr_uint32(struct sbusfpga_common_softc *sc, uint32_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint32_t));
}
static inline uint64_t csr_rd_uint64(struct sbusfpga_common_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint64_t));
}
static inline void csr_wr_uint64(struct sbusfpga_common_softc *sc, uint64_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint64_t));
}
/* Read a CSR located at address 'a' into an array 'buf' of 'cnt' elements.
*
* NOTE: Since CSR_DW_BYTES is a constant here, we might be tempted to further
* optimize things by leaving out one or the other of the if() branches below,
* depending on each unsigned type width;
* However, this code is also meant to serve as a reference for how CSRs are
* to be manipulated by other programs (e.g., an OS kernel), which may benefit
* from dynamically handling multiple possible CSR subregister data widths
* (e.g., by passing a value in through the Device Tree).
* Ultimately, if CSR_DW_BYTES is indeed a constant, the compiler should be
* able to determine on its own whether it can automatically optimize away one
* of the if() branches! */
#define _csr_rd_buf(sc, a, buf, cnt) \
{ \
int i, j, nsubs, n_sub_elem; \
uint64_t r; \
if (sizeof(buf[0]) >= CSR_DW_BYTES) { \
/* one or more subregisters per element */ \
for (i = 0; i < cnt; i++) { \
buf[i] = _csr_rd(sc, a, sizeof(buf[0])); \
a += CSR_OFFSET_BYTES * num_subregs(sizeof(buf[0])); \
} \
} else { \
/* multiple elements per subregister (2, 4, or 8) */ \
nsubs = num_subregs(sizeof(buf[0]) * cnt); \
n_sub_elem = CSR_DW_BYTES / sizeof(buf[0]); \
for (i = 0; i < nsubs; i++) { \
r = bus_space_read_4(sc->sc_bustag, 0, a); \
for (j = n_sub_elem - 1; j >= 0; j--) { \
if (i * n_sub_elem + j < cnt) \
buf[i * n_sub_elem + j] = r; \
r >>= sizeof(buf[0]) * 8; \
} \
a += CSR_OFFSET_BYTES; \
} \
} \
}
/* Write an array 'buf' of 'cnt' elements to a CSR located at address 'a'.
*
* NOTE: The same optimization considerations apply here as with _csr_rd_buf()
* above.
*/
#define _csr_wr_buf(sc, a, buf, cnt) \
{ \
int i, j, nsubs, n_sub_elem; \
uint64_t v; \
if (sizeof(buf[0]) >= CSR_DW_BYTES) { \
/* one or more subregisters per element */ \
for (i = 0; i < cnt; i++) { \
_csr_wr(sc, a, buf[i], sizeof(buf[0])); \
a += CSR_OFFSET_BYTES * num_subregs(sizeof(buf[0])); \
} \
} else { \
/* multiple elements per subregister (2, 4, or 8) */ \
nsubs = num_subregs(sizeof(buf[0]) * cnt); \
n_sub_elem = CSR_DW_BYTES / sizeof(buf[0]); \
for (i = 0; i < nsubs; i++) { \
v = buf[i * n_sub_elem + 0]; \
for (j = 1; j < n_sub_elem; j++) { \
if (i * n_sub_elem + j == cnt) \
break; \
v <<= sizeof(buf[0]) * 8; \
v |= buf[i * n_sub_elem + j]; \
} \
bus_space_write_4(sc->sc_bustag, 0, a, v); \
a += CSR_OFFSET_BYTES; \
} \
} \
}
static inline void csr_rd_buf_uint8(struct sbusfpga_common_softc *sc, unsigned long a, uint8_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint8(struct sbusfpga_common_softc *sc, unsigned long a,
const uint8_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
static inline void csr_rd_buf_uint16(struct sbusfpga_common_softc *sc, unsigned long a, uint16_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint16(struct sbusfpga_common_softc *sc, unsigned long a,
const uint16_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
static inline void csr_rd_buf_uint32(struct sbusfpga_common_softc *sc, unsigned long a, uint32_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint32(struct sbusfpga_common_softc *sc, unsigned long a,
const uint32_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
/* NOTE: the macros' "else" branch is unreachable, no need to be warned
* about a >= 64bit left shift! */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wshift-count-overflow"
static inline void csr_rd_buf_uint64(struct sbusfpga_common_softc *sc, unsigned long a, uint64_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint64(struct sbusfpga_common_softc *sc, unsigned long a,
const uint64_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
#pragma GCC diagnostic pop
#endif // __SBUSFPGA_CSR_COMMON_H__

1250
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdcard.c Normal file
View File

File diff suppressed because it is too large Load Diff

65
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdcard.h Normal file
View File

@@ -0,0 +1,65 @@
/* $NetBSD$ */
/*-
* Copyright (c) 2020 Romain Dolbeau <romain@dolbeau.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SBUSFPGA_SDCARD_H_
#define _SBUSFPGA_SDCARD_H_
struct sbusfpga_sd_softc {
struct dk_softc dk;
//device_t sc_dev; /* us as a device */
u_int sc_rev; /* revision */
int sc_node; /* PROM node ID */
int sc_burst; /* DVMA burst size in effect */
bus_space_tag_t sc_bustag; /* bus tag */
bus_space_handle_t sc_bhregs_sdcore; /* bus handle */
bus_space_handle_t sc_bhregs_sdirq; /* bus handle */
bus_space_handle_t sc_bhregs_sdphy; /* bus handle */
bus_space_handle_t sc_bhregs_sdblock2mem; /* bus handle */
bus_space_handle_t sc_bhregs_sdmem2block; /* bus handle */
int sc_bufsiz_sdcore; /* Size of buffer */
int sc_bufsiz_sdirq; /* Size of buffer */
int sc_bufsiz_sdphy; /* Size of buffer */
int sc_bufsiz_sdblock2mem; /* bus handle */
int sc_bufsiz_sdmem2block; /* bus handle */
/* card details */
u_int max_rd_blk_len;
u_int max_size_in_blk;
u_int init_done;
/* DMA kernel structures */
bus_dma_tag_t sc_dmatag;
bus_dmamap_t sc_dmamap;
bus_dma_segment_t sc_segs;
int sc_rsegs;
void * sc_dma_kva;
device_t sc_sdmmc_dev; /* us as a sdmmc bus device */
};
#define SBUSFPGA_SD_VAL_DMA_MAX_SZ (64*1024)
#endif /* _SBUSFPGA_SDCARD_H_ */

243
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c
View File

@@ -348,39 +348,7 @@ sbusfpga_sdram_attach(device_t parent, device_t self, void *aux)
disk_attach(&sc->dk.sc_dkdev);
sbusfpga_sdram_set_geometry(sc);
bufq_alloc(&sc->dk.sc_bufq, BUFQ_DISK_DEFAULT_STRAT, BUFQ_SORT_RAWBLOCK); /* needed ? */
if (0) {
struct disklabel *lp = sc->dk.sc_dkdev.dk_label;
struct cpu_disklabel *clp = sc->dk.sc_dkdev.dk_cpulabel;
memset(lp, 0, sizeof(struct disklabel));
memset(clp, 0, sizeof(struct cpu_disklabel));
lp->d_type = DKTYPE_FLASH;
lp->d_secsize = 512;
lp->d_nsectors = 4;
lp->d_ntracks = 2;
lp->d_ncylinders = sc->dma_real_mem_size / (lp->d_secsize * lp->d_nsectors * lp->d_ntracks);
lp->d_secpercyl = lp->d_ntracks * lp->d_nsectors;
lp->d_secperunit = lp->d_secpercyl * lp->d_ncylinders;
lp->d_rpm = 3600;
strncpy(lp->d_typename, "sdramdisk", sizeof(lp->d_typename));
strncpy(lp->d_packname, "fictitious", sizeof(lp->d_packname));
lp->d_interleave = 0;
lp->d_partitions[0].p_offset = lp->d_secpercyl * lp->d_secsize;
lp->d_partitions[0].p_size = lp->d_secpercyl * (lp->d_ncylinders - 1);
lp->d_partitions[0].p_fstype = FS_SWAP;
lp->d_partitions[RAW_PART].p_offset = 0;
lp->d_partitions[RAW_PART].p_size = lp->d_secpercyl * lp->d_ncylinders;
lp->d_partitions[RAW_PART].p_fstype = FS_UNUSED;
lp->d_npartitions = RAW_PART + 1;
lp->d_magic = DISKMAGIC;
lp->d_magic2 = DISKMAGIC;
lp->d_checksum = dkcksum(lp);
}
bufq_alloc(&sc->dk.sc_bufq, BUFQ_DISK_DEFAULT_STRAT, BUFQ_SORT_RAWBLOCK);
/*
// initialize some blocks were the FB lives to test the output
@@ -1130,213 +1098,8 @@ static inline void init_sequence(struct sbusfpga_sdram_softc *sc)
cdelay(200);
}
/* from hw/common.h, +sc */
/* CSR data width (subreg. width) in bytes, for direct comparson to sizeof() */
#define CSR_DW_BYTES (CONFIG_CSR_DATA_WIDTH/8)
#define CSR_OFFSET_BYTES 4
/* Number of subregs required for various total byte sizes, by subreg width:
* NOTE: 1, 2, 4, and 8 bytes represent uint[8|16|32|64]_t C types; However,
* CSRs of intermediate byte sizes (24, 40, 48, and 56) are NOT padded
* (with extra unallocated subregisters) to the next valid C type!
* +-----+-----------------+
* | csr | bytes |
* | _dw | 1 2 3 4 5 6 7 8 |
* | |-----=---=-=-=---|
* | 1 | 1 2 3 4 5 6 7 8 |
* | 2 | 1 1 2 2 3 3 4 4 |
* | 4 | 1 1 1 1 2 2 2 2 |
* | 8 | 1 1 1 1 1 1 1 1 |
* +-----+-----------------+ */
static inline int num_subregs(int csr_bytes)
{
return (csr_bytes - 1) / CSR_DW_BYTES + 1;
}
/* Read a CSR of size 'csr_bytes' located at address 'a'. */
static inline uint64_t _csr_rd(struct sbusfpga_sdram_softc *sc, unsigned long a, int csr_bytes)
{
uint64_t r = bus_space_read_4(sc->sc_bustag, 0, a);
for (int i = 1; i < num_subregs(csr_bytes); i++) {
r <<= CONFIG_CSR_DATA_WIDTH;
a += CSR_OFFSET_BYTES;
r |= bus_space_read_4(sc->sc_bustag, 0, a);
}
return r;
}
/* Write value 'v' to a CSR of size 'csr_bytes' located at address 'a'. */
static inline void _csr_wr(struct sbusfpga_sdram_softc *sc, unsigned long a, uint64_t v, int csr_bytes)
{
int ns = num_subregs(csr_bytes);
for (int i = 0; i < ns; i++) {
bus_space_write_4(sc->sc_bustag, 0, a , v >> (CONFIG_CSR_DATA_WIDTH * (ns - 1 - i)));
a += CSR_OFFSET_BYTES;
}
}
// FIXME: - should we provide 24, 40, 48, and 56 bit csr_[rd|wr] methods?
static inline uint8_t csr_rd_uint8(struct sbusfpga_sdram_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint8_t));
}
static inline void csr_wr_uint8(struct sbusfpga_sdram_softc *sc, uint8_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint8_t));
}
static inline uint16_t csr_rd_uint16(struct sbusfpga_sdram_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint16_t));
}
static inline void csr_wr_uint16(struct sbusfpga_sdram_softc *sc, uint16_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint16_t));
}
static inline uint32_t csr_rd_uint32(struct sbusfpga_sdram_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint32_t));
}
static inline void csr_wr_uint32(struct sbusfpga_sdram_softc *sc, uint32_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint32_t));
}
static inline uint64_t csr_rd_uint64(struct sbusfpga_sdram_softc *sc, unsigned long a)
{
return _csr_rd(sc, a, sizeof(uint64_t));
}
static inline void csr_wr_uint64(struct sbusfpga_sdram_softc *sc, uint64_t v, unsigned long a)
{
_csr_wr(sc, a, v, sizeof(uint64_t));
}
/* Read a CSR located at address 'a' into an array 'buf' of 'cnt' elements.
*
* NOTE: Since CSR_DW_BYTES is a constant here, we might be tempted to further
* optimize things by leaving out one or the other of the if() branches below,
* depending on each unsigned type width;
* However, this code is also meant to serve as a reference for how CSRs are
* to be manipulated by other programs (e.g., an OS kernel), which may benefit
* from dynamically handling multiple possible CSR subregister data widths
* (e.g., by passing a value in through the Device Tree).
* Ultimately, if CSR_DW_BYTES is indeed a constant, the compiler should be
* able to determine on its own whether it can automatically optimize away one
* of the if() branches! */
#define _csr_rd_buf(sc, a, buf, cnt) \
{ \
int i, j, nsubs, n_sub_elem; \
uint64_t r; \
if (sizeof(buf[0]) >= CSR_DW_BYTES) { \
/* one or more subregisters per element */ \
for (i = 0; i < cnt; i++) { \
buf[i] = _csr_rd(sc, a, sizeof(buf[0])); \
a += CSR_OFFSET_BYTES * num_subregs(sizeof(buf[0])); \
} \
} else { \
/* multiple elements per subregister (2, 4, or 8) */ \
nsubs = num_subregs(sizeof(buf[0]) * cnt); \
n_sub_elem = CSR_DW_BYTES / sizeof(buf[0]); \
for (i = 0; i < nsubs; i++) { \
r = bus_space_read_4(sc->sc_bustag, 0, a); \
for (j = n_sub_elem - 1; j >= 0; j--) { \
if (i * n_sub_elem + j < cnt) \
buf[i * n_sub_elem + j] = r; \
r >>= sizeof(buf[0]) * 8; \
} \
a += CSR_OFFSET_BYTES; \
} \
} \
}
/* Write an array 'buf' of 'cnt' elements to a CSR located at address 'a'.
*
* NOTE: The same optimization considerations apply here as with _csr_rd_buf()
* above.
*/
#define _csr_wr_buf(sc, a, buf, cnt) \
{ \
int i, j, nsubs, n_sub_elem; \
uint64_t v; \
if (sizeof(buf[0]) >= CSR_DW_BYTES) { \
/* one or more subregisters per element */ \
for (i = 0; i < cnt; i++) { \
_csr_wr(sc, a, buf[i], sizeof(buf[0])); \
a += CSR_OFFSET_BYTES * num_subregs(sizeof(buf[0])); \
} \
} else { \
/* multiple elements per subregister (2, 4, or 8) */ \
nsubs = num_subregs(sizeof(buf[0]) * cnt); \
n_sub_elem = CSR_DW_BYTES / sizeof(buf[0]); \
for (i = 0; i < nsubs; i++) { \
v = buf[i * n_sub_elem + 0]; \
for (j = 1; j < n_sub_elem; j++) { \
if (i * n_sub_elem + j == cnt) \
break; \
v <<= sizeof(buf[0]) * 8; \
v |= buf[i * n_sub_elem + j]; \
} \
bus_space_write_4(sc->sc_bustag, 0, a, v); \
a += CSR_OFFSET_BYTES; \
} \
} \
}
static inline void csr_rd_buf_uint8(struct sbusfpga_sdram_softc *sc, unsigned long a, uint8_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint8(struct sbusfpga_sdram_softc *sc, unsigned long a,
const uint8_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
static inline void csr_rd_buf_uint16(struct sbusfpga_sdram_softc *sc, unsigned long a, uint16_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint16(struct sbusfpga_sdram_softc *sc, unsigned long a,
const uint16_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
static inline void csr_rd_buf_uint32(struct sbusfpga_sdram_softc *sc, unsigned long a, uint32_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint32(struct sbusfpga_sdram_softc *sc, unsigned long a,
const uint32_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
/* NOTE: the macros' "else" branch is unreachable, no need to be warned
* about a >= 64bit left shift! */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wshift-count-overflow"
static inline void csr_rd_buf_uint64(struct sbusfpga_sdram_softc *sc, unsigned long a, uint64_t *buf, int cnt)
{
_csr_rd_buf(sc, a, buf, cnt);
}
static inline void csr_wr_buf_uint64(struct sbusfpga_sdram_softc *sc, unsigned long a,
const uint64_t *buf, int cnt)
{
_csr_wr_buf(sc, a, buf, cnt);
}
#pragma GCC diagnostic pop
#define sbusfpga_common_softc sbusfpga_sdram_softc
#include "dev/sbus/sbusfpga_csr_common.h"
/* sdram.c from liblitedram, preprocessed for our case, + sc */