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cleaning up some stuff, disable USB Host for testing SDRAM disk

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This commit is contained in:
Romain Dolbeau
2021-07-18 10:19:53 -04:00
parent 023e84b734
commit 38e3431c7f
6 changed files with 85 additions and 46 deletions
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20
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c
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@@ -350,7 +350,7 @@ sbusfpga_sdram_attach(device_t parent, device_t self, void *aux)
lp->d_secsize = 512;
lp->d_nsectors = 4;
lp->d_ntracks = 2;
lp->d_ncylinders = 65536;
lp->d_ncylinders = sc->dma_real_mem_size / (lp->d_secsize * lp->d_nsectors * lp->d_ntracks);
lp->d_secpercyl = lp->d_ntracks * lp->d_nsectors;
lp->d_secperunit = lp->d_secpercyl * lp->d_ncylinders;
lp->d_rpm = 3600;
@@ -398,10 +398,10 @@ static void sbusfpga_sdram_set_geometry(struct sbusfpga_sdram_softc *sc) {
dg->dg_secsize = 512;
dg->dg_nsectors = 2;
dg->dg_ntracks = 4;
dg->dg_ncylinders = 65536;
dg->dg_ncylinders = sc->dma_real_mem_size / (dg->dg_secsize * dg->dg_nsectors * dg->dg_ntracks);
dg->dg_secpercyl = dg->dg_nsectors * dg->dg_ntracks;
dg->dg_secperunit = dg->dg_secpercyl * dg->dg_ncylinders;
dg->dg_pcylinders = 65536;
dg->dg_pcylinders = dg->dg_ncylinders;
dg->dg_sparespertrack = 0;
dg->dg_sparespercyl = 0;
@@ -411,7 +411,8 @@ static void sbusfpga_sdram_set_geometry(struct sbusfpga_sdram_softc *sc) {
int
sbusfpga_sdram_size(dev_t dev) {
return 524288;
struct sbusfpga_sdram_softc *sc = device_lookup_private(&sbusfpga_sdram_cd, DISKUNIT(dev));
return sc->dma_real_mem_size / 512;
}
static void
@@ -466,7 +467,7 @@ sbusfpga_sdram_diskstart(device_t self, struct buf *bp)
if (blkcnt > (SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ/512))
blkcnt = (SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ/512);
if (blk+blkcnt <= 524288) {
if (blk+blkcnt <= (sc->dma_real_mem_size / 512)) {
err = sbusfpga_sdram_read_block(sc, blk, blkcnt, data);
} else {
aprint_error("%s:%d: blk = %lld read out of range! giving up\n", __PRETTY_FUNCTION__, __LINE__, blk);
@@ -502,7 +503,7 @@ sbusfpga_sdram_diskstart(device_t self, struct buf *bp)
if (blkcnt > (SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ/512))
blkcnt = (SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ/512);
if (blk+blkcnt <= 524288) {
if (blk+blkcnt <= (sc->dma_real_mem_size / 512)) {
err = sbusfpga_sdram_write_block(sc, blk, blkcnt, data);
} else {
aprint_error("%s:%d: blk = %lld write out of range! giving up\n", __PRETTY_FUNCTION__, __LINE__, blk);
@@ -543,7 +544,12 @@ int
dma_init(struct sbusfpga_sdram_softc *sc) {
sc->dma_blk_size = exchange_with_mem_blk_size_read(sc);
sc->dma_blk_base = exchange_with_mem_blk_base_read(sc);
aprint_normal_dev(sc->dk.sc_dev, "DMA: HW -> block size is %d, base address is 0x%08x\n", sc->dma_blk_size, sc->dma_blk_base * sc->dma_blk_size);
sc->dma_mem_size = exchange_with_mem_mem_size_read(sc);
sc->dma_real_mem_size = sc->dma_mem_size * sc->dma_blk_size;
aprint_normal_dev(sc->dk.sc_dev, "DMA: HW -> block size is %d, base address is 0x%08x (%d MiB)\n",
sc->dma_blk_size,
sc->dma_blk_base * sc->dma_blk_size,
sc->dma_real_mem_size / 1048576);
/* Allocate a dmamap */
if (bus_dmamap_create(sc->sc_dmatag, SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ, 1, SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_dmamap) != 0) {

4
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.h
View File

@@ -47,6 +47,8 @@ struct sbusfpga_sdram_softc {
/* specific of the DMA engine */
u_int dma_blk_size;
u_int dma_blk_base;
u_int dma_mem_size; /* in blk_size */
u_int dma_real_mem_size; /* precomputed in bytes */
/* DMA kernel structures */
bus_dma_tag_t sc_dmatag;
bus_dmamap_t sc_dmamap;
@@ -55,6 +57,6 @@ struct sbusfpga_sdram_softc {
void * sc_dma_kva;
};
#define SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ (4*1024)
#define SBUSFPGA_SDRAM_VAL_DMA_MAX_SZ (64*1024)
#endif /* _SBUSFPGA_SDRAM_H_ */

63
sbus-to-ztex-gateware-migen/netbsd_csr.h
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@@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-07-18 04:58:11
// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-07-18 09:29:51
//--------------------------------------------------------------------------------
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
@@ -142,54 +142,59 @@ static inline uint32_t exchange_with_mem_blk_size_read(struct sbusfpga_sdram_sof
static inline uint32_t exchange_with_mem_blk_base_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x4L);
}
#define CSR_EXCHANGE_WITH_MEM_BLK_ADDR_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x8L)
#define CSR_EXCHANGE_WITH_MEM_BLK_ADDR_SIZE 1
static inline uint32_t exchange_with_mem_blk_addr_read(struct sbusfpga_sdram_softc *sc) {
#define CSR_EXCHANGE_WITH_MEM_MEM_SIZE_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x8L)
#define CSR_EXCHANGE_WITH_MEM_MEM_SIZE_SIZE 1
static inline uint32_t exchange_with_mem_mem_size_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x8L);
}
static inline void exchange_with_mem_blk_addr_write(struct sbusfpga_sdram_softc *sc, uint32_t v) {
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x8L, v);
}
#define CSR_EXCHANGE_WITH_MEM_DMA_ADDR_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0xcL)
#define CSR_EXCHANGE_WITH_MEM_DMA_ADDR_SIZE 1
static inline uint32_t exchange_with_mem_dma_addr_read(struct sbusfpga_sdram_softc *sc) {
#define CSR_EXCHANGE_WITH_MEM_BLK_ADDR_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0xcL)
#define CSR_EXCHANGE_WITH_MEM_BLK_ADDR_SIZE 1
static inline uint32_t exchange_with_mem_blk_addr_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0xcL);
}
static inline void exchange_with_mem_dma_addr_write(struct sbusfpga_sdram_softc *sc, uint32_t v) {
static inline void exchange_with_mem_blk_addr_write(struct sbusfpga_sdram_softc *sc, uint32_t v) {
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0xcL, v);
}
#define CSR_EXCHANGE_WITH_MEM_BLK_CNT_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x10L)
#define CSR_EXCHANGE_WITH_MEM_BLK_CNT_SIZE 1
static inline uint32_t exchange_with_mem_blk_cnt_read(struct sbusfpga_sdram_softc *sc) {
#define CSR_EXCHANGE_WITH_MEM_DMA_ADDR_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x10L)
#define CSR_EXCHANGE_WITH_MEM_DMA_ADDR_SIZE 1
static inline uint32_t exchange_with_mem_dma_addr_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x10L);
}
static inline void exchange_with_mem_blk_cnt_write(struct sbusfpga_sdram_softc *sc, uint32_t v) {
static inline void exchange_with_mem_dma_addr_write(struct sbusfpga_sdram_softc *sc, uint32_t v) {
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x10L, v);
}
#define CSR_EXCHANGE_WITH_MEM_LAST_BLK_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x14L)
#define CSR_EXCHANGE_WITH_MEM_LAST_BLK_SIZE 1
static inline uint32_t exchange_with_mem_last_blk_read(struct sbusfpga_sdram_softc *sc) {
#define CSR_EXCHANGE_WITH_MEM_BLK_CNT_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x14L)
#define CSR_EXCHANGE_WITH_MEM_BLK_CNT_SIZE 1
static inline uint32_t exchange_with_mem_blk_cnt_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x14L);
}
#define CSR_EXCHANGE_WITH_MEM_LAST_DMA_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x18L)
#define CSR_EXCHANGE_WITH_MEM_LAST_DMA_SIZE 1
static inline uint32_t exchange_with_mem_last_dma_read(struct sbusfpga_sdram_softc *sc) {
static inline void exchange_with_mem_blk_cnt_write(struct sbusfpga_sdram_softc *sc, uint32_t v) {
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x14L, v);
}
#define CSR_EXCHANGE_WITH_MEM_LAST_BLK_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x18L)
#define CSR_EXCHANGE_WITH_MEM_LAST_BLK_SIZE 1
static inline uint32_t exchange_with_mem_last_blk_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x18L);
}
#define CSR_EXCHANGE_WITH_MEM_BLK_REM_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x1cL)
#define CSR_EXCHANGE_WITH_MEM_BLK_REM_SIZE 1
static inline uint32_t exchange_with_mem_blk_rem_read(struct sbusfpga_sdram_softc *sc) {
#define CSR_EXCHANGE_WITH_MEM_LAST_DMA_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x1cL)
#define CSR_EXCHANGE_WITH_MEM_LAST_DMA_SIZE 1
static inline uint32_t exchange_with_mem_last_dma_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x1cL);
}
#define CSR_EXCHANGE_WITH_MEM_DMA_STATUS_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x20L)
#define CSR_EXCHANGE_WITH_MEM_DMA_STATUS_SIZE 1
static inline uint32_t exchange_with_mem_dma_status_read(struct sbusfpga_sdram_softc *sc) {
#define CSR_EXCHANGE_WITH_MEM_BLK_REM_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x20L)
#define CSR_EXCHANGE_WITH_MEM_BLK_REM_SIZE 1
static inline uint32_t exchange_with_mem_blk_rem_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x20L);
}
#define CSR_EXCHANGE_WITH_MEM_WR_TOSDRAM_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x24L)
#define CSR_EXCHANGE_WITH_MEM_DMA_STATUS_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x24L)
#define CSR_EXCHANGE_WITH_MEM_DMA_STATUS_SIZE 1
static inline uint32_t exchange_with_mem_dma_status_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x24L);
}
#define CSR_EXCHANGE_WITH_MEM_WR_TOSDRAM_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x28L)
#define CSR_EXCHANGE_WITH_MEM_WR_TOSDRAM_SIZE 1
static inline uint32_t exchange_with_mem_wr_tosdram_read(struct sbusfpga_sdram_softc *sc) {
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x24L);
return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x28L);
}
#endif // CSR_EXCHANGE_WITH_MEM_BASE

2
sbus-to-ztex-gateware-migen/prom_migen.fth
View File

@@ -41,7 +41,7 @@ finish-device
new-device
\ Absolute minimal stuff; name & registers def.
" generic-ohci" device-name
" DISABLED-generic-ohci" device-name
\ USB registers are in the device space, not the CSR space
my-address sbusfpga_regionaddr_usb_host_ctrl + my-space h# 1000 reg

7
sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py
View File

@@ -53,8 +53,10 @@ class ExchangeWithMem(Module, AutoCSR):
#self.blk_base = CSRConstant(value=soc.wb_mem_map["main_ram"] >> log2_int(data_width)) # report where the blk starts
self.blk_size = CSRStatus(32) # report the block size to the SW layer
self.blk_base = CSRStatus(32) # report where the blk starts
self.mem_size = CSRStatus(32) # report how much memory we have
self.comb += self.blk_size.status.eq(data_width)
self.comb += self.blk_base.status.eq(soc.wb_mem_map["main_ram"] >> log2_int(data_width))
self.comb += self.mem_size.status.eq((256 * 1024 * 1024) >> log2_int(data_width)) # is it already available from mem_regions ?
self.blk_addr = CSRStorage(32, description = "SDRAM Block address to read/write from Wishbone memory (block of size {})".format(data_width))
self.dma_addr = CSRStorage(32, description = "Host Base address where to write/read data (i.e. SPARC Virtual addr)")
@@ -72,8 +74,9 @@ class ExchangeWithMem(Module, AutoCSR):
self.comb += self.dma_status.status[1:2].eq(~req_w_fsm.ongoing("Idle")) # Write FSM Busy
self.comb += self.dma_status.status[2:3].eq(self.fromsbus_fifo.readable) # Some data available to write to memory
self.comb += self.dma_status.status[8:9].eq(req_w_fsm.ongoing("ReqToMemory"))
self.comb += self.dma_status.status[9:10].eq(req_w_fsm.ongoing("WaitForAck"))
self.comb += self.dma_status.status[8:9].eq(req_r_fsm.ongoing("ReqFromMemory"))
self.comb += self.dma_status.status[9:10].eq(req_r_fsm.ongoing("WaitForData"))
self.comb += self.dma_status.status[10:11].eq(req_r_fsm.ongoing("QueueReqToMemory"))
#self.comb += self.dma_status.status[16:17].eq(self.wishbone_w_master.cyc) # show the WB iface status (W)
#self.comb += self.dma_status.status[17:18].eq(self.wishbone_w_master.stb)

35
sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
View File

@@ -306,11 +306,11 @@ class SBusFPGABus(Module):
#led6 = platform.request("user_led", 6)
#led7 = platform.request("user_led", 7)
led0123 = Signal(4)
self.sync += platform.request("user_led", 0).eq(led0123[0])
self.sync += platform.request("user_led", 1).eq(led0123[1])
self.sync += platform.request("user_led", 2).eq(led0123[2])
self.sync += platform.request("user_led", 3).eq(led0123[3])
#led0123 = Signal(4)
#self.sync += platform.request("user_led", 0).eq(led0123[0])
#self.sync += platform.request("user_led", 1).eq(led0123[1])
#self.sync += platform.request("user_led", 2).eq(led0123[2])
#self.sync += platform.request("user_led", 3).eq(led0123[3])
#self.sync += platform.request("user_led", 0).eq(self.wishbone_master.cyc)
#self.sync += platform.request("user_led", 1).eq(self.wishbone_master.stb)
@@ -354,6 +354,29 @@ class SBusFPGABus(Module):
self.submodules.slave_fsm = slave_fsm = FSM(reset_state="Reset")
self.sync += platform.request("user_led", 5).eq(~slave_fsm.ongoing("Idle"))
self.sync += platform.request("user_led", 0).eq(slave_fsm.ongoing("Master_Translation"))
self.sync += platform.request("user_led", 1).eq(slave_fsm.ongoing("Master_Read") |
slave_fsm.ongoing("Master_Read_Ack") |
slave_fsm.ongoing("Master_Read_Finish") |
slave_fsm.ongoing("Master_Write") |
slave_fsm.ongoing("Master_Write_Final"))
self.sync += platform.request("user_led", 2).eq(slave_fsm.ongoing("Slave_Do_Read") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_Burst") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_Burst_Wait_For_Data") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_Burst_Wait_For_Wishbone") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_HWord") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_HWord_Wait_For_Data") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_HWord_Wait_For_Wishbone") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_Byte") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_Byte_Wait_For_Data") |
slave_fsm.ongoing("Slave_Ack_Read_Reg_Byte_Wait_For_Wishbone"))
self.sync += platform.request("user_led", 3).eq(slave_fsm.ongoing("Slave_Ack_Reg_Write_Burst") |
slave_fsm.ongoing("Slave_Ack_Reg_Write_Final") |
slave_fsm.ongoing("Slave_Ack_Reg_Write_Burst_Wait_For_Wishbone") |
slave_fsm.ongoing("Slave_Ack_Reg_Write_HWord") |
slave_fsm.ongoing("Slave_Ack_Reg_Write_HWord_Wait_For_Wishbone") |
slave_fsm.ongoing("Slave_Ack_Reg_Write_Byte") |
slave_fsm.ongoing("Slave_Ack_Reg_Write_Byte_Wait_For_Wishbone"))
self.sync += platform.request("user_led", 6).eq(master_data_src_tosbus_fifo)
self.sync += platform.request("user_led", 7).eq(master_data_src_fromsbus_fifo)
@@ -680,7 +703,7 @@ class SBusFPGABus(Module):
NextValue(burst_limit_m1, 0), ## only single word for now
NextValue(master_size, SIZ_WORD),
NextValue(SBUS_3V3_SIZ_o, SIZ_WORD),
NextValue(led0123, self.wishbone_slave.sel)
#NextValue(led0123, self.wishbone_slave.sel)
]
}),
# NextValue(master_data, self.wishbone_slave.dat_w),