minor renaming, think about buffering writes
This commit is contained in:
Romain Dolbeau
parent
6d4ba3aaa1
commit
4303270b53
@ -332,6 +332,11 @@ class SBusFPGABus(Module):
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self.master_read_buffer_read = Array(Signal() for a in range(4))
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self.master_read_buffer_start = Signal()
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self.master_write_buffer_data = Array(Signal(32) for a in range(4))
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self.master_write_buffer_addr = Signal(28)
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self.master_write_buffer_todo = Array(Signal() for a in range(4))
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self.master_write_buffer_start = Signal()
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self.submodules.slave_fsm = slave_fsm = FSM(reset_state="Reset")
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self.sync += platform.request("user_led", 5).eq(~slave_fsm.ongoing("Idle"))
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@ -1285,13 +1290,13 @@ class SBusFPGABus(Module):
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)
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# ##### Slave read buffering FSM ####
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last_word_idx = Signal(2)
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self.submodules.wishbone_slave_buffering_fsm = wishbone_slave_buffering_fsm = FSM(reset_state="Reset")
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last_read_word_idx = Signal(2)
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self.submodules.wishbone_slave_read_buffering_fsm = wishbone_slave_read_buffering_fsm = FSM(reset_state="Reset")
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#self.sync += led4.eq(self.master_read_buffer_start)
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wishbone_slave_buffering_fsm.act("Reset",
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NextState("Idle")
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wishbone_slave_read_buffering_fsm.act("Reset",
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NextState("Idle")
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)
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wishbone_slave_buffering_fsm.act("Idle",
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wishbone_slave_read_buffering_fsm.act("Idle",
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If(self.wishbone_slave.cyc &
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self.wishbone_slave.stb &
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~self.wishbone_slave.ack &
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@ -1323,7 +1328,7 @@ class SBusFPGABus(Module):
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NextValue(self.master_read_buffer_read[1], 0),
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NextValue(self.master_read_buffer_read[2], 0),
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NextValue(self.master_read_buffer_read[3], 0),
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NextValue(last_word_idx, self.wishbone_slave.adr[0:2]),
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NextValue(last_read_word_idx, self.wishbone_slave.adr[0:2]),
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NextValue(self.master_read_buffer_start, 1),
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NextState("WaitForData")
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).Else(
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@ -1331,16 +1336,16 @@ class SBusFPGABus(Module):
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)
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)
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)
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wishbone_slave_buffering_fsm.act("WaitForData",
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wishbone_slave_read_buffering_fsm.act("WaitForData",
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#led2.eq(1),
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If(self.master_read_buffer_done[last_word_idx],
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If(self.master_read_buffer_done[last_read_word_idx],
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NextValue(self.wishbone_slave.ack, 1),
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NextValue(self.wishbone_slave.dat_r, Cat(self.master_read_buffer_data[last_word_idx][24:32], # LE
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self.master_read_buffer_data[last_word_idx][16:24],
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self.master_read_buffer_data[last_word_idx][ 8:16],
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self.master_read_buffer_data[last_word_idx][ 0: 8])),
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# NextValue(self.wishbone_slave.dat_r, self.master_read_buffer_data[last_word_idx]),
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NextValue(self.master_read_buffer_read[last_word_idx], 1),
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NextValue(self.wishbone_slave.dat_r, Cat(self.master_read_buffer_data[last_read_word_idx][24:32], # LE
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self.master_read_buffer_data[last_read_word_idx][16:24],
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self.master_read_buffer_data[last_read_word_idx][ 8:16],
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self.master_read_buffer_data[last_read_word_idx][ 0: 8])),
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# NextValue(self.wishbone_slave.dat_r, self.master_read_buffer_data[last_read_word_idx]),
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NextValue(self.master_read_buffer_read[last_read_word_idx], 1),
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NextValue(wishbone_slave_timeout, wishbone_default_timeout),
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NextState("Idle")
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),
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@ -1349,3 +1354,77 @@ class SBusFPGABus(Module):
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)
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)
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#last_write_word_idx = Signal(2)
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#last_write_timeout = Signal(3)
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#self.submodules.wishbone_slave_write_buffering_fsm = wishbone_slave_write_buffering_fsm = FSM(reset_state="Reset")
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#wishbone_slave_write_buffering_fsm.act("Reset",
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# NextState("Idle")
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#)
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#wishbone_slave_write_buffering_fsm.act("Idle",
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# If(self.wishbone_slave.cyc &
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# self.wishbone_slave.stb &
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# ~self.wishbone_slave.ack &
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# ~self.wishbone_slave.err &
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# (self.wishbone_slave.sel == 0xf) & # Full Words Only
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# self.wishbone_slave.we,
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# NextValue(self.master_write_buffer_addr, self.wishbone_slave.adr[2:30]),
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# NextValue(self.master_write_buffer_data[self.wishbone_slave.adr[0:2]],
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# Cat(self.wishbone_slave.dat_w[24:32], # LE
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# self.wishbone_slave.dat_w[16:24],
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# self.wishbone_slave.dat_w[ 8:16],
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# self.wishbone_slave.dat_w[ 0: 8])),
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# NextValue(self.master_write_buffer_todo[self.wishbone_slave.adr[0:2]], 1),
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# NextValue(self.wishbone_slave.ack, 1),
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# NextValue(last_write_word_idx, self.wishbone_slave.adr[0:2]),
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# NextValue(wishbone_slave_timeout, wishbone_default_timeout),
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# If(self.wishbone_slave.adr[0:2] == 0,
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# NextValue(last_write_timeout, 5), # CHECKME: 5 is arbitrary
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# NextState("WaitForMoreData"),
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# ).Else(
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# NextValue(self.master_write_buffer_start, 1),
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# NextState("WaitForWrite"),
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# )
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# )
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#)
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#wishbone_slave_write_buffering_fsm.act("WaitForMoreData",
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# If(last_write_timeout > 0,
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# NextValue(last_write_timeout, last_write_timeout - 1),
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# ),
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# If(self.wishbone_slave.cyc &
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# self.wishbone_slave.stb &
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# ~self.wishbone_slave.ack &
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# ~self.wishbone_slave.err &
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# self.wishbone_slave.we,
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# If(((self.wishbone_slave.adr[2:30] != self.master_write_buffer_addr) |
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# (self.wishbone_slave.sel != 0xf)),
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# NextValue(self.master_write_buffer_start, 1),
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# NextState("WaitForWrite"),
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# ).Else(
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# NextValue(self.master_write_buffer_data[self.wishbone_slave.adr[0:2]],
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# Cat(self.wishbone_slave.dat_w[24:32], # LE
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# self.wishbone_slave.dat_w[16:24],
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# self.wishbone_slave.dat_w[ 8:16],
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# self.wishbone_slave.dat_w[ 0: 8])),
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# NextValue(self.master_write_buffer_todo[self.wishbone_slave.adr[0:2]], 1),
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# NextValue(self.wishbone_slave.ack, 1),
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# NextValue(last_write_word_idx, self.wishbone_slave.adr[0:2]),
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# NextValue(wishbone_slave_timeout, wishbone_default_timeout),
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# NextValue(last_write_timeout, 5), # CHECKME: 5 is arbitrary
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# )
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# ).Elif(self.master_write_buffer_todo[0] &
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# self.master_write_buffer_todo[1] &
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# self.master_write_buffer_todo[2] &
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# self.master_write_buffer_todo[3],
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# NextValue(self.master_write_buffer_start, 1),
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# NextState("WaitForWrite"),
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# ).Elif(last_write_timeout == 0,
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# NextValue(self.master_write_buffer_start, 1),
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# NextState("WaitForWrite"),
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# )
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#)
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#wishbone_slave_write_buffering_fsm.act("WaitForWrite",
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# If(self.master_write_buffer_start == 0,
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# NextState("Idle"),
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# )
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#)
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