github.com/rdolbeau.SBusFPGA
1
0
Fork 0
mirror of synced 2026-01-11 23:42:59 +00:00
Code Issues Projects Releases Wiki Activity

nothing doing, SPI-mode SD won't work reliably :-(

Browse Source
This commit is contained in:
Romain Dolbeau 2021-01-17 08:16:25 -05:00
parent 119862f57f
commit 5986a8e30b
3 changed files with 68 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
sbus-to-ztex-gateware/SimpleSDHC_wrapper.vhd
View File

@ -78,16 +78,16 @@ architecture RTL of SimpleSDHC_wrapper is
end component;
signal sd_reset : std_logic;
signal sd_rd : std_logic;
signal sd_wr : std_logic;
signal sd_continue : std_logic;
signal sd_rd : std_logic := '0';
signal sd_wr : std_logic := '0';
signal sd_continue : std_logic := '0';
signal sd_addr : std_logic_vector(31 downto 0);
signal sd_data_i : std_logic_vector(7 downto 0);
signal sd_data_o : std_logic_vector(7 downto 0);
signal sd_busy : std_logic;
signal sd_dout_avail : std_logic;
signal sd_dout_taken : std_logic;
signal sd_din_valid : std_logic;
signal sd_dout_taken : std_logic := '0';
signal sd_din_valid : std_logic := '0';
signal sd_din_taken : std_logic;
signal sd_error : std_logic;
signal sd_error_code : std_logic_vector(7 downto 0);
@ -113,7 +113,7 @@ begin
generic map (
clockRate => 50000000,
slowClockDivider => 128,
R1_TIMEOUT => 10,
R1_TIMEOUT => 64,
WRITE_TIMEOUT => 500
)
port map (
@ -187,6 +187,9 @@ begin
when SIMPLESDHC_IDLE =>
sd_rd <= '0';
sd_wr <= '0';
sd_continue <= '0';
sd_dout_taken <= '0';
sd_din_valid <= '0';
if ((sd_busy = '0') and (out_sd_rd_addr_req ='1')) THEN -- handshake
--output_fifo_in <= '1' & x"7000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
--output_fifo_wr_en <= '1';
@ -258,20 +261,25 @@ output_fifo_wr_en <= '1';
END IF;
when SIMPLESDHC_READ_WAIT_READ =>
IF (sd_error = '1') THEN
output_fifo_in <= '1' & x"1100" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
sd_rd <= '0';
SIMPLESDHC_State <= SIMPLESDHC_IDLE;
--only read byte if we'll have some space to output the buffer
IF ((output_fifo_full = '0') AND (sd_dout_avail = '1')) THEN
ELSIF ((output_fifo_full = '0') AND (sd_dout_avail = '1')) THEN
output_fifo_in <= '1' & x"40" & sd_data_o & conv_std_logic_vector(byte_counter,16) & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
databuf(((15 - (byte_counter mod 16))*8 + 7) downto ((15 - (byte_counter mod 16))*8)) := sd_data_o;
sd_dout_taken <= '1';
byte_counter := byte_counter + 1;
SIMPLESDHC_State <= SIMPLESDHC_READ_WAIT_READ2;
ELSIF ((output_fifo_full = '0') AND (timeout_counter = 0)) THEN
output_fifo_in <= '1' & x"1100" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
SIMPLESDHC_State <= SIMPLESDHC_IDLE;
ELSIF (output_fifo_full = '0') THEN
timeout_counter := timeout_counter - 1;
-- ELSIF ((output_fifo_full = '0') AND (timeout_counter = 0)) THEN
--output_fifo_in <= '1' & x"1100" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
--output_fifo_wr_en <= '1';
-- SIMPLESDHC_State <= SIMPLESDHC_IDLE;
-- ELSIF (output_fifo_full = '0') THEN
-- timeout_counter := timeout_counter - 1;
ELSIF (sd_busy = '0') THEN
output_fifo_in <= '1' & x"1000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
@ -279,7 +287,12 @@ output_fifo_wr_en <= '1';
END IF;
when SIMPLESDHC_READ_WAIT_READ2 =>
IF (sd_dout_avail = '0') THEN
IF (sd_error = '1') THEN
output_fifo_in <= '1' & x"3100" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
sd_rd <= '0';
SIMPLESDHC_State <= SIMPLESDHC_IDLE;
ELSIF (sd_dout_avail = '0') THEN
output_fifo_in <= '1' & x"3000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
sd_dout_taken <= '0';
@ -327,8 +340,13 @@ output_fifo_wr_en <= '1';
END IF;
when SIMPLESDHC_WRITE_WAIT_WRITE =>
IF (sd_error = '1') THEN
output_fifo_in <= '1' & x"1101" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
sd_wr <= '0';
SIMPLESDHC_State <= SIMPLESDHC_IDLE;
--only write byte if we have some space to output the buffer
IF ((input_fifo_empty = '0') OR ((byte_counter mod 16) /= 0)) THEN
ELSIF ((input_fifo_empty = '0') OR ((byte_counter mod 16) /= 0)) THEN
--output_fifo_in <= '1' & x"40" & sd_data_o & conv_std_logic_vector(byte_counter,16) & x"00000000000000000000000000000000";
--output_fifo_wr_en <= '1';
IF ((byte_counter mod 16) = 0) THEN
@ -339,12 +357,12 @@ output_fifo_wr_en <= '1';
sd_din_valid <= '1';
byte_counter := byte_counter + 1;
SIMPLESDHC_State <= SIMPLESDHC_WRITE_WAIT_WRITE2;
ELSIF ((input_fifo_empty = '0') AND (timeout_counter = 0)) THEN
output_fifo_in <= '1' & x"1101" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
SIMPLESDHC_State <= SIMPLESDHC_IDLE;
ELSIF (input_fifo_empty = '0') THEN
timeout_counter := timeout_counter - 1;
-- ELSIF ((input_fifo_empty = '0') AND (timeout_counter = 0)) THEN
--output_fifo_in <= '1' & x"1101" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
--output_fifo_wr_en <= '1';
-- SIMPLESDHC_State <= SIMPLESDHC_IDLE;
-- ELSIF (input_fifo_empty = '0') THEN
-- timeout_counter := timeout_counter - 1;
ELSIF (sd_busy = '0') THEN
output_fifo_in <= '1' & x"1001" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
@ -352,7 +370,12 @@ output_fifo_wr_en <= '1';
END IF;
when SIMPLESDHC_WRITE_WAIT_WRITE2 =>
IF (sd_din_taken = '1') THEN
IF (sd_error = '1') THEN
output_fifo_in <= '1' & x"3101" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
output_fifo_wr_en <= '1';
sd_wr <= '0';
SIMPLESDHC_State <= SIMPLESDHC_IDLE;
ELSIF (sd_din_taken = '1') THEN
--output_fifo_in <= '1' & x"3001" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000";
--output_fifo_wr_en <= '1';
sd_din_valid <= '0';

5
sbus-to-ztex-gateware/sbus-to-ztex.xdc
View File

@ -383,6 +383,7 @@ set_property IOSTANDARD LVTTL [get_ports {LED1}]
set_property PACKAGE_PIN V6 [get_ports {SD_nCS}]
set_property IOSTANDARD LVCMOS33 [get_ports {SD_nCS}]
set_property PULLUP TRUE [get_ports {SD_nCS}]
set_property SLEW FAST [get_ports {SD_nCS}]
set_property PACKAGE_PIN U6 [get_ports {LED2}]
set_property IOSTANDARD LVTTL [get_ports {LED2}]
@ -392,6 +393,8 @@ set_property IOSTANDARD LVTTL [get_ports {LED2}]
#set_property IOSTANDARD LVCMOS33 [get_ports {SD_D0}]
set_property PACKAGE_PIN V5 [get_ports {SD_DO}]
set_property IOSTANDARD LVCMOS33 [get_ports {SD_DO}]
set_property PULLUP TRUE [get_ports {SD_DO}]
set_property SLEW FAST [get_ports {SD_DO}]
set_property PACKAGE_PIN T8 [get_ports {LED3}]
set_property IOSTANDARD LVTTL [get_ports {LED3}]
@ -403,12 +406,14 @@ set_property IOSTANDARD LVTTL [get_ports {LED3}]
#set_property IOSTANDARD LVCMOS33 [get_ports {SD_CLK}]
set_property PACKAGE_PIN R8 [get_ports {SD_CLK}]
set_property IOSTANDARD LVCMOS33 [get_ports {SD_CLK}]
set_property SLEW FAST [get_ports {SD_CLK}]
#set_property PACKAGE_PIN T5 [get_ports {SD_CMD}]
#set_property IOSTANDARD LVCMOS33 [get_ports {SD_CMD}]
set_property PACKAGE_PIN T5 [get_ports {SD_DI}]
set_property IOSTANDARD LVCMOS33 [get_ports {SD_DI}]
set_property PULLUP TRUE [get_ports {SD_DI}]
set_property SLEW FAST [get_ports {SD_DI}]
set_property PACKAGE_PIN R7 [get_ports {SBUS_3V3_SIZ[0]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[0]}]

38
sbus-to-ztex-gateware/sbus_fsm.vhd
View File

@ -1765,8 +1765,7 @@ BEGIN
IF (fifo_fromsdcard_dout(159 downto 144) = x"1000") THEN
-- fixme
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SDDMAW_CTRL) <= x"00000000";
END IF;
IF (fifo_fromsdcard_dout(159 downto 144) = x"1001") THEN
ELSIF (fifo_fromsdcard_dout(159 downto 144) = x"1001") THEN
-- fixme
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SDDMA_CTRL) <= x"00000000";
END IF;
@ -1811,8 +1810,7 @@ BEGIN
out_sd_rd_addr_send <= '1';
END IF;
sdcard_deadbeef_counter := 0;
END IF;
IF (REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_CTRL)(SD_CTRL_SENT_IDX) = '1') THEN
ELSIF (REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_CTRL)(SD_CTRL_SENT_IDX) = '1') THEN
IF (out_sd_rd_addr_rcv = '1') THEN
out_sd_rd_addr_send <= '0';
IF (REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_CTRL)(SD_CTRL_READ_IDX) = '1') THEN
@ -1822,23 +1820,23 @@ BEGIN
END IF;
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_CTRL) <= (others => '0');
END IF;
IF (sdcard_deadbeef_counter = 255) THEN
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT) <= x"C0FFEE00";
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT2) <= x"0000" & conv_std_logic_vector(sdcard_deadbeef_counter, 16);
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_CTRL) <= (others => '0');
END IF;
sdcard_deadbeef_counter := sdcard_deadbeef_counter + 1;
END IF;
if ((fifo_fromsdcard_full = '1') AND (fifo_fromsdcard_empty = '1')) THEN
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SDDMAW_CTRL) <= (others => '0');
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SDDMA_CTRL) <= (others => '0');
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT) <= x"DEADBEEF";
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT2) <= x"C000" & conv_std_logic_vector(sdcard_deadbeef_counter, 16);
sdcard_deadbeef_counter := sdcard_deadbeef_counter + 1;
ELSIF (REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT) = x"DEADBEEF") THEN
REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT2) <=
fifo_fromsdcard_full & fifo_fromsdcard_empty & '0' & '0' & x"000" & conv_std_logic_vector(sdcard_deadbeef_counter, 16);
-- IF (sdcard_deadbeef_counter = 255) THEN
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT) <= x"C0FFEE00";
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT2) <= x"0000" & conv_std_logic_vector(sdcard_deadbeef_counter, 16);
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_CTRL) <= (others => '0');
-- END IF;
-- sdcard_deadbeef_counter := sdcard_deadbeef_counter + 1;
END IF;
-- if ((fifo_fromsdcard_full = '1') AND (fifo_fromsdcard_empty = '1')) THEN
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SDDMAW_CTRL) <= (others => '0');
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SDDMA_CTRL) <= (others => '0');
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT) <= x"DEADBEEF";
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT2) <= x"C000" & conv_std_logic_vector(sdcard_deadbeef_counter, 16);
-- sdcard_deadbeef_counter := sdcard_deadbeef_counter + 1;
-- ELSIF (REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT) = x"DEADBEEF") THEN
-- REGISTERS(reg_bank_size*reg_bank_sdcard_idx + REG_INDEX_SD_STATUS_DAT2) <=
-- fifo_fromsdcard_full & fifo_fromsdcard_empty & '0' & '0' & x"000" & conv_std_logic_vector(sdcard_deadbeef_counter, 16);
-- END IF;
END IF;
END PROCESS;