github.com/rdolbeau.SBusFPGA
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Wishbone is word-addressed (still no lock)

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This commit is contained in:
Romain Dolbeau
2021-06-15 02:31:07 -04:00
parent 49b4dae59d
commit 5c66170a3a
2 changed files with 2 additions and 2 deletions
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2
sbus-to-ztex-gateware-migen/sbus-to-fpga.py
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@@ -122,7 +122,7 @@ class SBusFPGA(SoCCore):
self.submodules.sbus_slave = SBusFPGASlave(platform=self.platform, self.submodules.sbus_slave = SBusFPGASlave(platform=self.platform,
prom=prom, prom=prom,
hold_reset=hold_reset, hold_reset=hold_reset,
wishbone=wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width), wishbone=wishbone.Interface(data_width=self.bus.data_width),
chaser=self.leds) chaser=self.leds)
self.bus.add_master(name="SBusBridgeToWishbone", master=self.sbus_slave.wishbone) self.bus.add_master(name="SBusBridgeToWishbone", master=self.sbus_slave.wishbone)

2
sbus-to-ztex-gateware-migen/sbus_to_fpga_slave.py
View File

@@ -480,7 +480,7 @@ class SBusFPGASlave(Module):
) )
) )
wb_fsm.act("Write", wb_fsm.act("Write",
self.wishbone.adr.eq(csr_data_w_addr), self.wishbone.adr.eq(csr_data_w_addr[2:32]),
self.wishbone.dat_w.eq(csr_data_w_data), self.wishbone.dat_w.eq(csr_data_w_data),
self.wishbone.we.eq(1), self.wishbone.we.eq(1),
self.wishbone.cyc.eq(1), self.wishbone.cyc.eq(1),