basic DMA support
This commit is contained in:
Romain Dolbeau
parent
10447bb7ec
commit
92c7751290
@ -46,6 +46,8 @@ __KERNEL_RCSID(0, "$NetBSD$");
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#include <dev/sbus/rdfpga.h>
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#include <machine/param.h>
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int rdfpga_print(void *, const char *);
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int rdfpga_match(device_t, cfdata_t, void *);
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void rdfpga_attach(device_t, device_t, void *);
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@ -99,19 +101,19 @@ rdfpga_ioctl (dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
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switch (cmd) {
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case RDFPGA_WC:
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for (i = 0 ; i < 2 ; i++)
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_C + (i*8)), bits->x[i] );
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_C + (i*8)), bits->x[i] );
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break;
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case RDFPGA_WH:
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for (i = 0 ; i < 2 ; i++)
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_H + (i*8)), bits->x[i] );
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_H + (i*8)), bits->x[i] );
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break;
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case RDFPGA_WI:
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for (i = 0 ; i < 2 ; i++)
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_I + (i*8)), bits->x[i] );
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_I + (i*8)), bits->x[i] );
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break;
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case RDFPGA_RC:
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for (i = 0 ; i < 2 ; i++)
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bits->x[i] = bus_space_read_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_C + (i*8)));
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bits->x[i] = bus_space_read_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_C + (i*8)));
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break;
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case RDFPGA_WL:
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_LED, *(uint32_t*)data);
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@ -131,11 +133,11 @@ rdfpga_open(dev_t dev, int flags, int mode, struct lwp *l)
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int i;
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for (i = 0 ; i < 4 ; i++)
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_C + (i*4)), 0);
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_C + (i*4)), 0);
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for (i = 0 ; i < 4 ; i++)
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_H + (i*4)), 0);
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_H + (i*4)), 0);
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for (i = 0 ; i < 4 ; i++)
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_I + (i*4)), 0);
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_I + (i*4)), 0);
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return (0);
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}
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@ -147,11 +149,11 @@ rdfpga_close(dev_t dev, int flags, int mode, struct lwp *l)
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int i;
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for (i = 0 ; i < 4 ; i++)
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_C + (i*4)), 0);
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_C + (i*4)), 0);
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for (i = 0 ; i < 4 ; i++)
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_H + (i*4)), 0);
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_H + (i*4)), 0);
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for (i = 0 ; i < 4 ; i++)
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_I + (i*4)), 0);
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_I + (i*4)), 0);
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return (0);
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}
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@ -160,17 +162,115 @@ int
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rdfpga_write(dev_t dev, struct uio *uio, int flags)
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{
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struct rdfpga_softc *sc = device_lookup_private(&rdfpga_cd, minor(dev));
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int error = 0;
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int error = 0, ctr = 0, res;
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while (uio->uio_resid > 0) {
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aprint_normal_dev(sc->sc_dev, "dma uio: %zu in %d\n", uio->uio_resid, uio->uio_iovcnt);
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delay(100);
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while (!error && uio->uio_resid >= 16 && uio->uio_iovcnt == 1) {
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uint64_t ctrl;
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uint32_t nblock = uio->uio_resid/16;
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if (nblock > 256)
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nblock = 256;
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/* no implemented on sparc ? */
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/* if (bus_dmamap_load_uio(sc->sc_dmatag, sc->sc_dmamap, uio, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | BUS_DMA_WRITE)) { */
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/* aprint_error_dev(sc->sc_dev, "cannot allocate DVMA address"); */
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/* return ENXIO; */
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/* } else { */
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/* aprint_normal_dev(sc->sc_dev, "dma: %lu %lu %d\n", sc->sc_dmamap->dm_maxsegsz, sc->sc_dmamap->dm_mapsize, sc->sc_dmamap->dm_nsegs); */
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/* } */
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/* uint64_t buf[4]; */
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/* if ((error = uiomove(buf, 32, uio)) != 0) */
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/* break; */
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/* if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, buf, 32, /\* kernel space *\/ NULL, */
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/* BUS_DMA_NOWAIT | BUS_DMA_STREAMING | BUS_DMA_WRITE)) { */
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/* aprint_error_dev(sc->sc_dev, "cannot allocate DVMA address"); */
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/* return ENXIO; */
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/* } else { */
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/* aprint_normal_dev(sc->sc_dev, "dma: %lu %lu %d\n", sc->sc_dmamap->dm_maxsegsz, sc->sc_dmamap->dm_mapsize, sc->sc_dmamap->dm_nsegs); */
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/* } */
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aprint_normal_dev(sc->sc_dev, "dmamem about to alloc for %d blocks...\n", nblock);
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bus_dma_segment_t segs;
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int rsegs;
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if (bus_dmamem_alloc(sc->sc_dmatag, nblock*16, 64, 64, &segs, 1, &rsegs, BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) {
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aprint_error_dev(sc->sc_dev, "cannot allocate DVMA memory");
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return ENXIO;
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} else {
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aprint_normal_dev(sc->sc_dev, "dmamem alloc: %d\n", rsegs);
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}
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void* kvap;
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if (bus_dmamem_map(sc->sc_dmatag, &segs, 1, nblock*16, &kvap, BUS_DMA_NOWAIT)) {
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aprint_error_dev(sc->sc_dev, "cannot allocate DVMA address");
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return ENXIO;
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} else {
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aprint_normal_dev(sc->sc_dev, "dmamem map: %p\n", kvap);
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}
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if ((error = uiomove(kvap, nblock*16, uio)) != 0)
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break;
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aprint_normal_dev(sc->sc_dev, "uimove: left %zu in %d\n", uio->uio_resid, uio->uio_iovcnt);
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if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, kvap, nblock*16, /* kernel space */ NULL,
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BUS_DMA_NOWAIT | BUS_DMA_STREAMING | BUS_DMA_WRITE)) {
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aprint_error_dev(sc->sc_dev, "cannot load dma map");
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return ENXIO;
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} else {
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aprint_normal_dev(sc->sc_dev, "dmamap: %lu %lu %d\n", sc->sc_dmamap->dm_maxsegsz, sc->sc_dmamap->dm_mapsize, sc->sc_dmamap->dm_nsegs);
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}
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bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, nblock*16, BUS_DMASYNC_PREWRITE);
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aprint_normal_dev(sc->sc_dev, "dma: synced\n");
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ctrl = ((uint64_t)(0x80000000 | ((nblock-1) & 0x0FF))) | ((uint64_t)(uint32_t)(sc->sc_dmamap->dm_segs[0].ds_addr)) << 32;
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aprint_normal_dev(sc->sc_dev, "trying 0x%016llx\n", ctrl);
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_DMA_ADDR), ctrl);
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aprint_normal_dev(sc->sc_dev, "dma: cmd sent\n");
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do {
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ctr ++;
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delay(1);
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} while (((res = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_DMA_CTRL))) & 0x80000000) && (ctr < 10));
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if ((res & 0x80000000) || (res & 0x20000000)) {
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aprint_error_dev(sc->sc_dev, "read 0x%08x (%d try)\n", res, ctr);
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error = ENXIO;
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}
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/* if (sc->sc_dmamap->dm_nsegs > 0) { */
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bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, nblock*16, BUS_DMASYNC_POSTWRITE);
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aprint_normal_dev(sc->sc_dev, "dma: synced (2)\n");
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bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
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aprint_normal_dev(sc->sc_dev, "dma: unloaded\n");
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bus_dmamem_unmap(sc->sc_dmatag, kvap, nblock*16);
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aprint_normal_dev(sc->sc_dev, "dma: unmapped\n");
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bus_dmamem_free(sc->sc_dmatag, &segs, 1);
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aprint_normal_dev(sc->sc_dev, "dma: freed\n");
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/* } */
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}
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if (uio->uio_resid > 0)
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aprint_normal_dev(sc->sc_dev, "%zd bytes left after DMA\n", uio->uio_resid);
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while (!error && uio->uio_resid > 0) {
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uint64_t bp[2] = {0, 0};
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size_t len = uimin(16, uio->uio_resid);
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if ((error = uiomove(bp, len, uio)) != 0)
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break;
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_I + 0), bp[0]);
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_I + 8), bp[1]);
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_I + 0), bp[0]);
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bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_I + 8), bp[1]);
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}
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return (error);
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@ -204,19 +304,17 @@ rdfpga_attach(device_t parent, device_t self, void *aux)
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int node;
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int sbusburst;
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/* bus_dma_tag_t dt = sa->sa_dmatag; */
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bus_space_handle_t bh;
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sc->sc_bustag = sa->sa_bustag;
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sc->sc_dmatag = sa->sa_dmatag;
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sc->sc_dev = self;
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if (sbus_bus_map(sc->sc_bustag, sa->sa_slot, sa->sa_offset, sa->sa_size,
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BUS_SPACE_MAP_LINEAR, &bh) != 0) {
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BUS_SPACE_MAP_LINEAR, &sc->sc_bhregs) != 0) {
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aprint_error(": cannot map registers\n");
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return;
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}
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sc->sc_bhregs = bh;
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//sc->sc_buffer = bus_space_vaddr(sc->sc_bustag, sc->sc_bhregs);
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sc->sc_bufsiz = sa->sa_size;
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@ -239,12 +337,22 @@ rdfpga_attach(device_t parent, device_t self, void *aux)
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sc->sc_burst &= sbusburst;
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aprint_normal("\n");
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aprint_normal_dev(self, " nid 0x%x, bustag %p, slave-burst 0x%x\n",
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aprint_normal_dev(self, "nid 0x%x, bustag %p, slave-burst 0x%x\n",
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sc->sc_node,
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sc->sc_bustag,
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sc->sc_burst);
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/* change blink pattern */
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/* change blink pattern to marching 2 */
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_LED , 0x81422418);
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bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_LED , 0xc0300c03);
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/* DMA */
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/* Allocate a dmamap */
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#define MAX_DMA_SZ 4096
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if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_dmamap) != 0) {
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aprint_error_dev(self, ": DMA map create failed\n");
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} else {
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aprint_normal_dev(self, "dmamap: %lu %lu %d (%p)\n", sc->sc_dmamap->dm_maxsegsz, sc->sc_dmamap->dm_mapsize, sc->sc_dmamap->dm_nsegs, sc->sc_dmatag->_dmamap_load);
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}
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}
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@ -41,12 +41,26 @@ struct rdfpga_softc {
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bus_space_handle_t sc_bhregs; /* bus handle */
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//void * sc_buffer; /* VA of the registers */
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int sc_bufsiz; /* Size of buffer */
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bus_dma_tag_t sc_dmatag;
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bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
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};
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#define RDFPGA_REG_LED 0x0
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#define RDFPGA_REG_LED 0x0 /* 1 reg */
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#define RDFPGA_REG_H 0x40
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#define RDFPGA_REG_C 0x50
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#define RDFPGA_REG_I 0x60
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#define RDFGPA_REG_GCM_BASE 0x40
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#define RDFPGA_REG_GCM_H (RDFGPA_REG_GCM_BASE + 0x00) /* 4 regs */
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#define RDFPGA_REG_GCM_C (RDFGPA_REG_GCM_BASE + 0x10) /* 4 regs */
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#define RDFPGA_REG_GCM_I (RDFGPA_REG_GCM_BASE + 0x20) /* 4 regs */
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#define RDFPGA_REG_DMA_BASE 0x80
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#define RDFPGA_REG_DMA_ADDR (RDFPGA_REG_DMA_BASE + 0x00)
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#define RDFPGA_REG_DMA_CTRL (RDFPGA_REG_DMA_BASE + 0x04)
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#define RDFPGA_MASK_DMA_CTRL_START 0x80000000
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#define RDFPGA_MASK_DMA_CTRL_BUSY 0x40000000
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#define RDFPGA_MASK_DMA_CTRL_ERR 0x20000000
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/* #define RDFPGA_MASK_DMA_CTRL_RW 0x10000000 */
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#define RDFPGA_MASK_DMA_CTRL_BLKCNT 0x000000FF
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/* #define RDFPGA_MASK_DMA_CTRL_SIZ 0x00000F00 */
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#endif /* _RDFPGA_H_ */
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