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read PROM from Wishbone (simplify things, save resources as it was mapped there already anyway), add sd_card (unused, un-promed yet)

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This commit is contained in:
Romain Dolbeau
2021-07-14 08:30:27 -04:00
parent b46bdf382a
commit 9437d287db
4 changed files with 193 additions and 92 deletions
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8
sbus-to-ztex-gateware-migen/prom_csr.fth
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@@ -1,9 +1,13 @@
\ auto-generated base regions for CSRs in the PROM
h# 40000 constant sbusfpga_csraddr_leds
h# 41000 constant sbusfpga_csraddr_ddrphy
h# 42000 constant sbusfpga_csraddr_sdram
h# 42000 constant sbusfpga_csraddr_sdblock2mem
h# 43000 constant sbusfpga_csraddr_sdcore
h# 44000 constant sbusfpga_csraddr_sdirq
h# 45000 constant sbusfpga_csraddr_sdmem2block
h# 46000 constant sbusfpga_csraddr_sdphy
h# 47000 constant sbusfpga_csraddr_sdram
h# 80000 constant sbusfpga_regionaddr_usb_host_ctrl
h# 90000 constant sbusfpga_regionaddr_usb_shared_mem
h# 0 constant sbusfpga_regionaddr_prom
h# fc000000 constant sbusfpga_regionaddr_usb_fake_dma
h# 80000000 constant sbusfpga_regionaddr_main_ram

71
sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
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@@ -171,7 +171,7 @@ LED_M_READ = 0x20
LED_M_CACHE = 0x40
class SBusFPGABus(Module):
def __init__(self, platform, prom, hold_reset, wishbone_slave, wishbone_master):
def __init__(self, platform, hold_reset, wishbone_slave, wishbone_master):
self.platform = platform
self.hold_reset = hold_reset
@@ -379,14 +379,8 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_PARITY),
NextState("Slave_Error")
).Elif((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX),
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
NextValue(SBUS_3V3_ERRs_o, 1),
NextValue(p_data, prom[SBUS_3V3_PA_i[ADDR_PHYS_LOW+2:ADDR_PFX_LOW]]),
NextValue(sbus_wishbone_le, 0),
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 40))),
NextState("Slave_Ack_Read_Prom_Burst")
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == USBOHCI_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
@@ -417,16 +411,10 @@ class SBusFPGABus(Module):
(SBUS_3V3_ASs_i == 0) &
(SIZ_BYTE == SBUS_3V3_SIZ_i) &
(SBUS_3V3_PPRD_i == 1)),
NextValue(sbus_oe_master_in, 1),
NextValue(sbus_last_pa, SBUS_3V3_PA_i),
If((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX),
NextValue(SBUS_3V3_ACKs_o, ACK_BYTE),
NextValue(SBUS_3V3_ERRs_o, 1),
NextValue(sbus_wishbone_le, 0),
NextValue(p_data, prom[SBUS_3V3_PA_i[ADDR_PHYS_LOW+2:ADDR_PFX_LOW]]),
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 80))),
NextState("Slave_Ack_Read_Prom_Byte")
).Elif((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX),
NextValue(sbus_oe_master_in, 1),
NextValue(sbus_last_pa, SBUS_3V3_PA_i),
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
NextValue(SBUS_3V3_ERRs_o, 1),
NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
@@ -444,13 +432,13 @@ class SBusFPGABus(Module):
NextValue(sbus_slave_timeout, sbus_default_timeout),
NextState("Slave_Ack_Read_Reg_Byte_Wait_For_Wishbone")
)
).Else(
#NextValue(self.led_display.value, 0x0000000040 | 0x0000000001),
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextState("Slave_Error")
)
).Else(
#NextValue(self.led_display.value, 0x0000000040 | 0x0000000001),
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextState("Slave_Error")
)
).Elif(((SBUS_3V3_SELs_i == 0) &
(SBUS_3V3_ASs_i == 0) &
(SIZ_HWORD == SBUS_3V3_SIZ_i) &
@@ -462,7 +450,8 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_PARITY),
NextState("Slave_Error")
).Elif((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX),
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
NextValue(SBUS_3V3_ERRs_o, 1),
NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)),
@@ -712,34 +701,6 @@ class SBusFPGABus(Module):
)
# ##### SLAVE READ #####
# ## BURST (1->16 words) ##
slave_fsm.act("Slave_Ack_Read_Prom_Burst",
#NextValue(self.led_display.value, Cat(Signal(8, reset = 0x02), self.led_display.value[8:40])),
NextValue(sbus_oe_data, 1),
NextValue(SBUS_3V3_D_o, p_data),
NextValue(p_data, prom[Cat(index_with_wrap((burst_counter+1), burst_limit_m1, sbus_last_pa[ADDR_PHYS_LOW+2:ADDR_PHYS_LOW+6]), sbus_last_pa[ADDR_PHYS_LOW+6:ADDR_PFX_LOW])]),
If((burst_counter == burst_limit_m1),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE),
NextState("Slave_Do_Read")
).Else(
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
NextValue(burst_counter, burst_counter + 1)
)
)
slave_fsm.act("Slave_Ack_Read_Prom_Byte",
#NextValue(self.led_display.value, Cat(Signal(8, reset = 0x03), self.led_display.value[8:40])),
NextValue(sbus_oe_data, 1),
If((sbus_last_pa[0:2] == 0x0),
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[24:32]))
).Elif((sbus_last_pa[0:2] == 0x1),
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[16:24]))
).Elif((sbus_last_pa[0:2] == 0x2),
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[ 8:16]))
).Elif((sbus_last_pa[0:2] == 0x3),
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[ 0: 8]))
),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE),
NextState("Slave_Do_Read")
)
slave_fsm.act("Slave_Do_Read",
#NextValue(self.led_display.value, Cat(Signal(8, reset = 0x04), self.led_display.value[8:40])),
NextValue(sbus_oe_data, 0),

45
sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
View File

@@ -10,7 +10,7 @@ from litex.soc.integration.builder import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.clock import *
from litex.soc.cores.led import LedChaser
from litex_boards.platforms import ztex213
import ztex213_sbus
from migen.genlib.fifo import *
from litedram.modules import MT41J128M16
@@ -20,32 +20,6 @@ from sbus_to_fpga_fsm import *;
import sbus_to_fpga_export;
_sbus_sbus = [
("SBUS_3V3_CLK", 0, Pins("D15"), IOStandard("lvttl")),
("SBUS_3V3_ASs", 0, Pins("T4"), IOStandard("lvttl")),
("SBUS_3V3_BGs", 0, Pins("T6"), IOStandard("lvttl")),
("SBUS_3V3_BRs", 0, Pins("R6"), IOStandard("lvttl")),
("SBUS_3V3_ERRs", 0, Pins("V2"), IOStandard("lvttl")),
("SBUS_DATA_OE_LED", 0, Pins("U1"), IOStandard("lvttl")),
("SBUS_DATA_OE_LED_2", 0, Pins("T3"), IOStandard("lvttl")),
("SBUS_3V3_RSTs", 0, Pins("U2"), IOStandard("lvttl")),
("SBUS_3V3_SELs", 0, Pins("K6"), IOStandard("lvttl")),
("SBUS_3V3_INT1s", 0, Pins("R3"), IOStandard("lvttl")),
("SBUS_3V3_INT7s", 0, Pins("N5"), IOStandard("lvttl")),
("SBUS_3V3_PPRD", 0, Pins("N6"), IOStandard("lvttl")),
("SBUS_OE", 0, Pins("P5"), IOStandard("lvttl")),
("SBUS_3V3_ACKs", 0, Pins("M6 L6 N4"), IOStandard("lvttl")),
("SBUS_3V3_SIZ", 0, Pins("R7 U3 V1"), IOStandard("lvttl")),
("SBUS_3V3_D", 0, Pins("J18 K16 J17 K15 K13 J15 J13 J14 H14 H17 G14 G17 G16 G18 H16 F18 F16 E18 F15 D18 E17 G13 D17 F13 F14 E16 E15 C17 C16 A18 B18 C15"), IOStandard("lvttl")),
("SBUS_3V3_PA", 0, Pins("B16 B17 D14 C14 D12 A16 A15 B14 B13 B12 C12 A14 A13 B11 A11 M4 R2 M3 P2 M2 N2 K5 N1 L4 M1 L3 L1 K3"), IOStandard("lvttl")),
]
_usb_io = [
("usb", 0,
Subsignal("dp", Pins("V9")), # Serial TX
Subsignal("dm", Pins("U9")), # Serial RX
IOStandard("LVCMOS33"))
]
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
@@ -115,9 +89,9 @@ class SBusFPGA(SoCCore):
self.sys_clk_freq = sys_clk_freq = 100e6 ## 25e6
self.platform = platform = ztex213.Platform(variant="ztex2.13a", expansion="sbus")
self.platform.add_extension(_sbus_sbus)
self.platform.add_extension(_usb_io)
self.platform = platform = ztex213_sbus.Platform(variant="ztex2.13a")
self.platform.add_extension(ztex213_sbus._usb_io)
SoCCore.__init__(self,
platform=platform,
sys_clk_freq=sys_clk_freq,
@@ -131,6 +105,8 @@ class SBusFPGA(SoCCore):
# the physical address here are used as offset in the SBus
# reserved area of 256 MiB
# Anything at 0x10000000 is therefore unreachable directly
# The position of the 'usb_fake_dma' is so it overlaps
# the virtual address space used by NetBSD DMA allocators
wb_mem_map = {
"prom": 0x00000000,
"csr" : 0x00040000,
@@ -151,7 +127,7 @@ class SBusFPGA(SoCCore):
self.add_usb_host(pads=platform.request("usb"), usb_clk_freq=48e6)
#self.comb += self.cpu.interrupt[16].eq(self.usb_host.interrupt) #fixme: need to deal with interrupts
self.add_ram(name="usb_shared_mem", origin=self.mem_map["usb_shared_mem"], size=2**16)
# self.add_ram(name="usb_shared_mem", origin=self.mem_map["usb_shared_mem"], size=2**16)
pad_SBUS_3V3_INT1s = platform.request("SBUS_3V3_INT1s")
SBUS_3V3_INT1s_o = Signal(reset=1)
@@ -170,7 +146,7 @@ class SBusFPGA(SoCCore):
prom_file = "prom_migen.fc"
prom_data = soc_core.get_mem_data(prom_file, "big")
prom = Array(prom_data)
# prom = Array(prom_data)
#print("\n****************************************\n")
#for i in range(len(prom)):
# print(hex(prom[i]))
@@ -197,7 +173,6 @@ class SBusFPGA(SoCCore):
self.submodules.wishbone_slave_sys = wishbone.WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_sbus, cd_master="sys", cd_slave="sbus")
_sbus_bus = SBusFPGABus(platform=self.platform,
prom=prom,
hold_reset=hold_reset,
wishbone_slave=wishbone_slave_sbus,
wishbone_master=self.wishbone_master_sbus)
@@ -206,8 +181,6 @@ class SBusFPGA(SoCCore):
self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
#self.add_sdcard()
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
@@ -218,6 +191,8 @@ class SBusFPGA(SoCCore):
module = MT41J128M16(sys_clk_freq, "1:4"),
l2_cache_size = 0
)
self.add_sdcard()
def main():
parser = argparse.ArgumentParser(description="SbusFPGA")

161
sbus-to-ztex-gateware-migen/ztex213_sbus.py Normal file
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@@ -0,0 +1,161 @@
#
# This file is part of LiteX-Boards.
#
# Support for the ZTEX USB-FGPA Module 2.13:
# <https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html>
# With (no-so-optional) expansion, either the ZTEX Debug board:
# <https://www.ztex.de/usb-fpga-2/debug.e.html>
# Or the SBusFPGA adapter board:
# <https://github.com/rdolbeau/SBusFPGA>
#
# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020-2021 Romain Dolbeau <romain@dolbeau.org>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
## 48 MHz clock reference
("clk48", 0, Pins("P15"), IOStandard("LVCMOS33")),
## embedded 256 MiB DDR3 DRAM
("ddram", 0,
Subsignal("a", Pins("C5 B6 C7 D5 A3 E7 A4 C6", "A6 D8 B2 A5 B3 B7"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("E5 A1 E6"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("E3"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("D3"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("D4"), IOStandard("SSTL135")),
# Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
Subsignal("dm", Pins("G1 G6"), IOStandard("SSTL135")),
Subsignal("dq", Pins(
"H1 F1 E2 E1 F4 C1 F3 D2",
"G4 H5 G3 H6 J2 J3 K1 K2"),
IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("H2 J4"),
IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("G2 H4"),
IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("C4"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("B4"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("B1"), IOStandard("SSTL135")),
Subsignal("odt", Pins("F5"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("J5"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
]
_sbus_io = [
## leds on the SBus board
("user_led", 0, Pins("U8"), IOStandard("lvcmos33")), #LED0
("user_led", 1, Pins("U7"), IOStandard("lvcmos33")), #LED1
("user_led", 2, Pins("U6"), IOStandard("lvcmos33")), #LED2
("user_led", 3, Pins("T8"), IOStandard("lvcmos33")), #LED3
("user_led", 4, Pins("P4"), IOStandard("lvcmos33")), #LED4
("user_led", 5, Pins("P3"), IOStandard("lvcmos33")), #LED5
("user_led", 6, Pins("T1"), IOStandard("lvcmos33")), #LED6
("user_led", 7, Pins("R1"), IOStandard("lvcmos33")), #LED7
#("user_led", 8, Pins("U1"), IOStandard("lvcmos33")), #SBUS_DATA_OE_LED
#("user_led", 9, Pins("T3"), IOStandard("lvcmos33")), #SBUS_DATA_OE_LED_2
## serial header for console
("serial", 0,
Subsignal("tx", Pins("V9")), # FIXME: might be the other way round
Subsignal("rx", Pins("U9")),
IOStandard("LVCMOS33")
),
## sdcard connector
("spisdcard", 0,
Subsignal("clk", Pins("R8")),
Subsignal("mosi", Pins("T5"), Misc("PULLUP")),
Subsignal("cs_n", Pins("V6"), Misc("PULLUP")),
Subsignal("miso", Pins("V5"), Misc("PULLUP")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("data", Pins("V5 V4 V7 V6"), Misc("PULLUP")),
Subsignal("cmd", Pins("T5"), Misc("PULLUP")),
Subsignal("clk", Pins("R8")),
#Subsignal("cd", Pins("V6")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
]
_sbus_sbus = [
("SBUS_3V3_CLK", 0, Pins("D15"), IOStandard("lvttl")),
("SBUS_3V3_ASs", 0, Pins("T4"), IOStandard("lvttl")),
("SBUS_3V3_BGs", 0, Pins("T6"), IOStandard("lvttl")),
("SBUS_3V3_BRs", 0, Pins("R6"), IOStandard("lvttl")),
("SBUS_3V3_ERRs", 0, Pins("V2"), IOStandard("lvttl")),
("SBUS_DATA_OE_LED", 0, Pins("U1"), IOStandard("lvttl")),
("SBUS_DATA_OE_LED_2", 0, Pins("T3"), IOStandard("lvttl")),
("SBUS_3V3_RSTs", 0, Pins("U2"), IOStandard("lvttl")),
("SBUS_3V3_SELs", 0, Pins("K6"), IOStandard("lvttl")),
("SBUS_3V3_INT1s", 0, Pins("R3"), IOStandard("lvttl")),
("SBUS_3V3_INT7s", 0, Pins("N5"), IOStandard("lvttl")),
("SBUS_3V3_PPRD", 0, Pins("N6"), IOStandard("lvttl")),
("SBUS_OE", 0, Pins("P5"), IOStandard("lvttl")),
("SBUS_3V3_ACKs", 0, Pins("M6 L6 N4"), IOStandard("lvttl")),
("SBUS_3V3_SIZ", 0, Pins("R7 U3 V1"), IOStandard("lvttl")),
("SBUS_3V3_D", 0, Pins("J18 K16 J17 K15 K13 J15 J13 J14 H14 H17 G14 G17 G16 G18 H16 F18 F16 E18 F15 D18 E17 G13 D17 F13 F14 E16 E15 C17 C16 A18 B18 C15"), IOStandard("lvttl")),
("SBUS_3V3_PA", 0, Pins("B16 B17 D14 C14 D12 A16 A15 B14 B13 B12 C12 A14 A13 B11 A11 M4 R2 M3 P2 M2 N2 K5 N1 L4 M1 L3 L1 K3"), IOStandard("lvttl")),
]
# reusing the UART pins !!!
_usb_io = [
("usb", 0,
Subsignal("dp", Pins("V9")), # Serial TX
Subsignal("dm", Pins("U9")), # Serial RX
IOStandard("LVCMOS33"))
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, variant="ztex2.13a"):
device = {
"ztex2.13a": "xc7a35tcsg324-1",
"ztex2.13b": "xc7a50tcsg324-1", #untested
"ztex2.13b2": "xc7a50tcsg324-1", #untested
"ztex2.13c": "xc7a75tcsg324-2", #untested
"ztex2.13d": "xc7a100tcsg324-2" #untested
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
self.add_extension(_sbus_io)
self.add_extension(_sbus_sbus)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS true [current_design]",
"set_property BITSTREAM.GENERAL.CRC DISABLE [current_design]",
"set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
"set_property CFGBVS VCCO [current_design]"
# , "set_property STEPS.SYNTH_DESIGN.ARGS.DIRECTIVE AreaOptimized_high [get_runs synth_1]"
]
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) #FIXME
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)