Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main
This commit is contained in:
Romain Dolbeau
commit
97f688dd7d
File diff suppressed because it is too large
Load Diff
@ -5,9 +5,18 @@
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*/
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#define HRES 1280 // FIXME : should be generated
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#ifndef HRES
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#define HRES 1280
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#warning "Using default HRES"
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#endif
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#ifndef VRES
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#define VRES 1024
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#define BASE_FB 0x8FE00000 // FIXME : should be generated ; 2+ MiB of SDRAM as framebuffer
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#warning "Using default VRES"
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#endif
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#ifndef BASE_FB
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#define BASE_FB 0x8FE00000 // FIXME : should be generated ; 2+ MiB of SDRAM as framebuffer
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#warning "Using default BASE_FB"
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#endif
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#define BASE_ROM 0x00410000 // FIXME : should be generated ; 4-64 KiB of Wishbone ROM ? ; also in the LDS file ; also in the Vex config
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@ -369,7 +378,7 @@ struct cg6_fbc {
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void from_reset(void) __attribute__ ((noreturn)); // nothrow,
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static inline void flush_cache(void) {
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//asm volatile(".word 0x0000500F\n"); // flush the Dcache so that we get updated data
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asm volatile(".word 0x0000500F\n"); // flush the Dcache so that we get updated data
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}
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typedef unsigned int unsigned_param_type;
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@ -1,5 +1,9 @@
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#!/bin/bash -x
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HRES=${1:-1280}
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VRES=${2:-1024}
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BASE_FB=${3:-0x8FE00000}
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GCCDIR=~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14
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GCCPFX=riscv64-unknown-elf-
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GCCLINK=${GCCDIR}/bin/${GCCPFX}gcc
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@ -16,9 +20,11 @@ OBJCOPY=${GCCDIR}/bin/${GCCPFX}objcopy
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OPT=-Os #-fno-inline
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ARCH=rv32i_zba_zbb_zbt
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PARAM="-DHRES=${HRES} -DVRES=${VRES} -DBASE_FB=${BASE_FB}"
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if test "x$1" != "xASM"; then
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$GCC $OPT -S -o blit.s -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.c
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$GCC $OPT -S -o blit.s $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.c
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fi
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$GCC $OPT -c -o blit.o -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.s &&
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$GCCLINK $OPT -o blit -march=$ARCH -mabi=ilp32 -T blit.lds -nostartfiles blit.o &&
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$GCC $OPT -c -o blit.o $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.s &&
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$GCCLINK $OPT -o blit $PARAM -march=$ARCH -mabi=ilp32 -T blit.lds -nostartfiles blit.o &&
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$OBJCOPY -O binary -j .text -j .rodata blit blit.raw
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@ -28,7 +28,15 @@ cg3_timings = {
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}
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def cg3_rounded_size(hres, vres):
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return int(1048576 * ceil(((hres * vres) + 0) / 1048576))
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mib = int(ceil(((hres * vres) + 0) / 1048576))
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if (mib == 3):
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mib = 4
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if (mib > 4 and mib < 8):
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mib = 8
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if (mib > 8 or mib < 1):
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print(f"{mib} mebibytes framebuffer not supported")
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assert(False)
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return int(1048576 * mib)
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class VideoFrameBuffer256c(Module, AutoCSR):
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"""Video FrameBuffer256c"""
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@ -145,24 +153,44 @@ class VideoFrameBuffer256c(Module, AutoCSR):
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hwcursory_buf.eq(vtg_sink.hwcursory),
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]
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vga_sync += [
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source_out_de.eq(source_buf_de),
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source_out_hsync.eq(source_buf_hsync),
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source_out_vsync.eq(source_buf_vsync),
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source_out_valid.eq(source_buf_valid),
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#source_buf_ready.eq(source_out_ready), # ready flow the other way
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]
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if (hwcursor):
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source_mid_valid = Signal()
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source_mid_de = Signal()
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source_mid_hsync = Signal()
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source_mid_vsync = Signal()
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data_mid = Signal(8)
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hwcursor_color_idx = Signal(2)
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# first cycle, buffer everything and look up the cursor overlay color
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vga_sync += [
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If(hwcursor_buf & (overlay[0][hwcursory_buf][hwcursorx_buf] | overlay[1][hwcursory_buf][hwcursorx_buf]),
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source_out_r.eq(omap[0][Cat(overlay[0][hwcursory_buf][hwcursorx_buf], overlay[1][hwcursory_buf][hwcursorx_buf])]),
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source_out_g.eq(omap[1][Cat(overlay[0][hwcursory_buf][hwcursorx_buf], overlay[1][hwcursory_buf][hwcursorx_buf])]),
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source_out_b.eq(omap[2][Cat(overlay[0][hwcursory_buf][hwcursorx_buf], overlay[1][hwcursory_buf][hwcursorx_buf])]),
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).Elif(source_buf_de,
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source_out_r.eq(clut[0][data_buf]),
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source_out_g.eq(clut[1][data_buf]),
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source_out_b.eq(clut[2][data_buf])
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source_mid_de.eq(source_buf_de),
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source_mid_hsync.eq(source_buf_hsync),
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source_mid_vsync.eq(source_buf_vsync),
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source_mid_valid.eq(source_buf_valid),
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data_mid.eq(data_buf),
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If(hwcursor_buf,
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hwcursor_color_idx.eq(Cat(overlay[0][hwcursory_buf][hwcursorx_buf], overlay[1][hwcursory_buf][hwcursorx_buf])),
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).Else(
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hwcursor_color_idx.eq(0),
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)
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]
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#second cycle, produce the pixel by doing CLUT lookup
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vga_sync += [
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source_out_de.eq(source_mid_de),
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source_out_hsync.eq(source_mid_hsync),
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source_out_vsync.eq(source_mid_vsync),
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source_out_valid.eq(source_mid_valid),
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#source_buf_ready.eq(source_out_ready), # ready flow the other way
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If(hwcursor_color_idx != 0,
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source_out_r.eq(omap[0][hwcursor_color_idx]),
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source_out_g.eq(omap[1][hwcursor_color_idx]),
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source_out_b.eq(omap[2][hwcursor_color_idx]),
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).Elif(source_mid_de,
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source_out_r.eq(clut[0][data_mid]),
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source_out_g.eq(clut[1][data_mid]),
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source_out_b.eq(clut[2][data_mid])
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).Else(
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source_out_r.eq(0),
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source_out_g.eq(0),
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@ -171,6 +199,11 @@ class VideoFrameBuffer256c(Module, AutoCSR):
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]
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else:
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vga_sync += [
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source_out_de.eq(source_buf_de),
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source_out_hsync.eq(source_buf_hsync),
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source_out_vsync.eq(source_buf_vsync),
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source_out_valid.eq(source_buf_valid),
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#source_buf_ready.eq(source_out_ready), # ready flow the other way
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If(source_buf_de,
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source_out_r.eq(clut[0][data_buf]),
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source_out_g.eq(clut[1][data_buf]),
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@ -5,20 +5,24 @@ from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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class CG6Accel(Module): # AutoCSR ?
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def __init__(self, platform):
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#from cg6_blit import CG6Blit
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class CG6Accel(Module): # AutoCSR ?
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def __init__(self, soc, base_fb, hres, vres):
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platform = soc.platform
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# for FBC and TEC - where we just ignore TEC
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self.bus = bus = wishbone.Interface()
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COORD_BITS=12
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self.COORD_BITS = COORD_BITS = 12
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fbc_config = Signal(32, reset = (0x60000000)) # bit 11-12 are for resolution, see the GX manual
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fbc_mode = Signal(32)
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fbc_clip = Signal(32)
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fbc_s = Signal(32)
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#fbc_font = Signal(32)
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fbc_x = Array(Signal(COORD_BITS) for a in range(0, 4))
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fbc_y = Array(Signal(COORD_BITS) for a in range(0, 4))
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self.fbc_x = fbc_x = Array(Signal(COORD_BITS) for a in range(0, 4))
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self.fbc_y = fbc_y = Array(Signal(COORD_BITS) for a in range(0, 4))
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fbc_offx = Signal(COORD_BITS)
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fbc_offy = Signal(COORD_BITS)
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fbc_incx = Signal(COORD_BITS)
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@ -29,21 +33,23 @@ class CG6Accel(Module): # AutoCSR ?
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fbc_clipmaxy = Signal(COORD_BITS+1) # need the 13th bit as X11 uses 4096 for clipmaxx (console uses 4095)
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fbc_fg = Signal(8)
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fbc_bg = Signal(8)
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fbc_alu = Signal(32)
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fbc_pm = Signal(8)
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self.fbc_alu = fbc_alu = Signal(32)
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self.fbc_pm = fbc_pm = Signal(8)
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fbc_arectx = Signal(COORD_BITS)
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fbc_arecty = Signal(COORD_BITS)
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# extra stuff for the Vex core
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fbc_arectx_prev = Signal(COORD_BITS) # after fbc_arecty (600) - R/O
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fbc_arecty_prev = Signal(COORD_BITS) # after fbc_arectx_prev (601) - R/O
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fbc_r5_cmd = Signal(32) # to communicate with Vex (602)
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self.fbc_r5_cmd = fbc_r5_cmd = Signal(32) # to communicate with Vex (602)
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fbc_r5_status = Array(Signal(32) for a in range(0, 4))
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fbc_next_font = Signal(32)
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fbc_next_x0 = Signal(COORD_BITS)
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fbc_next_x1 = Signal(COORD_BITS)
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fbc_next_y0 = Signal(COORD_BITS)
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#self.submodules.cg6_blit = CG6Blit(accel = self, soc = soc, base_fb = base_fb, hres = hres, vres = vres)
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# do-some-work flags
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fbc_do_draw = Signal()
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fbc_do_blit = Signal()
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@ -256,8 +262,8 @@ class CG6Accel(Module): # AutoCSR ?
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#timeout_rst = 0xFFFFFFF
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#timeout = Signal(28, reset = timeout_rst)
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#pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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#self.comb += pad_SBUS_DATA_OE_LED.eq(~local_reset)
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pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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self.comb += pad_SBUS_DATA_OE_LED.eq(~local_reset)
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_r5_cmd[1]) # blitting
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_pm != 0) # planemasking
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fifo_overflow)
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@ -267,11 +273,11 @@ class CG6Accel(Module): # AutoCSR ?
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_do_draw & fbc_s[GX_INPROGRESS_BIT])
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_do_blit & fbc_s[GX_INPROGRESS_BIT])
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self.sync += fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable)
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self.sync += fbc_s[27].eq(fbc_do_draw)
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self.sync += fbc_s[26].eq(fbc_do_blit)
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self.sync += fbc_s[25].eq(self.fbc_fifo_font.readable)
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self.sync += fbc_s[24].eq(~local_reset)
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#self.sync += fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable)
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#self.sync += fbc_s[27].eq(fbc_do_draw)
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#self.sync += fbc_s[26].eq(fbc_do_blit)
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#self.sync += fbc_s[25].eq(self.fbc_fifo_font.readable)
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#self.sync += fbc_s[24].eq(~local_reset)
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#self.sync += fbc_s[0].eq(draw_blit_overflow)
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#fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable)
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@ -324,6 +330,8 @@ class CG6Accel(Module): # AutoCSR ?
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#fbc_s[GX_FULL_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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##self.cg6_blit.go.eq(1),
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)
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#).Elif((timeout == 0) & fbc_s[GX_INPROGRESS_BIT], # OUPS
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# fbc_r5_cmd.eq(0),
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@ -353,9 +361,9 @@ class CG6Accel(Module): # AutoCSR ?
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i_iBusWishbone_DAT_MISO = ibus.dat_r,
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o_iBusWishbone_DAT_MOSI = ibus.dat_w,
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o_iBusWishbone_SEL = ibus.sel,
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#i_iBusWishbone_ERR = ibus.err,
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#o_iBusWishbone_CTI = ibus.cti,
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#o_iBusWishbone_BTE = ibus.bte,
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i_iBusWishbone_ERR = ibus.err,
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o_iBusWishbone_CTI = ibus.cti,
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o_iBusWishbone_BTE = ibus.bte,
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o_dBusWishbone_CYC = dbus.cyc,
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o_dBusWishbone_STB = dbus.stb,
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i_dBusWishbone_ACK = dbus.ack,
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@ -38,14 +38,6 @@ FBC_ROM_ADDR_PFX = Signal(12, reset = 0x041)
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#FBC_RAM_ADDR_PFX = Signal(12, reset = 0x042)
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CG6_FBC_ADDR_PFX = Signal(12, reset = 0x070)
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ADDR_BIGPFX_HIGH = ADDR_PHYS_HIGH
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ADDR_BIGPFX_LOW = 20 ## 1 MiB per bigprefix
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ADDR_BIGPFX_LENGTH = 8 #(1 + ADDR_BIGPFX_HIGH - ADDR_BIGPFX_LOW)
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CG3_PIXELS_ADDR_BIGPFX = Signal(8, reset = 0x08) # cg3_pixels, remapped, first MiB, LE
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CG3_PIXELS_ADDR_BIGVAL = 0x08
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CG3_PIXELS_ADDR2_BIGPFX = Signal(8, reset = 0x09) # cg3_pixels, remapped, second MiB, LE
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CG3_PIXELS_ADDR2_BIGVAL = 0x09
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|
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wishbone_default_timeout = 120 ##
|
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sbus_default_timeout = 50 ## must be below 255/2 (two waits)
|
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sbus_default_master_throttle = 3
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@ -199,15 +191,34 @@ class SBusFPGABus(Module):
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self.fromsbus_fifo = fromsbus_fifo
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self.fromsbus_req_fifo = fromsbus_req_fifo
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|
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if (cg3_fb_size <= 1048576): #round up to 1 MiB
|
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if (cg3_fb_size == 1*1048576):
|
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CG3_UPPER_BITS=12
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CG3_KEPT_UPPER_BIT=20
|
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elif (cg3_fb_size == (2*1048576)):
|
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CG3_PIXELS_ADDR_BIGVAL = 0x08>>0
|
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CG3_PIXELS_ADDR_BIGPFX = Signal(8, reset = CG3_PIXELS_ADDR_BIGVAL)
|
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elif (cg3_fb_size == 2*1048576):
|
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CG3_UPPER_BITS=11
|
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CG3_KEPT_UPPER_BIT=21
|
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CG3_PIXELS_ADDR_BIGVAL = 0x08>>1
|
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CG3_PIXELS_ADDR_BIGPFX = Signal(7, reset = CG3_PIXELS_ADDR_BIGVAL)
|
||||
elif (cg3_fb_size == 4*1048576):
|
||||
CG3_UPPER_BITS=10
|
||||
CG3_KEPT_UPPER_BIT=22
|
||||
CG3_PIXELS_ADDR_BIGVAL = 0x08>>2
|
||||
CG3_PIXELS_ADDR_BIGPFX = Signal(6, reset = CG3_PIXELS_ADDR_BIGVAL)
|
||||
elif (cg3_fb_size == 8*1048576):
|
||||
CG3_UPPER_BITS=9
|
||||
CG3_KEPT_UPPER_BIT=23
|
||||
CG3_PIXELS_ADDR_BIGVAL = 0x08>>3
|
||||
CG3_PIXELS_ADDR_BIGPFX = Signal(5, reset = CG3_PIXELS_ADDR_BIGVAL)
|
||||
else:
|
||||
print(f"CG3 configuration ({cg3_fb_size//1048576} MiB) not yet supported\n")
|
||||
print(f"{cg3_fb_size//1048576} mebibytes framebuffer not supported")
|
||||
assert(False)
|
||||
|
||||
ADDR_BIGPFX_HIGH = ADDR_PHYS_HIGH
|
||||
ADDR_BIGPFX_LOW = CG3_KEPT_UPPER_BIT ## x MiB per bigprefix
|
||||
ADDR_BIGPFX_LENGTH = (1 + ADDR_BIGPFX_HIGH - ADDR_BIGPFX_LOW)
|
||||
|
||||
CG3_REMAPPED_BASE=cg3_base >> CG3_KEPT_UPPER_BIT
|
||||
|
||||
print(f"CG3 remapping: {cg3_fb_size//1048576} Mib starting at prefix {CG3_REMAPPED_BASE:x} ({(CG3_REMAPPED_BASE<<CG3_KEPT_UPPER_BIT):x})")
|
||||
@ -482,14 +493,12 @@ class SBusFPGABus(Module):
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
If(self.wishbone_master.cyc == 0,
|
||||
NextValue(self.wishbone_master.cyc, 1),
|
||||
@ -500,15 +509,11 @@ class SBusFPGABus(Module):
|
||||
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
NextValue(wishbone_master_timeout, wishbone_default_timeout),
|
||||
NextValue(sbus_slave_timeout, sbus_default_timeout),
|
||||
@ -518,13 +523,10 @@ class SBusFPGABus(Module):
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
NextValue(sbus_slave_timeout, sbus_default_timeout),
|
||||
NextState("Slave_Ack_Read_Reg_Burst_Wait_For_Wishbone")
|
||||
@ -546,14 +548,12 @@ class SBusFPGABus(Module):
|
||||
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
If(self.wishbone_master.cyc == 0,
|
||||
NextValue(self.wishbone_master.cyc, 1),
|
||||
@ -564,15 +564,11 @@ class SBusFPGABus(Module):
|
||||
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
NextValue(wishbone_master_timeout, wishbone_default_timeout),
|
||||
NextValue(sbus_slave_timeout, sbus_default_timeout),
|
||||
@ -582,13 +578,10 @@ class SBusFPGABus(Module):
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
NextValue(sbus_slave_timeout, sbus_default_timeout),
|
||||
NextState("Slave_Ack_Read_Reg_Byte_Wait_For_Wishbone")
|
||||
@ -616,14 +609,12 @@ class SBusFPGABus(Module):
|
||||
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
If(self.wishbone_master.cyc == 0,
|
||||
NextValue(self.wishbone_master.cyc, 1),
|
||||
@ -634,15 +625,11 @@ class SBusFPGABus(Module):
|
||||
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
NextValue(wishbone_master_timeout, wishbone_default_timeout),
|
||||
NextValue(sbus_slave_timeout, sbus_default_timeout),
|
||||
@ -652,13 +639,10 @@ class SBusFPGABus(Module):
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
NextValue(sbus_slave_timeout, sbus_default_timeout),
|
||||
NextState("Slave_Ack_Read_Reg_HWord_Wait_For_Wishbone")
|
||||
@ -701,23 +685,18 @@ class SBusFPGABus(Module):
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM
|
||||
# next remap 8 MiB to Y MiB of SDRAM
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
If(~self.wishbone_master.cyc,
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
|
||||
@ -747,23 +726,18 @@ class SBusFPGABus(Module):
|
||||
NextValue(sbus_oe_master_in, 1),
|
||||
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM
|
||||
# next remap 8 MiB to Y MiB of SDRAM
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
If(~self.wishbone_master.cyc,
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_BYTE),
|
||||
@ -799,23 +773,18 @@ class SBusFPGABus(Module):
|
||||
NextState("Slave_Error")
|
||||
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
|
||||
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
|
||||
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
|
||||
],
|
||||
# next remap X MiB to last MiB of SDRAM
|
||||
# next remap 8 MiB to Y MiB of SDRAM
|
||||
CG3_PIXELS_ADDR_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
CG3_PIXELS_ADDR2_BIGVAL: [
|
||||
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
|
||||
],
|
||||
}),
|
||||
If(~self.wishbone_master.cyc,
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_HWORD),
|
||||
|
||||
@ -271,7 +271,7 @@ class SBusFPGA(SoCCore):
|
||||
"cg6_accel_ram": 0x00420000, # R5 microcode working space (stack)
|
||||
"cg6_fbc": 0x00700000, # required for compatibility
|
||||
#"cg6_tec": 0x00701000, # required for compatibility
|
||||
"cg3_pixels": 0x00800000, # required for compatibility, 1-2 MiB for now (2nd MiB is 0x00900000) (cg3 and cg6 idem)
|
||||
"cg3_pixels": 0x00800000, # required for compatibility, 1/2/4/8 MiB for now (up to 0x00FFFFFF inclusive) (cg3 and cg6 idem)
|
||||
"main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible),
|
||||
"video_framebuffer":0x80000000 + 0x10000000 - cg3_fb_size, # FIXME
|
||||
"usb_fake_dma": 0xfc000000, # required to match DVMA virtual addresses
|
||||
@ -350,6 +350,7 @@ class SBusFPGA(SoCCore):
|
||||
if (cg3 or cg6):
|
||||
if (avail_sdram >= cg3_fb_size):
|
||||
avail_sdram = avail_sdram - cg3_fb_size
|
||||
base_fb = self.wb_mem_map["main_ram"] + avail_sdram
|
||||
else:
|
||||
print("***** ERROR ***** Can't have a FrameBuffer without main ram\n")
|
||||
assert(False)
|
||||
@ -411,7 +412,7 @@ class SBusFPGA(SoCCore):
|
||||
version=version,
|
||||
burst_size=burst_size,
|
||||
cg3_fb_size=cg3_fb_size,
|
||||
cg3_base=(self.wb_mem_map["main_ram"] + avail_sdram))
|
||||
cg3_base=base_fb)
|
||||
#self.submodules.sbus_bus = _sbus_bus
|
||||
self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus)
|
||||
self.submodules.sbus_bus_stat = SBusFPGABusStat(soc = self, sbus_bus = self.sbus_bus)
|
||||
@ -456,7 +457,7 @@ class SBusFPGA(SoCCore):
|
||||
|
||||
|
||||
if (cg6):
|
||||
self.submodules.cg6_accel = cg6_accel.CG6Accel(self.platform)
|
||||
self.submodules.cg6_accel = cg6_accel.CG6Accel(soc = self, base_fb = base_fb, hres = hres, vres = vres)
|
||||
self.bus.add_slave("cg6_fbc", self.cg6_accel.bus, SoCRegion(origin=self.mem_map.get("cg6_fbc", None), size=0x2000, cached=False))
|
||||
self.bus.add_slave("cg6_fhc", self.cg6.bus2, SoCRegion(origin=self.mem_map.get("cg6_fhc", None), size=0x2000, cached=False))
|
||||
self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus)
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user