USB configurability
This commit is contained in:
Romain Dolbeau
parent
e352323ae3
commit
984abbc656
@ -32,7 +32,7 @@ import sbus_to_fpga_export;
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq, usb=True):
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self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by SBus (via pll), SoC/Wishbone main clock
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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@ -41,7 +41,8 @@ class _CRG(Module):
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self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset, we don't want the delay after a warm reset)
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self.clock_domains.cd_sbus = ClockDomain() # 16.67-25 MHz SBus, reset'ed by SBus, native SBus clock domain
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# self.clock_domains.cd_por = ClockDomain() # 48 MHz native, reset'ed by SBus, power-on-reset timer
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self.clock_domains.cd_usb = ClockDomain() # 48 MHZ PLL, reset'ed by SBus (via pll), for USB controller
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if (usb):
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self.clock_domains.cd_usb = ClockDomain() # 48 MHZ PLL, reset'ed by SBus (via pll), for USB controller
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self.clock_domains.cd_clk50 = ClockDomain() # 50 MHz (gated) for curve25519engine -> eng_clk
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#self.clock_domains.cd_clk100 = ClockDomain() # 100 MHz for curve25519engine -> sys_clk
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self.clock_domains.cd_clk100_gated = ClockDomain() # 100 MHz (gated) for curve25519engine -> mul_clk
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@ -121,14 +122,15 @@ class _CRG(Module):
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# self.comb += pll.reset.eq(~por_done | ~rst_sbus)
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# USB
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self.submodules.usb_pll = usb_pll = S7MMCM(speedgrade=-1)
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#usb_pll.register_clkin(clk48, 48e6)
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usb_pll.register_clkin(self.clk48_bufg, 48e6)
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usb_pll.create_clkout(self.cd_usb, 48e6, margin = 0)
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platform.add_platform_command("create_generated_clock -name usbclk [get_pins {{MMCME2_ADV_2/CLKOUT0}}]")
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self.comb += usb_pll.reset.eq(~rst_sbus) # | ~por_done
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platform.add_false_path_constraints(self.cd_sys.clk, self.cd_usb.clk)
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if (usb):
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self.submodules.usb_pll = usb_pll = S7MMCM(speedgrade=-1)
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#usb_pll.register_clkin(clk48, 48e6)
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usb_pll.register_clkin(self.clk48_bufg, 48e6)
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usb_pll.create_clkout(self.cd_usb, 48e6, margin = 0)
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platform.add_platform_command("create_generated_clock -name usbclk [get_pins {{MMCME2_ADV_2/CLKOUT0}}]")
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self.comb += usb_pll.reset.eq(~rst_sbus) # | ~por_done
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platform.add_false_path_constraints(self.cd_sys.clk, self.cd_usb.clk)
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self.submodules.pll_idelay = pll_idelay = S7MMCM(speedgrade=-1)
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#pll_idelay.register_clkin(clk48, 48e6)
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pll_idelay.register_clkin(self.clk48_bufg, 48e6)
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@ -139,7 +141,7 @@ class _CRG(Module):
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class SBusFPGA(SoCCore):
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def __init__(self, version, **kwargs):
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def __init__(self, version, usb, **kwargs):
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print(f"Building SBusFPGA for board version {version}")
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kwargs["cpu_type"] = "None"
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@ -180,7 +182,7 @@ class SBusFPGA(SoCCore):
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"usb_fake_dma": 0xfc000000,
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}
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self.mem_map.update(wb_mem_map)
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self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq)
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self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, usb=usb)
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self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6) # SBus max
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if (version == "V1.0"):
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@ -188,18 +190,18 @@ class SBusFPGA(SoCCore):
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pads = platform.request("SBUS_DATA_OE_LED_2"), #platform.request("user_led", 7),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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self.add_usb_host(pads=platform.request("usb"), usb_clk_freq=48e6)
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#self.comb += self.cpu.interrupt[16].eq(self.usb_host.interrupt) #fixme: need to deal with interrupts
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# self.add_ram(name="usb_shared_mem", origin=self.mem_map["usb_shared_mem"], size=2**16)
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pad_SBUS_3V3_INT1s = platform.request("SBUS_3V3_INT1s")
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SBUS_3V3_INT1s_o = Signal(reset=1)
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# the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt)
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self.comb += pad_SBUS_3V3_INT1s.eq(SBUS_3V3_INT1s_o)
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self.comb += SBUS_3V3_INT1s_o.eq(~self.usb_host.interrupt) ##
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if (usb):
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self.add_usb_host(pads=platform.request("usb"), usb_clk_freq=48e6)
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if (version == "V1.0"):
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pad_usb_interrupt = platform.request("SBUS_3V3_INT1s") ## only one usable
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elif (version == "V1.2"):
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pad_usb_interrupt = platform.request("SBUS_3V3_INT3s") ## can be 1-6, beware others
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sig_usb_interrupt = Signal(reset=1)
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# the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt)
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self.comb += pad_usb_interrupt.eq(sig_usb_interrupt)
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self.comb += sig_usb_interrupt.eq(~self.usb_host.interrupt) ##
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#pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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#SBUS_DATA_OE_LED_o = Signal()
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@ -284,7 +286,9 @@ class SBusFPGA(SoCCore):
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self.submodules.sbus_bus_stat = SBusFPGABusStat(sbus_bus = self.sbus_bus)
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self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
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self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
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if (usb):
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self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
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#self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_slave)
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#self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_slave)
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@ -295,6 +299,7 @@ class SBusFPGA(SoCCore):
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# beware the naming, as 'clk50' 'sysclk' 'clk200' are used in the original platform constraints
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# the local engine.py was slightly modified to have configurable names, so we can have 'clk50', 'clk100', 'clk200'
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# Beware that Engine implicitely runs in 'sys' by default, need to rename that one as well
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# Actually renaming 'sys' doesn't work - unless we can CDC the CSRs as well
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self.submodules.curve25519engine = ClockDomainsRenamer({"eng_clk":"clk50", "rf_clk":"clk200", "mul_clk":"clk100_gated"})(Engine(platform=platform,prefix=self.mem_map.get("curve25519engine", None))) # , "sys":"clk100"
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#self.submodules.curve25519engine_wishbone_cdc = wishbone.WishboneDomainCrossingMaster(platform=self.platform, slave=self.curve25519engine.bus, cd_master="sys", cd_slave="clk100")
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#self.bus.add_slave("curve25519engine", self.curve25519engine_wishbone_cdc, SoCRegion(origin=self.mem_map.get("curve25519engine", None), size=0x20000, cached=False))
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@ -309,12 +314,14 @@ def main():
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parser = argparse.ArgumentParser(description="SbusFPGA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--version", default="V1.0", help="SBusFPGA board version (default V1.0)")
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parser.add_argument("--usb", action="store_true", help="add a USB OHCI controller")
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builder_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = SBusFPGA(**soc_core_argdict(args),
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version=args.version)
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version=args.version,
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usb=args.usb)
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#soc.add_uart(name="uart", baudrate=115200, fifo_depth=16)
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builder = Builder(soc, **builder_argdict(args))
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