preliminary i2c support via the OC I2C ctrl & betrustedio wrapper
Now with a NetBSD driver (based on the OpenBSD one) that shows the i2c bus, and some prom support. Not tested with a device, waiting on custom Pmod.
This commit is contained in:
Romain Dolbeau
parent
8f017f5b92
commit
9ae081ed19
463
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_ociic.c
Normal file
463
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_ociic.c
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@ -0,0 +1,463 @@
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/* $NetBSD$ */
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/*
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* Original driver from OpenBSD:
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* Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
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*
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* NetBSD support for the SBusFPGA variant (based on the betrustedio wrapper):
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* Copyright (c) 2022 Romain Dolbeau <romain@dolbeau.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/bus.h>
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#include <machine/autoconf.h>
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#include <sys/cpu.h>
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#include <sys/conf.h>
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#define _I2C_PRIVATE
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#include <dev/i2c/i2cvar.h>
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#include <machine/param.h>
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//#define CONFIG_CSR_DATA_WIDTH 32
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//#include "dev/sbus/sbusfpga_csr_i2c.h"
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/* Registers */
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/* with the betrustedio wrapper to the OC I2C core,
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prescale register is 16-bits,
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TXR/RXR are split, CR/SR are split,
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RESET, EV_* are new */
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/* #define I2C_PRER_LO 0x0000 */
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/* #define I2C_PRER_HI 0x0004 */
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#define I2C_PRER 0x0000
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#define I2C_CTR 0x0004
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#define I2C_CTR_EN (1 << 7)
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#define I2C_CTR_IEN (1 << 6)
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#define I2C_TXR 0x0008
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#define I2C_RXR 0x000C
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#define I2C_CR 0x0010
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#define I2C_CR_STA (1 << 7)
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#define I2C_CR_STO (1 << 6)
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#define I2C_CR_RD (1 << 5)
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#define I2C_CR_WR (1 << 4)
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#define I2C_CR_NACK (1 << 3)
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#define I2C_CR_IACK (1 << 0)
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#define I2C_SR 0x0014
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#define I2C_SR_RXNACK (1 << 7)
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#define I2C_SR_BUSY (1 << 6)
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#define I2C_SR_AL (1 << 5)
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#define I2C_SR_TIP (1 << 1)
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#define I2C_SR_IF (1 << 0)
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#define I2C_RESET 0x0018
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#define I2C_EV_SR 0x001C
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#define I2C_EV_PEND 0x0020
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#define I2C_EV_ENAB 0x0024
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struct ociic_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bustag; /* bus tag */
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bus_space_handle_t sc_bhregs_i2c; /* bus handle */
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int sc_node;
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int sc_burst;
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struct i2c_controller sc_ic;
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};
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static inline uint8_t
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ociic_read(struct ociic_softc *sc, bus_size_t reg)
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{
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return bus_space_read_1(sc->sc_bustag, sc->sc_bhregs_i2c, reg);
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}
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static inline void
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ociic_write(struct ociic_softc *sc, bus_size_t reg, const uint8_t value)
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{
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bus_space_write_1(sc->sc_bustag, sc->sc_bhregs_i2c, reg, value);
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}
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static inline void
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ociic_set(struct ociic_softc *sc, bus_size_t reg, const uint8_t bits)
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{
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ociic_write(sc, reg, ociic_read(sc, reg) | bits);
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}
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static inline void
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ociic_clr(struct ociic_softc *sc, bus_size_t reg, const uint8_t bits)
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{
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ociic_write(sc, reg, ociic_read(sc, reg) & ~bits);
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}
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int ociic_match(device_t, cfdata_t, void *);
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void ociic_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(sbusfpga_ociic, sizeof(struct ociic_softc),
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ociic_match, ociic_attach, NULL, NULL);
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int ociic_acquire_bus(void *, int);
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void ociic_release_bus(void *, int);
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int ociic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
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void *, size_t, int);
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static prop_array_t create_dict(device_t parent);
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static void add_prop(prop_array_t c, const char *name, const char *compat, u_int addr, int node);
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void ociic_bus_scan(struct device *, struct i2cbus_attach_args *, void *);
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int
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ociic_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct sbus_attach_args *sa = (struct sbus_attach_args *)aux;
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return (strcmp("oc,i2c", sa->sa_name) == 0);
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}
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void
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ociic_attach(device_t parent, device_t self, void *aux)
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{
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struct sbus_attach_args *sa = aux;
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struct ociic_softc *sc = device_private(self);
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struct sbus_softc *sbsc = device_private(parent);
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int sbusburst;
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struct i2cbus_attach_args iba;
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uint32_t clock_speed, bus_speed;
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uint32_t div;
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sc->sc_bustag = sa->sa_bustag;
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// sc->sc_dmatag = sa->sa_dmatag;
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sc->sc_dev = self;
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aprint_normal("\n");
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if (sa->sa_nreg < 1) {
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aprint_error(": Not enough registers spaces\n");
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return;
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}
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/* sc->sc_bustag = faa->fa_iot; */
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/* sc->sc_node = faa->fa_node; */
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sc->sc_node = sa->sa_node;
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/*
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* Get transfer burst size from PROM
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*/
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sbusburst = sbsc->sc_burst;
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if (sbusburst == 0)
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sbusburst = SBUS_BURST_32 - 1; /* 1->16 */
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sc->sc_burst = prom_getpropint(sc->sc_node, "burst-sizes", -1);
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if (sc->sc_burst == -1)
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/* take SBus burst sizes */
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sc->sc_burst = sbusburst;
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/* Clamp at parent's burst sizes */
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sc->sc_burst &= sbusburst;
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aprint_normal_dev(self, "nid 0x%x, bustag %p, burst 0x%x (parent 0x%0x)\n",
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sc->sc_node,
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sc->sc_bustag,
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sc->sc_burst,
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sbsc->sc_burst);
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/* map registers */
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if (sbus_bus_map(sc->sc_bustag,
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sa->sa_reg[0].oa_space /* sa_slot */,
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sa->sa_reg[0].oa_base /* sa_offset */,
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sa->sa_reg[0].oa_size /* sa_size */,
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BUS_SPACE_MAP_LINEAR,
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&sc->sc_bhregs_i2c) != 0) {
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aprint_error(": cannot map I2C registers\n");
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return;
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}
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/* pinctrl_byname(sc->sc_node, "default"); */
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/* clock_enable_all(sc->sc_node); */
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ociic_clr(sc, I2C_CTR, I2C_CTR_EN);
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clock_speed = prom_getpropint(sc->sc_node, "clock-speed", -1);
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bus_speed = prom_getpropint(sc->sc_node, "bus-speed", -1);
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aprint_normal_dev(self, "clock-speed = %d, bus-speed = %d\n", clock_speed, bus_speed);
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if ((clock_speed > 0) && (bus_speed > 0)) {
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div = (clock_speed / (5 * bus_speed));
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if (div > 0)
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div -= 1;
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if (div > 0xffff)
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div = 0xffff;
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/* ociic_write(sc, I2C_PRER_LO, div & 0xff); */
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/* ociic_write(sc, I2C_PRER_HI, div >> 8); */
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bus_space_write_2(sc->sc_bustag, sc->sc_bhregs_i2c, I2C_PRER, div);
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aprint_normal_dev(self, "div = %d\n", div);
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} else {
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aprint_error(": invalid clock/bus speed\n");
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return;
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}
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memset(&sc->sc_ic, 0, sizeof(sc->sc_ic));
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sc->sc_ic.ic_cookie = sc;
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sc->sc_ic.ic_acquire_bus = ociic_acquire_bus;
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sc->sc_ic.ic_release_bus = ociic_release_bus;
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sc->sc_ic.ic_exec = ociic_exec;
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/* Configure its children */
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memset(&iba, 0, sizeof(iba));
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iba.iba_tag = &sc->sc_ic;
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iba.iba_child_devices = create_dict(self);
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{
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char *name;
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char *compat;
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uint32_t addr;
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int node;
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for (node = prom_firstchild(sc->sc_node); node; node = prom_nextsibling(node)) {
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if ((name = prom_getpropstring(node, "name")) == NULL)
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continue;
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if (name[0] == '\0')
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continue;
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if ((compat = prom_getpropstring(node, "compatible")) == NULL)
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continue;
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if (compat[0] == '\0')
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continue;
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if ((addr = prom_getpropint(node, "addr", -1)) == -1)
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continue;
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add_prop(iba.iba_child_devices, name, compat, addr, sc->sc_node);
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}
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}
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config_found_ia(self, "i2cbus", &iba, iicbus_print);
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}
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int
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ociic_acquire_bus(void *cookie, int flags)
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{
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struct ociic_softc *sc = cookie;
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ociic_set(sc, I2C_CTR, I2C_CTR_EN);
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return 0;
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}
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void
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ociic_release_bus(void *cookie, int flags)
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{
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struct ociic_softc *sc = cookie;
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ociic_clr(sc, I2C_CTR, I2C_CTR_EN);
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}
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int
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ociic_unbusy(struct ociic_softc *sc);
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int
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ociic_unbusy(struct ociic_softc *sc)
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{
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uint8_t stat;
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int timo;
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for (timo = 50000; timo > 0; timo--) {
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stat = ociic_read(sc, I2C_SR);
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if ((stat & I2C_SR_BUSY) == 0)
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break;
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delay(10);
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}
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if (timo == 0) {
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ociic_write(sc, I2C_CR, I2C_CR_STO);
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return ETIMEDOUT;
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}
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return 0;
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}
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int
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ociic_wait(struct ociic_softc *sc, int ack);
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int
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ociic_wait(struct ociic_softc *sc, int ack)
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{
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uint8_t stat;
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int timo;
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for (timo = 50000; timo > 0; timo--) {
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stat = ociic_read(sc, I2C_SR);
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if ((stat & I2C_SR_TIP) == 0)
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break;
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if ((stat & I2C_SR_AL))
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break;
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delay(10);
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}
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if (timo == 0) {
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ociic_write(sc, I2C_CR, I2C_CR_STO);
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return ETIMEDOUT;
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}
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if (stat & I2C_SR_AL) {
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ociic_write(sc, I2C_CR, I2C_CR_STO);
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return EIO;
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}
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if (ack && (stat & I2C_SR_RXNACK)) {
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ociic_write(sc, I2C_CR, I2C_CR_STO);
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return EIO;
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}
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return 0;
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}
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int
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ociic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd,
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size_t cmdlen, void *buf, size_t buflen, int flags)
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{
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struct ociic_softc *sc = cookie;
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int error, i;
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error = ociic_unbusy(sc);
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if (error)
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return error;
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if (cmdlen > 0) {
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ociic_write(sc, I2C_TXR, addr << 1);
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ociic_write(sc, I2C_CR, I2C_CR_STA | I2C_CR_WR);
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error = ociic_wait(sc, 1);
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if (error)
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return error;
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for (i = 0; i < cmdlen; i++) {
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ociic_write(sc, I2C_TXR, ((const uint8_t *)cmd)[i]);
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ociic_write(sc, I2C_CR, I2C_CR_WR);
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error = ociic_wait(sc, 1);
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if (error)
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return error;
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}
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}
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if (I2C_OP_READ_P(op)) {
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ociic_write(sc, I2C_TXR, addr << 1 | 1);
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ociic_write(sc, I2C_CR, I2C_CR_STA | I2C_CR_WR);
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error = ociic_wait(sc, 1);
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if (error)
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return error;
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for (i = 0; i < buflen; i++) {
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ociic_write(sc, I2C_CR, I2C_CR_RD |
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(i == (buflen - 1) ? I2C_CR_NACK : 0));
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error = ociic_wait(sc, 0);
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if (error)
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return error;
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((uint8_t *)buf)[i] = ociic_read(sc, I2C_RXR);
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}
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} else {
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if (cmdlen == 0) {
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ociic_write(sc, I2C_TXR, addr << 1);
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ociic_write(sc, I2C_CR, I2C_CR_STA | I2C_CR_WR);
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}
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for (i = 0; i < buflen; i++) {
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ociic_write(sc, I2C_TXR, ((const uint8_t *)buf)[i]);
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ociic_write(sc, I2C_CR, I2C_CR_WR);
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error = ociic_wait(sc, 1);
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if (error)
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return error;
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}
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}
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if (I2C_OP_STOP_P(op))
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ociic_write(sc, I2C_CR, I2C_CR_STO);
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return 0;
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}
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void
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ociic_bus_scan(struct device *self, struct i2cbus_attach_args *iba, void *arg)
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{
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int iba_node = *(int *)arg;
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struct i2c_attach_args ia;
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/* char name[32], status[32]; */
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/* uint32_t reg[1]; */
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char *name;
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uint32_t addr;
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int node;
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/* for (node = OF_child(iba_node); node; node = OF_peer(node)) { */
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/* memset(name, 0, sizeof(name)); */
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/* memset(status, 0, sizeof(status)); */
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/* memset(reg, 0, sizeof(reg)); */
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/* if (OF_getprop(node, "compatible", name, sizeof(name)) == -1) */
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/* continue; */
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/* if (name[0] == '\0') */
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/* continue; */
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/* if (OF_getprop(node, "status", status, sizeof(status)) > 0 && */
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/* strcmp(status, "disabled") == 0) */
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/* continue; */
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/* if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg)) */
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/* continue; */
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/* memset(&ia, 0, sizeof(ia)); */
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/* ia.ia_tag = iba->iba_tag; */
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/* ia.ia_addr = bemtoh32(®[0]); */
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/* ia.ia_name = name; */
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/* ia.ia_cookie = &node; */
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/* config_found(self, &ia, iicbus_print); */
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/* } */
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for (node = prom_firstchild(iba_node); node; node = prom_nextsibling(node)) {
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if ((name = prom_getpropstring(node, "name")) == NULL)
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continue;
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if (name[0] == '\0')
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continue;
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if ((addr = prom_getpropint(node, "addr", -1)) == -1)
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continue;
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memset(&ia, 0, sizeof(ia));
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ia.ia_tag = iba->iba_tag;
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ia.ia_addr = addr;
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ia.ia_name = name;
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ia.ia_cookie = (uintptr_t)&node;
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config_found(self, &ia, iicbus_print);
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}
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}
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/* stolen from arch/sparc64/dev/pcfiic_ebus.c */
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static prop_array_t
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create_dict(device_t parent)
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{
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prop_dictionary_t props = device_properties(parent);
|
||||
prop_array_t cfg = prop_dictionary_get(props, "i2c-child-devices");
|
||||
if (cfg) return cfg;
|
||||
cfg = prop_array_create();
|
||||
prop_dictionary_set(props, "i2c-child-devices", cfg);
|
||||
prop_object_release(cfg);
|
||||
return cfg;
|
||||
}
|
||||
|
||||
static void
|
||||
add_prop(prop_array_t c, const char *name, const char *compat, u_int addr, int node)
|
||||
{
|
||||
prop_dictionary_t dev;
|
||||
prop_data_t data;
|
||||
|
||||
dev = prop_dictionary_create();
|
||||
prop_dictionary_set_cstring(dev, "name", name);
|
||||
data = prop_data_create_data(compat, strlen(compat)+1);
|
||||
prop_dictionary_set(dev, "compatible", data);
|
||||
prop_object_release(data);
|
||||
prop_dictionary_set_uint32(dev, "addr", addr);
|
||||
prop_dictionary_set_uint64(dev, "cookie", node);
|
||||
prop_array_add(c, dev);
|
||||
prop_object_release(dev);
|
||||
}
|
||||
@ -561,6 +561,7 @@ class SBusFPGABus(Module):
|
||||
(SBUS_3V3_PPRD_i == 1)),
|
||||
NextValue(sbus_oe_master_in, 1),
|
||||
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
@ -624,6 +625,7 @@ class SBusFPGABus(Module):
|
||||
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
|
||||
NextState("Slave_Error")
|
||||
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
@ -746,7 +748,8 @@ class SBusFPGABus(Module):
|
||||
(SIZ_BYTE == SBUS_3V3_SIZ_i) &
|
||||
(SBUS_3V3_PPRD_i == 0)),
|
||||
NextValue(sbus_oe_master_in, 1),
|
||||
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
@ -795,7 +798,8 @@ class SBusFPGABus(Module):
|
||||
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
|
||||
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
|
||||
NextState("Slave_Error")
|
||||
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
|
||||
@ -188,8 +188,17 @@ def get_prom(soc,
|
||||
r += "finish-device\nnew-device\n"
|
||||
|
||||
if (i2c):
|
||||
r += "\" RDOL,i2c\" device-name\n"
|
||||
r += "\" oc,i2c\" device-name\n"
|
||||
r += get_header_map_stuff("i2c", "i2c", 64)
|
||||
r += (f"h# {sys_clk_freq:x} encode-int \" clock-speed\" property\n").replace("0x", "")
|
||||
bus_speed = 400000
|
||||
r += (f"h# {bus_speed:x} encode-int \" bus-speed\" property\n").replace("0x", "")
|
||||
# assume just a lm75-compatible device at 0x48 (i.e. the custom Pmod)
|
||||
r += " new-device\n"
|
||||
r += " \" AT30TS74-UFM10\" encode-string \" name\" property\n"
|
||||
r += " \" lm75\" encode-string \" compatible\" property\n"
|
||||
r += " h# 48 encode-int \" addr\" property\n"
|
||||
r += " finish-device\n"
|
||||
if (framebuffer or sdcard):
|
||||
r += "finish-device\nnew-device\n"
|
||||
|
||||
|
||||
@ -30,7 +30,7 @@ from migen.genlib.cdc import BusSynchronizer
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
# betrusted-io/gateware
|
||||
from gateware import i2c
|
||||
from gateware.i2c import *
|
||||
|
||||
import sbus_to_fpga_export
|
||||
import sbus_to_fpga_prom
|
||||
@ -347,7 +347,11 @@ class SBusFPGA(SoCCore):
|
||||
#for i in range(len(prom)):
|
||||
# print(hex(prom[i]))
|
||||
#print("\n****************************************\n")
|
||||
self.add_ram("prom", origin=self.mem_map["prom"], size=2**15, contents=prom_data, mode="r") ### FIXME: round up the prom_data size & check for <= 2**16!
|
||||
prom_len = 4*len(prom_data);
|
||||
rounded_prom_len = 2**log2_int(prom_len, False)
|
||||
print(f"ROM is {prom_len} bytes, using {rounded_prom_len}")
|
||||
assert(rounded_prom_len <= 2**16)
|
||||
self.add_ram("prom", origin=self.mem_map["prom"], size=rounded_prom_len, contents=prom_data, mode="r")
|
||||
#getattr(self,"prom").mem.init = prom_data
|
||||
#getattr(self,"prom").mem.depth = 2**15
|
||||
|
||||
@ -501,7 +505,7 @@ class SBusFPGA(SoCCore):
|
||||
self.comb += self.crg.curve25519_on.eq(self.curve25519engine.power.fields.on)
|
||||
|
||||
if (i2c):
|
||||
self.submodules.i2c = i2c.RTLI2C(platform, pads=platform.request("i2c"))
|
||||
self.submodules.i2c = RTLI2C(platform, pads=platform.request("i2c"))
|
||||
|
||||
if (framebuffer):
|
||||
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
|
||||
@ -524,7 +528,11 @@ class SBusFPGA(SoCCore):
|
||||
self.bus.add_master(name="cg6_accel_r5_d", master=self.cg6_accel.dbus)
|
||||
cg6_rom_file = "blit.raw"
|
||||
cg6_rom_data = soc_core.get_mem_data(cg6_rom_file, "little")
|
||||
self.add_ram("cg6_accel_rom", origin=self.mem_map["cg6_accel_rom"], size=2**13, contents=cg6_rom_data, mode="r")
|
||||
cg6_rom_len = 4*len(cg6_rom_data);
|
||||
rounded_cg6_rom_len = 2**log2_int(cg6_rom_len, False)
|
||||
print(f"CG6 ROM is {cg6_rom_len} bytes, using {rounded_cg6_rom_len}")
|
||||
assert(rounded_cg6_rom_len <= 2**16)
|
||||
self.add_ram("cg6_accel_rom", origin=self.mem_map["cg6_accel_rom"], size=rounded_cg6_rom_len, contents=cg6_rom_data, mode="r")
|
||||
self.add_ram("cg6_accel_ram", origin=self.mem_map["cg6_accel_ram"], size=2**12, mode="rw")
|
||||
|
||||
print("IRQ to Device map:\n")
|
||||
|
||||
@ -196,12 +196,22 @@ _i2c_v1_0 = [
|
||||
IOStandard("LVCMOS33"))
|
||||
]
|
||||
# reusing the UART pins !!!
|
||||
_i2c_v1_2 = [
|
||||
("i2c", 0,
|
||||
Subsignal("scl", Pins("V9")),
|
||||
Subsignal("sda", Pins("U9")),
|
||||
IOStandard("LVCMOS33"))
|
||||
#_i2c_v1_2 = [
|
||||
# ("i2c", 0,
|
||||
# Subsignal("scl", Pins("V9")),
|
||||
# Subsignal("sda", Pins("U9")),
|
||||
# IOStandard("LVCMOS33"))
|
||||
#]
|
||||
|
||||
def tempi2c_pmod_io(pmod):
|
||||
return [
|
||||
("i2c", 0,
|
||||
Subsignal("scl", Pins(f"{pmod}:3"), Misc("PULLUP True")),
|
||||
Subsignal("sda", Pins(f"{pmod}:7"), Misc("PULLUP True")),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
]
|
||||
_tempi2c_pmod_io_v1_2 = tempi2c_pmod_io("P1")
|
||||
|
||||
# VGA ----------------------------------------------------------------------------------------------
|
||||
|
||||
@ -272,7 +282,7 @@ class Platform(XilinxPlatform):
|
||||
}[version]
|
||||
i2c = {
|
||||
"V1.0" : _i2c_v1_0,
|
||||
"V1.2" : _i2c_v1_2,
|
||||
"V1.2" : _tempi2c_pmod_io_v1_2,
|
||||
}[version]
|
||||
self.avail_irqs = {
|
||||
"V1.0" : { 1 }, # don't add 7 here, too risky
|
||||
@ -288,6 +298,12 @@ class Platform(XilinxPlatform):
|
||||
self.add_extension(sbus_io)
|
||||
self.add_extension(sbus_sbus)
|
||||
self.add_extension(i2c)
|
||||
|
||||
self.toolchain.opt_directive = "Explore"
|
||||
#self.toolchain.vivado_place_directive = "Explore"
|
||||
self.toolchain.vivado_post_place_phys_opt_directive = "Explore"
|
||||
#self.toolchain.vivado_route_directive = "Explore"
|
||||
self.toolchain.vivado_post_route_phys_opt_directive = "Explore"
|
||||
|
||||
self.toolchain.bitstream_commands = \
|
||||
["set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]",
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user