fix sdram prom config for 90 MHz sysclk

sbus-to-ztex-gateware-migen/sbus_to_fpga_prom.py

@@ -93,7 +93,8 @@ def get_header_mapx_stuff(gname, names, sizes, types):
     return r
 
 def get_prom(soc,
-             version="V1.0",
+             version,
+             sys_clk_freq,
              trng=False,
              usb=False,
              sdram=True,
@@ -216,6 +217,19 @@ def get_prom(soc,
     if (sdcard):
         r += "\" LITEX,sdcard\" device-name\n"
         r += get_header_mapx_stuff("sdcard", ["sdcore", "sdirq", "sdphy", "sdblock2mem", "sdmem2block" ], [ 4096, 4096, 4096, 4096, 4096 ], [ "csr", "csr", "csr", "csr", "csr" ] )
+        if (sys_clq_freq == 100e6):
+            r += "25 constant m0_delay\n"
+            r += "25 constant m1_delay\n"
+            r += "1 constant m0_bitslip\n"
+            r += "1 constant m1_bitslip\n"
+        elif (sys_clq_freq == 90e6):
+            r += "28 constant m0_delay\n"
+            r += "28 constant m1_delay\n"
+            r += "1 constant m0_bitslip\n"
+            r += "1 constant m1_bitslip\n"
+        else:
+            print("UNCALIBRATED FREQUENCY for SDRAM!")
+            assert(False)
         r += ": sdcard-init!\n"
         r += "  map-in-sdcard\n"
         r += "  0 sdirq-virt h# 8 + l! ( disable irqs )\n"

sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py

@@ -624,7 +624,7 @@ def main():
         csr_base  = soc.mem_regions['csr'].origin)
     write_to_file(os.path.join(f"prom_csr_{version_for_filename}.fth"), csr_forth_contents)
 
-    prom_content = sbus_to_fpga_prom.get_prom(soc=soc, version=args.version,
+    prom_content = sbus_to_fpga_prom.get_prom(soc=soc, version=args.version, sys_clk_freq=sys_clk_freq,
                                               trng=args.trng,
                                               usb=args.usb,
                                               sdram=args.sdram,

sbus-to-ztex-gateware-migen/sdram_init.fth

@@ -119,22 +119,22 @@ fload sdram_csr.fth
 	\ .( config module 0 read ) cr
 	1 dphy_dly_sel_wr
 	1 dphy_rdly_dq_bitslip_rst_wr
-	1 0 do
+	m0_bitslip 0 do
 		1 0 do 1 dphy_rdly_dq_bitslip_wr loop
 	loop
 	1 dphy_rdly_dq_rst_wr
-	25 0 do
+	m0_delay 0 do
 	   1 dphy_rdly_dq_inc_wr
 	loop
 	
 	\ .( config module 1 read ) cr
 	2 dphy_dly_sel_wr
 	1 dphy_rdly_dq_bitslip_rst_wr
-	1 0 do
+	m1_bitslip 0 do
 		1 0 do 1 dphy_rdly_dq_bitslip_wr loop
 	loop
 	1 dphy_rdly_dq_rst_wr
-	25 0 do
+	m1_delay 0 do
 	   1 dphy_rdly_dq_inc_wr
 	loop
 	\ .( finish ) cr