sdcard, interrupt line on sdram
This commit is contained in:
Romain Dolbeau
parent
94c36e7a36
commit
a944704ef4
@ -59,7 +59,11 @@ class ExchangeWithMem(Module, AutoCSR):
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self.comb += self.blk_size.status.eq(data_width)
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self.comb += self.blk_base.status.eq(soc.wb_mem_map["main_ram"] >> log2_int(data_width))
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self.comb += self.mem_size.status.eq((mem_size * 1024 * 1024) >> log2_int(data_width))
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self.irqctrl = CSRStorage(write_from_dev=True, fields = [CSRField("irq_enable", 1, description = "Enable interrupt"),
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CSRField("irq_clear", 1, description = "Clear interrupt"),
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CSRField("reserved", 30, description = "Reserved"),
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])
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self.blk_addr = CSRStorage(32, description = "SDRAM Block address to read/write from Wishbone memory (block of size {})".format(data_width))
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self.dma_addr = CSRStorage(32, description = "Host Base address where to write/read data (i.e. SPARC Virtual addr)")
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#self.blk_cnt = CSRStorage(32, write_from_dev=True, description = "How many blk to read/write (max 2^{}-1); bit 31 is RD".format(max_block_bits), reset = 0)
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@ -114,6 +118,25 @@ class ExchangeWithMem(Module, AutoCSR):
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self.comb += self.tosbus_fifo_readable_sync.i.eq(self.tosbus_fifo.readable)
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self.comb += tosbus_fifo_readable_in_sys.eq(self.tosbus_fifo_readable_sync.o)
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self.comb += self.dma_status.fields.has_rd_data.eq(tosbus_fifo_readable_in_sys) # there's still data to be sent to memory; this will drop before the last SBus Master Cycle is finished, but then the SBus is busy so the host won't be able to read the status before the cycle is finished so we're good
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ongoing_m1 = Signal()
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ongoing = Signal()
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self.irq = irq = Signal()
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self.sync += ongoing_m1.eq(ongoing)
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self.sync += ongoing.eq(self.dma_status.fields.rd_fsm_busy |
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self.dma_status.fields.wr_fsm_busy |
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self.dma_status.fields.has_wr_data |
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self.dma_status.fields.has_requests |
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self.dma_status.fields.has_rd_data |
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(self.blk_cnt.storage[0:max_block_bits] != 0)
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)
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self.sync += irq.eq(((~ongoing & ongoing_m1) & self.irqctrl.fields.irq_enable) | # irq on falling edge of ongoing
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(self.irq & ~self.irqctrl.fields.irq_clear & ~(ongoing & ~ongoing_m1))) # keep irq until cleared or rising edge of ongoing
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self.sync += If(self.irqctrl.fields.irq_clear,
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self.irqctrl.we.eq(1),
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self.irqctrl.dat_w.eq(self.irqctrl.storage & 0xFFFFFFFD)) ## auto-reset irq_clear
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#self.comb += self.dma_status.status[16:17].eq(self.wishbone_w_master.cyc) # show the WB iface status (W)
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#self.comb += self.dma_status.status[17:18].eq(self.wishbone_w_master.stb)
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@ -191,7 +191,7 @@ class SBusFPGABus(Module):
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self.fromsbus_fifo = fromsbus_fifo
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self.fromsbus_req_fifo = fromsbus_req_fifo
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if (cg3_fb_size == 1*1048576):
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if (cg3_fb_size <= 1*1048576):
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CG3_UPPER_BITS=12
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CG3_KEPT_UPPER_BIT=20
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CG3_PIXELS_ADDR_BIGVAL = 0x08>>0
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@ -14,29 +14,29 @@ def get_header_map_stuff(gname, name, size, type="csr", reg=True):
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r = ""
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if (reg):
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r += f"my-address sbusfpga_{type}addr_{name} + my-space h# {size:x} reg\n"
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r += "h# 7f xdrint \" slave-burst-sizes\" attribute\n" # fixme: burst-sizes
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r += "h# 7f xdrint \" burst-sizes\" attribute\n" # fixme: burst-sizes
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r += "h# 7f encode-int \" slave-burst-sizes\" property\n" # fixme: burst-sizes
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r += "h# 7f encode-int \" burst-sizes\" property\n" # fixme: burst-sizes
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r += "headers\n"
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r += f"-1 instance value {name}-virt\nmy-address constant my-sbus-address\nmy-space constant my-sbus-space\n"
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r += ": map-in ( adr space size -- virt ) \" map-in\" $call-parent ;\n: map-out ( virt size -- ) \" map-out\" $call-parent ;\n";
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r += f": map-in-{gname} ( -- ) my-sbus-address sbusfpga_{type}addr_{name} + my-sbus-space h# {size:x} map-in is {name}-virt ;\n"
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r += f": map-in-{gname} ( -- ) my-sbus-address sbusfpga_{type}addr_{name} + my-sbus-space h# {size:x} map-in to {name}-virt ;\n"
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r += f": map-out-{gname} ( -- ) {name}-virt h# {size:x} map-out ;\n"
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return r
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def get_header_map2_stuff(gname, name1, name2, size1, size2, type1="csr", type2="csr"):
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r = f"my-address sbusfpga_{type1}addr_{name1} + my-space xdrphys h# {size1:x} xdrint xdr+\n"
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r += f"my-address sbusfpga_{type2}addr_{name2} + my-space xdrphys xdr+ h# {size2:x} xdrint xdr+\n"
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r += "\" reg\" attribute\n"
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r += "h# 7f xdrint \" slave-burst-sizes\" attribute\n" # fixme: burst-sizes
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r += "h# 7f xdrint \" burst-sizes\" attribute\n" # fixme: burst-sizes
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r = f"my-address sbusfpga_{type1}addr_{name1} + my-space encode-phys h# {size1:x} encode-int encode+\n"
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r += f"my-address sbusfpga_{type2}addr_{name2} + my-space encode-phys encode+ h# {size2:x} encode-int encode+\n"
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r += "\" reg\" property\n"
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r += "h# 7f encode-int \" slave-burst-sizes\" property\n" # fixme: burst-sizes
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r += "h# 7f encode-int \" burst-sizes\" property\n" # fixme: burst-sizes
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r += "headers\n"
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r += f"-1 instance value {name1}-virt\n"
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r += f"-1 instance value {name2}-virt\n"
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r += "my-address constant my-sbus-address\nmy-space constant my-sbus-space\n"
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r += ": map-in ( adr space size -- virt ) \" map-in\" $call-parent ;\n: map-out ( virt size -- ) \" map-out\" $call-parent ;\n";
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r += f": map-in-{gname} ( -- )\n"
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r += f"my-sbus-address sbusfpga_{type1}addr_{name1} + my-sbus-space h# {size1:x} map-in is {name1}-virt\n"
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r += f"my-sbus-address sbusfpga_{type2}addr_{name2} + my-sbus-space h# {size2:x} map-in is {name2}-virt\n"
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r += f"my-sbus-address sbusfpga_{type1}addr_{name1} + my-sbus-space h# {size1:x} map-in to {name1}-virt\n"
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r += f"my-sbus-address sbusfpga_{type2}addr_{name2} + my-sbus-space h# {size2:x} map-in to {name2}-virt\n"
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r += ";\n"
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r += f": map-out-{gname} ( -- )\n"
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r += f"{name1}-virt h# {size1:x} map-out\n"
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@ -45,12 +45,12 @@ def get_header_map2_stuff(gname, name1, name2, size1, size2, type1="csr", type2=
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return r
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def get_header_map3_stuff(gname, name1, name2, name3, size1, size2, size3, type1="csr", type2="csr", type3="csr"):
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r = f"my-address sbusfpga_{type1}addr_{name1} + my-space xdrphys h# {size1:x} xdrint xdr+\n"
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r += f"my-address sbusfpga_{type2}addr_{name2} + my-space xdrphys xdr+ h# {size2:x} xdrint xdr+\n"
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r += f"my-address sbusfpga_{type3}addr_{name3} + my-space xdrphys xdr+ h# {size3:x} xdrint xdr+\n"
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r += "\" reg\" attribute\n"
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r += "h# 7f xdrint \" slave-burst-sizes\" attribute\n" # fixme: burst-sizes
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r += "h# 7f xdrint \" burst-sizes\" attribute\n" # fixme: burst-sizes
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r = f"my-address sbusfpga_{type1}addr_{name1} + my-space encode-phys h# {size1:x} encode-int encode+\n"
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r += f"my-address sbusfpga_{type2}addr_{name2} + my-space encode-phys encode+ h# {size2:x} encode-int encode+\n"
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r += f"my-address sbusfpga_{type3}addr_{name3} + my-space encode-phys encode+ h# {size3:x} encode-int encode+\n"
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r += "\" reg\" property\n"
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r += "h# 7f encode-int \" slave-burst-sizes\" property\n" # fixme: burst-sizes
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r += "h# 7f encode-int \" burst-sizes\" property\n" # fixme: burst-sizes
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r += "headers\n"
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r += f"-1 instance value {name1}-virt\n"
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r += f"-1 instance value {name2}-virt\n"
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@ -58,9 +58,9 @@ def get_header_map3_stuff(gname, name1, name2, name3, size1, size2, size3, type1
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r += "my-address constant my-sbus-address\nmy-space constant my-sbus-space\n"
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r += ": map-in ( adr space size -- virt ) \" map-in\" $call-parent ;\n: map-out ( virt size -- ) \" map-out\" $call-parent ;\n";
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r += f": map-in-{gname} ( -- )\n"
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r += f"my-sbus-address sbusfpga_{type1}addr_{name1} + my-sbus-space h# {size1:x} map-in is {name1}-virt\n"
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r += f"my-sbus-address sbusfpga_{type2}addr_{name2} + my-sbus-space h# {size2:x} map-in is {name2}-virt\n"
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r += f"my-sbus-address sbusfpga_{type3}addr_{name3} + my-sbus-space h# {size3:x} map-in is {name3}-virt\n"
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r += f"my-sbus-address sbusfpga_{type1}addr_{name1} + my-sbus-space h# {size1:x} map-in to {name1}-virt\n"
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r += f"my-sbus-address sbusfpga_{type2}addr_{name2} + my-sbus-space h# {size2:x} map-in to {name2}-virt\n"
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r += f"my-sbus-address sbusfpga_{type3}addr_{name3} + my-sbus-space h# {size3:x} map-in to {name3}-virt\n"
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r += ";\n"
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r += f": map-out-{gname} ( -- )\n"
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r += f"{name1}-virt h# {size1:x} map-out\n"
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@ -69,6 +69,28 @@ def get_header_map3_stuff(gname, name1, name2, name3, size1, size2, size3, type1
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r += ";\n"
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return r
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def get_header_mapx_stuff(gname, names, sizes, types):
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r = f"my-address sbusfpga_{types[0]}addr_{names[0]} + my-space encode-phys h# {sizes[0]:x} encode-int encode+\n"
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for i in range(1, len(names)):
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r += f"my-address sbusfpga_{types[i]}addr_{names[i]} + my-space encode-phys encode+ h# {sizes[i]:x} encode-int encode+\n"
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r += "\" reg\" property\n"
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r += "h# 7f encode-int \" slave-burst-sizes\" property\n" # fixme: burst-sizes
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r += "h# 7f encode-int \" burst-sizes\" property\n" # fixme: burst-sizes
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r += "headers\n"
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for i in range(0, len(names)):
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r += f"-1 instance value {names[i]}-virt\n"
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r += "my-address constant my-sbus-address\nmy-space constant my-sbus-space\n"
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r += ": map-in ( adr space size -- virt ) \" map-in\" $call-parent ;\n: map-out ( virt size -- ) \" map-out\" $call-parent ;\n";
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r += f": map-in-{gname} ( -- )\n"
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for i in range(0, len(names)):
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r += f"my-sbus-address sbusfpga_{types[i]}addr_{names[i]} + my-sbus-space h# {sizes[i]:x} map-in to {names[i]}-virt\n"
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r += ";\n"
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r += f": map-out-{gname} ( -- )\n"
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for i in range(0, len(names)):
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r += f"{names[i]}-virt h# {sizes[i]:x} map-out\n"
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r += ";\n"
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return r
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def get_prom(soc,
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version="V1.0",
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usb=False,
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@ -77,7 +99,8 @@ def get_prom(soc,
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i2c=False,
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cg3=False,
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cg6=False,
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cg3_res=None):
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cg3_res=None,
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sdcard=False):
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r = "fcode-version2\nfload prom_csr_{}.fth\n".format(version.replace(".", "_"))
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@ -99,12 +122,12 @@ def get_prom(soc,
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r += " map-out-trng\n"
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r += ";\n"
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r += "disabletrng!\n"
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if (usb or sdram or engine or i2c or cg3 or cg6):
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if (usb or sdram or engine or i2c or cg3 or cg6 or sdcard):
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r += "finish-device\nnew-device\n"
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if (usb):
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r += "\" generic-ohci\" device-name\n"
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r += "sbusfpga_irq_usb_host xdrint \" interrupts\" attribute\n"
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r += "sbusfpga_irq_usb_host encode-int \" interrupts\" property\n"
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r += get_header_map_stuff("usb_host_ctrl", "usb_host_ctrl", 4096, type="region")
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r += ": my-reset! ( -- )\n"
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r += " map-in-usb_host_ctrl\n"
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@ -119,28 +142,29 @@ def get_prom(soc,
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r += " map-out-usb_host_ctrl\n"
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r += ";\n"
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r += "my-reset!\n"
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if (sdram or engine or i2c or cg3 or cg6):
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if (sdram or engine or i2c or cg3 or cg6 or sdcard):
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r += "finish-device\nnew-device\n"
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if (sdram):
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r += "\" RDOL,sdram\" device-name\n"
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r += get_header_map3_stuff("mregs", "ddrphy", "sdram", "exchange_with_mem", 4096, 4096, 4096)
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r += get_header_mapx_stuff("mregs", [ "ddrphy", "sdram", "exchange_with_mem" ], [ 4096, 4096, 4096 ], [ "csr", "csr", "csr" ])
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r += "sbusfpga_irq_sdram encode-int \" interrupts\" property\n"
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r += "fload sdram_init.fth\ninit!\n"
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if (engine or i2c or cg3 or cg6):
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if (engine or i2c or cg3 or cg6 or sdcard):
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r += "finish-device\nnew-device\n"
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if (engine):
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r += "\" betrustedc25519e\" device-name\n"
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r += ": sbusfpga_regionaddr_curve25519engine-microcode sbusfpga_regionaddr_curve25519engine ;\n"
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r += ": sbusfpga_regionaddr_curve25519engine-regfile sbusfpga_regionaddr_curve25519engine h# 10000 + ;\n"
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r += get_header_map3_stuff("curve25519engine", "curve25519engine-regs", "curve25519engine-microcode", "curve25519engine-regfile", 4096, 4096, 65536, type2="region", type3="region")
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if (i2c or cg3 or cg6):
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r += get_header_mapx_stuff("curve25519engine", [ "curve25519engine-regs", "curve25519engine-microcode", "curve25519engine-regfile" ], [ 4096, 4096, 65536 ] , ["csr", "region", "region" ] )
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if (i2c or cg3 or cg6 or sdcard):
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r += "finish-device\nnew-device\n"
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if (i2c):
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r += "\" RDOL,i2c\" device-name\n"
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r += get_header_map_stuff("i2c", "i2c", 64)
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if (cg3 or cg6):
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if (cg3 or cg6 or sdcard):
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r += "finish-device\nnew-device\n"
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if (cg3 or cg6):
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@ -166,7 +190,22 @@ def get_prom(soc,
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if (cg6):
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r += get_header_map_stuff("cg6extraregs", "cg6", 4096, reg=False)
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r += "fload cg6_init.fth\ncg6_init!\n"
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if (sdcard):
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r += "finish-device\nnew-device\n"
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if (sdcard):
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r += "\" LITEX,sdcard\" device-name\n"
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r += get_header_mapx_stuff("sdcard", ["sdcore", "sdirq", "sdphy", "sdblock2mem", "sdmem2block" ], [ 4096, 4096, 4096, 4096, 4096 ], [ "csr", "csr", "csr", "csr", "csr" ] )
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r += ": sdcard-init!\n"
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r += " map-in-sdcard\n"
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r += " 0 sdirq-virt h# 8 + l! ( disable irqs )\n"
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r += " 0 sdblock2mem-virt h# c + l! ( disable dma )\n"
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r += " 0 sdmem2block-virt h# c + l! ( disable dma )\n"
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r += " map-out-sdcard\n"
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r += ";\n"
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r += "sdcard-init!\n"
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r += "fload sdcard.fth\n"
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r += "fload sdcard_access.fth\n"
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r += "end0\n"
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return r
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@ -215,7 +215,7 @@ class SBusFPGA(SoCCore):
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#if self.irq.enabled:
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#self.irq.add(name, use_loc_if_exists=True)
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def __init__(self, variant, version, sys_clk_freq, usb, sdram, engine, i2c, cg3, cg6, cg3_res, **kwargs):
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def __init__(self, variant, version, sys_clk_freq, usb, sdram, engine, i2c, cg3, cg6, cg3_res, sdcard, **kwargs):
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print(f"Building SBusFPGA for board version {version}")
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kwargs["cpu_type"] = "None"
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@ -244,10 +244,11 @@ class SBusFPGA(SoCCore):
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# if there's just one DVMA bus master in the design,
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# then we'll connect it directly to the wishbone interface
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# in the FSM rather than to the system Wishbone bus
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# sdcard has two by itself, so never a single_dvma_master
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single_dvma_master = False
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if (usb and not engine): # fixme: others?
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if (usb and not engine and not sdcard): # fixme: others?
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single_dvma_master = True
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if (engine and not usb): # fixme: others?
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if (engine and not usb and not sdcard): # fixme: others?
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single_dvma_master = True
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SoCCore.__init__(self,
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@ -263,7 +264,7 @@ class SBusFPGA(SoCCore):
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# the physical address here are used as offset in the SBus
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# reserved area of 256 MiB
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# Anything at 0x10000000 is therefore unreachable directly
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# The position of the 'usb_fake_dma' is so it overlaps
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# The position of the 'dvma_bridge' is so it overlaps
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# the virtual address space used by NetBSD DMA allocators
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# (themselves constrained by the SBus MMU capabilities)
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self.wb_mem_map = wb_mem_map = {
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@ -284,7 +285,7 @@ class SBusFPGA(SoCCore):
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"cg3_pixels": 0x00800000, # required for compatibility, 1/2/4/8 MiB for now (up to 0x00FFFFFF inclusive) (cg3 and cg6 idem)
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"main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible),
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"video_framebuffer":0x80000000 + 0x10000000 - cg3_fb_size, # Updated later
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"usb_fake_dma": 0xfc000000, # required to match DVMA virtual addresses
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"dvma_bridge": 0xfc000000, # required to match DVMA virtual addresses
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}
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self.mem_map.update(wb_mem_map)
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self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, usb=usb, usb_clk_freq=48e6, sdram=sdram, engine=engine, cg3=(cg3 or cg6), pix_clk=litex.soc.cores.video.video_timings[cg3_res]["pix_clk"])
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@ -318,6 +319,7 @@ class SBusFPGA(SoCCore):
|
||||
pad_usb_interrupt = platform.get_irq(irq_req=4, device="usb_host", next_down=True, next_up=False)
|
||||
if (pad_usb_interrupt is None):
|
||||
print(" ***** ERROR ***** USB requires an interrupt")
|
||||
assert(False)
|
||||
sig_usb_interrupt = Signal(reset=1)
|
||||
# the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt)
|
||||
self.comb += pad_usb_interrupt.eq(sig_usb_interrupt)
|
||||
@ -409,6 +411,14 @@ class SBusFPGA(SoCCore):
|
||||
mem_size=avail_sdram//1048576,
|
||||
burst_size=burst_size,
|
||||
do_checksum = False)
|
||||
pad_sdram_interrupt = platform.get_irq(irq_req=5, device="sdram", next_down=True, next_up=True)
|
||||
if (pad_sdram_interrupt is None):
|
||||
print(" ***** ERROR ***** sdram requires an interrupt")
|
||||
assert(False)
|
||||
sig_sdram_interrupt = Signal(reset=1)
|
||||
# the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt)
|
||||
self.comb += pad_sdram_interrupt.eq(sig_sdram_interrupt)
|
||||
self.comb += sig_sdram_interrupt.eq(~self.exchange_with_mem.irq) ##
|
||||
else:
|
||||
self.submodules.tosbus_fifo = None
|
||||
self.submodules.fromsbus_fifo = None
|
||||
@ -432,12 +442,23 @@ class SBusFPGA(SoCCore):
|
||||
self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
|
||||
|
||||
if (usb):
|
||||
if (not single_dvma_master):
|
||||
self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
|
||||
else:
|
||||
if (single_dvma_master):
|
||||
self.comb += self.usb_host.wb_dma.connect(self.wishbone_slave_sys)
|
||||
|
||||
#self.add_sdcard()
|
||||
|
||||
if (sdcard):
|
||||
self.add_sdcard()
|
||||
#pad_sdcard_interrupt = platform.get_irq(irq_req=3, device="sdcard", next_down=True, next_up=False)
|
||||
#if (pad_sdcard_interrupt is None):
|
||||
# print(" ***** ERROR ***** sdcard requires an interrupt")
|
||||
# assert(False)
|
||||
#sig_sdcard_interrupt = Signal(reset=1)
|
||||
## the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt)
|
||||
#self.comb += pad_sdcard_interrupt.eq(sig_sdcard_interrupt)
|
||||
#self.comb += sig_sdcard_interrupt.eq(~self.sdirq.irq) ##
|
||||
|
||||
if (usb or engine or sdcard):
|
||||
if (not single_dvma_master):
|
||||
self.bus.add_slave(name="dvma_bridge", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("dvma_bridge", None), size=0x03ffffff, cached=False))
|
||||
|
||||
self.submodules.trng = NeoRV32TrngWrapper(platform=platform)
|
||||
|
||||
@ -506,6 +527,7 @@ def main():
|
||||
parser.add_argument("--cg3", action="store_true", help="add a CG3 framebuffer [V1.2+VGA_RGB222 pmod]")
|
||||
parser.add_argument("--cg3-res", default="1152x900@76Hz", help="Specify the CG3/CG6 resolution")
|
||||
parser.add_argument("--cg6", action="store_true", help="add a CG6 framebuffer [V1.2+VGA_RGB222 pmod]")
|
||||
parser.add_argument("--sdcard", action="store_true", help="add a sdcard {no SW yet}")
|
||||
builder_args(parser)
|
||||
vivado_build_args(parser)
|
||||
args = parser.parse_args()
|
||||
@ -534,7 +556,8 @@ def main():
|
||||
i2c=args.i2c,
|
||||
cg3=args.cg3,
|
||||
cg6=args.cg6,
|
||||
cg3_res=args.cg3_res)
|
||||
cg3_res=args.cg3_res,
|
||||
sdcard=args.sdcard)
|
||||
#soc.add_uart(name="uart", baudrate=115200, fifo_depth=16)
|
||||
|
||||
version_for_filename = args.version.replace(".", "_")
|
||||
@ -579,7 +602,8 @@ def main():
|
||||
i2c=args.i2c,
|
||||
cg3=args.cg3,
|
||||
cg6=args.cg6,
|
||||
cg3_res=args.cg3_res)
|
||||
cg3_res=args.cg3_res,
|
||||
sdcard=args.sdcard)
|
||||
write_to_file(os.path.join(f"prom_{version_for_filename}.fth"), prom_content)
|
||||
|
||||
|
||||
|
||||
@ -77,15 +77,15 @@ _sbus_io_v1_0 = [
|
||||
## sdcard connector
|
||||
("spisdcard", 0,
|
||||
Subsignal("clk", Pins("R8")),
|
||||
Subsignal("mosi", Pins("T5"), Misc("PULLUP")),
|
||||
Subsignal("cs_n", Pins("V6"), Misc("PULLUP")),
|
||||
Subsignal("miso", Pins("V5"), Misc("PULLUP")),
|
||||
Subsignal("mosi", Pins("T5"), Misc("PULLUP True")),
|
||||
Subsignal("cs_n", Pins("V6"), Misc("PULLUP True")),
|
||||
Subsignal("miso", Pins("V5"), Misc("PULLUP True")),
|
||||
Misc("SLEW=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
("sdcard", 0,
|
||||
Subsignal("data", Pins("V5 V4 V7 V6"), Misc("PULLUP")),
|
||||
Subsignal("cmd", Pins("T5"), Misc("PULLUP")),
|
||||
Subsignal("data", Pins("V5 V4 V7 V6"), Misc("PULLUP True")),
|
||||
Subsignal("cmd", Pins("T5"), Misc("PULLUP True")),
|
||||
Subsignal("clk", Pins("R8")),
|
||||
#Subsignal("cd", Pins("V6")),
|
||||
Misc("SLEW=FAST"),
|
||||
@ -104,15 +104,15 @@ _sbus_io_v1_2 = [
|
||||
## sdcard connector
|
||||
("spisdcard", 0,
|
||||
Subsignal("clk", Pins("R8")),
|
||||
Subsignal("mosi", Pins("T5"), Misc("PULLUP")),
|
||||
Subsignal("cs_n", Pins("V6"), Misc("PULLUP")),
|
||||
Subsignal("miso", Pins("V5"), Misc("PULLUP")),
|
||||
Subsignal("mosi", Pins("T5"), Misc("PULLUP True")),
|
||||
Subsignal("cs_n", Pins("V6"), Misc("PULLUP True")),
|
||||
Subsignal("miso", Pins("V5"), Misc("PULLUP True")),
|
||||
Misc("SLEW=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
("sdcard", 0,
|
||||
Subsignal("data", Pins("V5 V4 V7 V6"), Misc("PULLUP")),
|
||||
Subsignal("cmd", Pins("T5"), Misc("PULLUP")),
|
||||
Subsignal("data", Pins("V5 V4 V7 V6"), Misc("PULLUP True")),
|
||||
Subsignal("cmd", Pins("T5"), Misc("PULLUP True")),
|
||||
Subsignal("clk", Pins("R8")),
|
||||
#Subsignal("cd", Pins("V6")),
|
||||
Misc("SLEW=FAST"),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user