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support more Po2 FB sizes

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This commit is contained in:
Romain Dolbeau 2021-10-30 12:51:02 +02:00
parent 6f04a9bd73
commit afdfe4a686
5 changed files with 64 additions and 81 deletions
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5
sbus-to-ztex-gateware-migen/blit.c
View File

@ -13,7 +13,10 @@
#define VRES 1024
#warning "Using default VRES"
#endif
#define BASE_FB 0x8FE00000 // FIXME : should be generated ; 2+ MiB of SDRAM as framebuffer
#ifndef BASE_FB
#define BASE_FB 0x8FE00000 // FIXME : should be generated ; 2+ MiB of SDRAM as framebuffer
#warning "Using default BASE_FB"
#endif
#define BASE_ROM 0x00410000 // FIXME : should be generated ; 4-64 KiB of Wishbone ROM ? ; also in the LDS file ; also in the Vex config

9
sbus-to-ztex-gateware-migen/blit.sh
View File

@ -2,6 +2,7 @@
HRES=${1:-1280}
VRES=${2:-1024}
BASE_FB=0x8FE00000
GCCDIR=~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14
GCCPFX=riscv64-unknown-elf-
@ -19,9 +20,11 @@ OBJCOPY=${GCCDIR}/bin/${GCCPFX}objcopy
OPT=-Os #-fno-inline
ARCH=rv32i_zba_zbb_zbt
PARAM="-DHRES=${HRES} -DVRES=${VRES} -DBASE_FB=${BASE_FB}"
if test "x$1" != "xASM"; then
$GCC $OPT -S -o blit.s -DHRES=${HRES} -DVRES=${VRES} -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.c
$GCC $OPT -S -o blit.s $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.c
fi
$GCC $OPT -c -o blit.o -DHRES=${HRES} -DVRES=${VRES} -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.s &&
$GCCLINK $OPT -o blit -DHRES=${HRES} -DVRES=${VRES} -march=$ARCH -mabi=ilp32 -T blit.lds -nostartfiles blit.o &&
$GCC $OPT -c -o blit.o $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.s &&
$GCCLINK $OPT -o blit $PARAM -march=$ARCH -mabi=ilp32 -T blit.lds -nostartfiles blit.o &&
$OBJCOPY -O binary -j .text -j .rodata blit blit.raw

10
sbus-to-ztex-gateware-migen/cg3_fb.py
View File

@ -28,7 +28,15 @@ cg3_timings = {
}
def cg3_rounded_size(hres, vres):
return int(1048576 * ceil(((hres * vres) + 0) / 1048576))
mib = int(ceil(((hres * vres) + 0) / 1048576))
if (mib == 3):
mib = 4
if (mib > 4 and mib < 8):
mib = 8
if (mib > 8 or mib < 1):
print(f"{mib} mebibytes framebuffer not supported")
assert(False)
return int(1048576 * mib)
class VideoFrameBuffer256c(Module, AutoCSR):
"""Video FrameBuffer256c"""

119
sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
View File

@ -38,14 +38,6 @@ FBC_ROM_ADDR_PFX = Signal(12, reset = 0x041)
#FBC_RAM_ADDR_PFX = Signal(12, reset = 0x042)
CG6_FBC_ADDR_PFX = Signal(12, reset = 0x070)
ADDR_BIGPFX_HIGH = ADDR_PHYS_HIGH
ADDR_BIGPFX_LOW = 20 ## 1 MiB per bigprefix
ADDR_BIGPFX_LENGTH = 8 #(1 + ADDR_BIGPFX_HIGH - ADDR_BIGPFX_LOW)
CG3_PIXELS_ADDR_BIGPFX = Signal(8, reset = 0x08) # cg3_pixels, remapped, first MiB, LE
CG3_PIXELS_ADDR_BIGVAL = 0x08
CG3_PIXELS_ADDR2_BIGPFX = Signal(8, reset = 0x09) # cg3_pixels, remapped, second MiB, LE
CG3_PIXELS_ADDR2_BIGVAL = 0x09
wishbone_default_timeout = 120 ##
sbus_default_timeout = 50 ## must be below 255/2 (two waits)
sbus_default_master_throttle = 3
@ -199,16 +191,35 @@ class SBusFPGABus(Module):
self.fromsbus_fifo = fromsbus_fifo
self.fromsbus_req_fifo = fromsbus_req_fifo
if (cg3_fb_size <= 1048576): #round up to 1 MiB
if (cg3_fb_size == 1*1048576):
CG3_UPPER_BITS=12
CG3_KEPT_UPPER_BIT=20
elif (cg3_fb_size == (2*1048576)):
CG3_PIXELS_ADDR_BIGVAL = 0x08>>0
CG3_PIXELS_ADDR_BIGPFX = Signal(8, reset = CG3_PIXELS_ADDR_BIGVAL)
elif (cg3_fb_size == 2*1048576):
CG3_UPPER_BITS=11
CG3_KEPT_UPPER_BIT=21
CG3_PIXELS_ADDR_BIGVAL = 0x08>>1
CG3_PIXELS_ADDR_BIGPFX = Signal(7, reset = CG3_PIXELS_ADDR_BIGVAL)
elif (cg3_fb_size == 4*1048576):
CG3_UPPER_BITS=10
CG3_KEPT_UPPER_BIT=22
CG3_PIXELS_ADDR_BIGVAL = 0x08>>2
CG3_PIXELS_ADDR_BIGPFX = Signal(6, reset = CG3_PIXELS_ADDR_BIGVAL)
elif (cg3_fb_size == 8*1048576):
CG3_UPPER_BITS=9
CG3_KEPT_UPPER_BIT=23
CG3_PIXELS_ADDR_BIGVAL = 0x08>>3
CG3_PIXELS_ADDR_BIGPFX = Signal(5, reset = CG3_PIXELS_ADDR_BIGVAL)
else:
print(f"CG3 configuration ({cg3_fb_size//1048576} MiB) not yet supported\n")
print(f"{cg3_fb_size//1048576} mebibytes framebuffer not supported")
assert(False)
CG3_REMAPPED_BASE=cg3_base >> CG3_KEPT_UPPER_BIT
ADDR_BIGPFX_HIGH = ADDR_PHYS_HIGH
ADDR_BIGPFX_LOW = CG3_KEPT_UPPER_BIT ## x MiB per bigprefix
ADDR_BIGPFX_LENGTH = (1 + ADDR_BIGPFX_HIGH - ADDR_BIGPFX_LOW)
CG3_REMAPPED_BASE=cg3_base >> CG3_KEPT_UPPER_BIT # we always remapped to the appropriate range (e.g. the 2 MiB is mapped four times consecutively)
print(f"CG3 remapping: {cg3_fb_size//1048576} Mib starting at prefix {CG3_REMAPPED_BASE:x} ({(CG3_REMAPPED_BASE<<CG3_KEPT_UPPER_BIT):x})")
@ -482,14 +493,12 @@ class SBusFPGABus(Module):
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
NextValue(SBUS_3V3_ERRs_o, 1),
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
If(self.wishbone_master.cyc == 0,
NextValue(self.wishbone_master.cyc, 1),
@ -500,15 +509,11 @@ class SBusFPGABus(Module):
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
NextValue(wishbone_master_timeout, wishbone_default_timeout),
NextValue(sbus_slave_timeout, sbus_default_timeout),
@ -518,13 +523,10 @@ class SBusFPGABus(Module):
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
NextValue(sbus_slave_timeout, sbus_default_timeout),
NextState("Slave_Ack_Read_Reg_Burst_Wait_For_Wishbone")
@ -546,14 +548,12 @@ class SBusFPGABus(Module):
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
NextValue(SBUS_3V3_ERRs_o, 1),
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
If(self.wishbone_master.cyc == 0,
NextValue(self.wishbone_master.cyc, 1),
@ -564,15 +564,11 @@ class SBusFPGABus(Module):
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
NextValue(wishbone_master_timeout, wishbone_default_timeout),
NextValue(sbus_slave_timeout, sbus_default_timeout),
@ -582,13 +578,10 @@ class SBusFPGABus(Module):
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
NextValue(sbus_slave_timeout, sbus_default_timeout),
NextState("Slave_Ack_Read_Reg_Byte_Wait_For_Wishbone")
@ -616,14 +609,12 @@ class SBusFPGABus(Module):
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
NextValue(SBUS_3V3_ERRs_o, 1),
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
If(self.wishbone_master.cyc == 0,
NextValue(self.wishbone_master.cyc, 1),
@ -634,15 +625,11 @@ class SBusFPGABus(Module):
"default": [ NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:28], Signal(4, reset = 0))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(self.wishbone_master.adr, Cat(SBUS_3V3_PA_i[2:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
NextValue(wishbone_master_timeout, wishbone_default_timeout),
NextValue(sbus_slave_timeout, sbus_default_timeout),
@ -652,13 +639,10 @@ class SBusFPGABus(Module):
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM for CG3_PIXELS_ADDR_PFX
# next remap 8 MiB to Y MiB of SDRAM for CG3_PIXELS_ADDR_PFX
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
NextValue(sbus_slave_timeout, sbus_default_timeout),
NextState("Slave_Ack_Read_Reg_HWord_Wait_For_Wishbone")
@ -701,23 +685,18 @@ class SBusFPGABus(Module):
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM
# next remap 8 MiB to Y MiB of SDRAM
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
If(~self.wishbone_master.cyc,
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
@ -747,23 +726,18 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_master_in, 1),
If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM
# next remap 8 MiB to Y MiB of SDRAM
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
If(~self.wishbone_master.cyc,
NextValue(SBUS_3V3_ACKs_o, ACK_BYTE),
@ -799,23 +773,18 @@ class SBusFPGABus(Module):
NextState("Slave_Error")
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR2_BIGPFX)),
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
# next remap X MiB to last MiB of SDRAM
# next remap 8 MiB to Y MiB of SDRAM
CG3_PIXELS_ADDR_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
CG3_PIXELS_ADDR2_BIGVAL: [
NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i[0:CG3_KEPT_UPPER_BIT], Signal(CG3_UPPER_BITS, reset = CG3_REMAPPED_BASE))),
],
}),
If(~self.wishbone_master.cyc,
NextValue(SBUS_3V3_ACKs_o, ACK_HWORD),

2
sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
View File

@ -271,7 +271,7 @@ class SBusFPGA(SoCCore):
"cg6_accel_ram": 0x00420000, # R5 microcode working space (stack)
"cg6_fbc": 0x00700000, # required for compatibility
#"cg6_tec": 0x00701000, # required for compatibility
"cg3_pixels": 0x00800000, # required for compatibility, 1-2 MiB for now (2nd MiB is 0x00900000) (cg3 and cg6 idem)
"cg3_pixels": 0x00800000, # required for compatibility, 1/2/4/8 MiB for now (up to 0x00FFFFFF inclusive) (cg3 and cg6 idem)
"main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible),
"video_framebuffer":0x80000000 + 0x10000000 - cg3_fb_size, # FIXME
"usb_fake_dma": 0xfc000000, # required to match DVMA virtual addresses