cleanup, CSR for prom & netbsd (preliminary)
This commit is contained in:
Romain Dolbeau
133
sbus-to-ztex-gateware-migen/sbus_to_fpga_export.py
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133
sbus-to-ztex-gateware-migen/sbus_to_fpga_export.py
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@@ -0,0 +1,133 @@
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import os
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import json
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import inspect
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from shutil import which
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from sysconfig import get_platform
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from migen import *
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from litex.soc.interconnect.csr import CSRStatus
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from litex.build.tools import generated_banner
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from litex.soc.doc.rst import reflow
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from litex.soc.doc.module import gather_submodules, ModuleNotDocumented, DocumentedModule, DocumentedInterrupts
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from litex.soc.doc.csr import DocumentedCSRRegion
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from litex.soc.interconnect.csr import _CompoundCSR
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# for generating a timestamp in the description field, if none is otherwise given
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import datetime
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import time
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def _get_rw_functions_c(name, csr_name, reg_base, area_base, nwords, busword, alignment, read_only, with_access_functions):
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reg_name = name + "_" + csr_name
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r = ""
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addr_str = "CSR_{}_ADDR".format(reg_name.upper())
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size_str = "CSR_{}_SIZE".format(reg_name.upper())
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r += "#define {} (CSR_{}_BASE + {}L)\n".format(addr_str, name.upper(), hex(reg_base - area_base))
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r += "#define {} {}\n".format(size_str, nwords)
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size = nwords*busword//8
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if size > 8:
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# downstream should select appropriate `csr_[rd|wr]_buf_uintX()` pair!
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return r
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elif size > 4:
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ctype = "uint64_t"
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elif size > 2:
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ctype = "uint32_t"
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elif size > 1:
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ctype = "uint16_t"
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else:
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ctype = "uint8_t"
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stride = alignment//8;
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if with_access_functions:
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r += "static inline {} {}_read(struct sbusfpga_sdram_softc *sc) {{\n".format(ctype, reg_name)
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if nwords > 1:
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r += "\t{} r = bus_space_read_4(sc->sc_bustag, sc>sc_bhregs_{}, {}L);\n".format(ctype, name, hex(reg_base - area_base))
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for sub in range(1, nwords):
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r += "\tr <<= {};\n".format(busword)
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r += "\tr |= bus_space_read_4(sc->sc_bustag, sc>sc_bhregs_{}, {}L);\n".format(name, hex(reg_base - area_base + sub*stride))
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r += "\treturn r;\n}\n"
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else:
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r += "\treturn bus_space_read_4(sc->sc_bustag, sc>sc_bhregs_{}, {}L);\n}}\n".format(name, hex(reg_base - area_base))
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if not read_only:
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r += "static inline void {}_write(struct sbusfpga_sdram_softc *sc, {} v) {{\n".format(reg_name, ctype)
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for sub in range(nwords):
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shift = (nwords-sub-1)*busword
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if shift:
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v_shift = "v >> {}".format(shift)
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else:
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v_shift = "v"
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r += "\tbus_space_write_4(sc->sc_bustag, sc>sc_bhregs_{}, {}L, {});\n".format(name, hex(reg_base - area_base + sub*stride), v_shift)
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r += "}\n"
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return r
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def get_csr_header(regions, constants, csr_base=None, with_access_functions=True):
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alignment = constants.get("CONFIG_CSR_ALIGNMENT", 32)
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r = generated_banner("//")
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#if with_access_functions: # FIXME
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# r += "#include <generated/soc.h>\n"
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r += "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n"
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#if with_access_functions:
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# r += "#include <stdint.h>\n"
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# r += "#include <system.h>\n"
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# r += "#ifndef CSR_ACCESSORS_DEFINED\n"
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# r += "#include <hw/common.h>\n"
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# r += "#endif /* ! CSR_ACCESSORS_DEFINED */\n"
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csr_base = csr_base if csr_base is not None else regions[next(iter(regions))].origin
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r += "#ifndef CSR_BASE\n"
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r += "#define CSR_BASE {}L\n".format(hex(csr_base))
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r += "#endif\n"
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for name, region in regions.items():
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origin = region.origin - csr_base
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r += "\n/* "+name+" */\n"
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r += "#ifndef CSR_"+name.upper()+"_BASE\n"
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r += "#define CSR_"+name.upper()+"_BASE (CSR_BASE + "+hex(origin)+"L)\n"
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r += "#endif\n"
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if not isinstance(region.obj, Memory):
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for csr in region.obj:
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nr = (csr.size + region.busword - 1)//region.busword
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r += _get_rw_functions_c(name, csr.name, origin, region.origin - csr_base, nr, region.busword, alignment,
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getattr(csr, "read_only", False), with_access_functions)
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origin += alignment//8*nr
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if hasattr(csr, "fields"):
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for field in csr.fields.fields:
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offset = str(field.offset)
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size = str(field.size)
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r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_OFFSET "+offset+"\n"
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r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_SIZE "+size+"\n"
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if with_access_functions and csr.size <= 32: # FIXME: Implement extract/read functions for csr.size > 32-bit.
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reg_name = name + "_" + csr.name.lower()
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field_name = reg_name + "_" + field.name.lower()
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r += "static inline uint32_t " + field_name + "_extract(struct sbusfpga_sdram_softc *sc, uint32_t oldword) {\n"
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r += "\tuint32_t mask = ((1 << " + size + ")-1);\n"
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r += "\treturn ( (oldword >> " + offset + ") & mask );\n}\n"
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r += "static inline uint32_t " + field_name + "_read(struct sbusfpga_sdram_softc *sc) {\n"
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r += "\tuint32_t word = " + reg_name + "_read(sc);\n"
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r += "\treturn " + field_name + "_extract(word);\n"
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r += "}\n"
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if not getattr(csr, "read_only", False):
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r += "static inline uint32_t " + field_name + "_replace(struct sbusfpga_sdram_softc *sc, uint32_t oldword, uint32_t plain_value) {\n"
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r += "\tuint32_t mask = ((1 << " + size + ")-1);\n"
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r += "\treturn (oldword & (~(mask << " + offset + "))) | (mask & plain_value)<< " + offset + " ;\n}\n"
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r += "static inline void " + field_name + "_write(struct sbusfpga_sdram_softc *sc, uint32_t plain_value) {\n"
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r += "\tuint32_t oldword = " + reg_name + "_read(sc);\n"
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r += "\tuint32_t newword = " + field_name + "_replace(sc, oldword, plain_value);\n"
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r += "\t" + reg_name + "_write(sc, newword);\n"
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r += "}\n"
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r += "\n#endif\n"
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return r
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def get_csr_forth_header(csr_regions, mem_regions, constants, csr_base=None):
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r = "\\ auto-generated base regions for CSRs in the PROM\n"
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for name, region in csr_regions.items():
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_csraddr_{}".format(name) + "\n"
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for name, region in mem_regions.items():
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_regionaddr_{}".format(name) + "\n"
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return r
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@@ -18,6 +18,8 @@ from litedram.phy import s7ddrphy
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from sbus_to_fpga_fsm import *;
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import sbus_to_fpga_export;
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_sbus_sbus = [
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("SBUS_3V3_CLK", 0, Pins("D15"), IOStandard("lvttl")),
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("SBUS_3V3_ASs", 0, Pins("T4"), IOStandard("lvttl")),
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@@ -98,7 +100,7 @@ class _CRG(Module):
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self.submodules.pll_idelay = pll_idelay = S7PLL(speedgrade=-1)
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pll_idelay.register_clkin(clk48, 48e6)
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pll_idelay.create_clkout(self.cd_idelay, 200e6)
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pll_idelay.create_clkout(self.cd_idelay, 200e6, margin = 0)
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self.comb += pll_idelay.reset.eq(~rst_sbus) # | ~por_done
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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@@ -122,6 +124,13 @@ class SBusFPGA(SoCCore):
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clk_freq=sys_clk_freq,
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csr_paging=0x1000, # default is 0x800
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**kwargs)
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# This mem-map is also exposed in the FSM (matched prefixes)
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# and in the PROM (to tell NetBSD where everything is)
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# Currently it is a straight mapping between the two:
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# the physical address here are used as offset in the SBus
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# reserved area of 256 MiB
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# Anything at 0x10000000 is therefore unreachable directly
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wb_mem_map = {
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"prom": 0x00000000,
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"csr" : 0x00040000,
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@@ -180,66 +189,8 @@ class SBusFPGA(SoCCore):
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hold_reset = Signal(reset=1)
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self.comb += hold_reset.eq(~(hold_reset_ctr == 0))
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# FIFO to send data & address from SBus to the Wishbone
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##sbus_to_wishbone_wr_fifo = AsyncFIFOBuffered(width=32+30, depth=16)
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##sbus_to_wishbone_wr_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(sbus_to_wishbone_wr_fifo)
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##self.submodules += sbus_to_wishbone_wr_fifo
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# FIFOs to send address / receive data from SBus to the Wishbone
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##sbus_to_wishbone_rd_fifo_addr = AsyncFIFOBuffered(width=30, depth=16)
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##sbus_to_wishbone_rd_fifo_addr = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(sbus_to_wishbone_rd_fifo_addr)
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##self.submodules += sbus_to_wishbone_rd_fifo_addr
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##sbus_to_wishbone_rd_fifo_data = AsyncFIFOBuffered(width=32+1, depth=16)
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##sbus_to_wishbone_rd_fifo_data = ClockDomainsRenamer({"write": "sys", "read": "sbus"})(sbus_to_wishbone_rd_fifo_data)
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##self.submodules += sbus_to_wishbone_rd_fifo_data
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# SBus to Wishbone, 'Slave' on the SBus side, 'Master' on the Wishbone side
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##self.submodules.sbus_to_wishbone = SBusToWishbone(platform=self.platform,
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## wr_fifo=sbus_to_wishbone_wr_fifo,
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## rd_fifo_addr=sbus_to_wishbone_rd_fifo_addr,
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## rd_fifo_data=sbus_to_wishbone_rd_fifo_data,
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## wishbone=wishbone.Interface(data_width=self.bus.data_width))
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# FIFO to send data & address from Wishbone to the SBus
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##wishbone_to_sbus_wr_fifo = AsyncFIFOBuffered(width=32+30, depth=16)
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##wishbone_to_sbus_wr_fifo = ClockDomainsRenamer({"write": "sys", "read": "sbus"})(wishbone_to_sbus_wr_fifo)
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##self.submodules += wishbone_to_sbus_wr_fifo
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# FIFOs to send address / receive data from Wishbone to the SBus
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##wishbone_to_sbus_rd_fifo_addr = AsyncFIFOBuffered(width=30, depth=4)
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##wishbone_to_sbus_rd_fifo_addr = ClockDomainsRenamer({"write": "sys", "read": "sbus"})(wishbone_to_sbus_rd_fifo_addr)
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##self.submodules += wishbone_to_sbus_rd_fifo_addr
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##wishbone_to_sbus_rd_fifo_data = AsyncFIFOBuffered(width=32+1, depth=4)
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##wishbone_to_sbus_rd_fifo_data = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(wishbone_to_sbus_rd_fifo_data)
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##self.submodules += wishbone_to_sbus_rd_fifo_data
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# Wishbone to SBus, 'Master' on the SBus side, 'Slave' on the Wishbone side
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##self.submodules.wishbone_to_sbus = WishboneToSBus(platform=self.platform,
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## soc=self,
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## wr_fifo=wishbone_to_sbus_wr_fifo,
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## rd_fifo_addr=wishbone_to_sbus_rd_fifo_addr,
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## rd_fifo_data=wishbone_to_sbus_rd_fifo_data,
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## wishbone=wishbone.Interface(data_width=self.bus.data_width))
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##_sbus_bus = SBusFPGABus(platform=self.platform,
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## prom=prom,
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## hold_reset=hold_reset,
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## wr_fifo=sbus_to_wishbone_wr_fifo,
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## rd_fifo_addr=sbus_to_wishbone_rd_fifo_addr,
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## rd_fifo_data=sbus_to_wishbone_rd_fifo_data,
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## master_wr_fifo=wishbone_to_sbus_wr_fifo,
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## master_rd_fifo_addr=wishbone_to_sbus_rd_fifo_addr,
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## master_rd_fifo_data=wishbone_to_sbus_rd_fifo_data)
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##self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus)
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#wishbone_slave = wishbone.Interface(data_width=self.bus.data_width)
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#wishbone_master = wishbone.Interface(data_width=self.bus.data_width)
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#wishbone_slave = wishbone.Interface(data_width=self.bus.data_width)
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#wishbone_master = wishbone.Interface(data_width=self.bus.data_width)
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# Interface SBus to wishbone
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# we need to cross clock domains
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wishbone_slave_sbus = wishbone.Interface(data_width=self.bus.data_width)
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wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_master_sbus = wishbone.WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="sbus", cd_slave="sys")
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@@ -253,11 +204,6 @@ class SBusFPGA(SoCCore):
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#self.submodules.sbus_bus = _sbus_bus
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self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus)
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##self.bus.add_master(name="SBusBridgeToWishbone", master=self.sbus_to_wishbone.wishbone)
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##self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_to_sbus.wishbone, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
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#self.bus.add_master(name="SBusBridgeToWishbone", master=self.sbus_bus.wishbone_master)
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#self.bus.add_slave(name="usb_fake_dma", slave=self.sbus_bus.wishbone_slave, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
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self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
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self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
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@@ -273,18 +219,6 @@ class SBusFPGA(SoCCore):
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l2_cache_size = 0
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)
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# self.soc = Module()
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# self.soc.mem_regions = self.mem_regions = {}
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# region = litex.soc.integration.soc.SoCRegion(origin=0x0, size=0x0)
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# region.length = 0
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# self.mem_regions['csr'] = region
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# self.soc.constants = self.constants = {}
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# self.soc.csr_regions = self.csr_regions = {}
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# self.soc.cpu_type = self.cpu_type = None
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# def do_finalize(self):
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# self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6)
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def main():
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parser = argparse.ArgumentParser(description="SbusFPGA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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@@ -298,5 +232,20 @@ def main():
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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# Generate modified CSR registers definitions/access functions to netbsd_csr.h.
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csr_contents = sbus_to_fpga_export.get_csr_header(
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regions = soc.csr_regions,
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constants = soc.constants,
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csr_base = soc.mem_regions['csr'].origin)
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write_to_file(os.path.join("netbsd_csr.h"), csr_contents)
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# tells the prom where to find what
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csr_forth_contents = sbus_to_fpga_export.get_csr_forth_header(
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csr_regions = soc.csr_regions,
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mem_regions = soc.mem_regions,
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constants = soc.constants,
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csr_base = soc.mem_regions['csr'].origin)
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write_to_file(os.path.join("prom_csr.fth"), csr_forth_contents)
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if __name__ == "__main__":
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main()
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