switch sdram access from Wishbone to dedicated port, seems to be more reliable
This commit is contained in:
Romain Dolbeau
parent
2f5b4eecfb
commit
c5e9a025b4
@ -1,5 +1,5 @@
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//--------------------------------------------------------------------------------
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// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-07-17 11:01:08
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// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-07-18 04:58:11
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//--------------------------------------------------------------------------------
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#ifndef __GENERATED_CSR_H
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#define __GENERATED_CSR_H
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@ -5,6 +5,6 @@ h# 42000 constant sbusfpga_csraddr_exchange_with_mem
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h# 43000 constant sbusfpga_csraddr_sdram
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h# 80000 constant sbusfpga_regionaddr_usb_host_ctrl
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h# 0 constant sbusfpga_regionaddr_prom
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h# fc000000 constant sbusfpga_regionaddr_usb_fake_dma
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h# 80000000 constant sbusfpga_regionaddr_main_ram
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h# fc000000 constant sbusfpga_regionaddr_usb_fake_dma
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h# 40000 constant sbusfpga_regionaddr_csr
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@ -9,22 +9,29 @@ from litex.soc.interconnect import wishbone
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# width of fromsbus_fifo is 'blk_addr_width' + 'burst_size * 32' (blk_addr + data)
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# the blk_addr does the round-trip to accompany the data
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class ExchangeWithMem(Module, AutoCSR):
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def __init__(self, soc, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, burst_size = 8):
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self.wishbone_r_slave = wishbone.Interface(data_width=soc.bus.data_width)
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self.wishbone_w_slave = wishbone.Interface(data_width=soc.bus.data_width)
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def __init__(self, soc, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, dram_dma_writer, dram_dma_reader, burst_size = 8):
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#self.wishbone_r_slave = wishbone.Interface(data_width=soc.bus.data_width)
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#self.wishbone_w_slave = wishbone.Interface(data_width=soc.bus.data_width)
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self.tosbus_fifo = tosbus_fifo
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self.fromsbus_fifo = fromsbus_fifo
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self.fromsbus_req_fifo = fromsbus_req_fifo
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self.dram_dma_writer = dram_dma_writer
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self.dram_dma_reader = dram_dma_reader
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data_width = burst_size * 4
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data_width_bits = burst_size * 32
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blk_addr_width = 32 - log2_int(data_width) # 27 for burst_size == 8
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self.wishbone_r_master = wishbone.Interface(data_width=data_width_bits)
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self.wishbone_w_master = wishbone.Interface(data_width=data_width_bits)
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self.submodules += wishbone.Converter(self.wishbone_r_master, self.wishbone_r_slave)
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self.submodules += wishbone.Converter(self.wishbone_w_master, self.wishbone_w_slave)
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assert(len(self.dram_dma_writer.sink.data == data_width_bits))
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assert(len(self.dram_dma_reader.source.data == data_width_bits))
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assert(len(self.dram_dma_writer.sink.address == blk_addr_width))
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assert(len(self.dram_dma_reader.sink.address == blk_addr_width))
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#self.wishbone_r_master = wishbone.Interface(data_width=data_width_bits)
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#self.wishbone_w_master = wishbone.Interface(data_width=data_width_bits)
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#self.submodules += wishbone.Converter(self.wishbone_r_master, self.wishbone_r_slave)
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#self.submodules += wishbone.Converter(self.wishbone_w_master, self.wishbone_w_slave)
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print("ExchangeWithMem: data_width = {}, data_width_bits = {}, blk_addr_width = {}\n".format(data_width, data_width_bits, blk_addr_width))
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print("ExchangeWithMem: tosbus_fifo width = {}, fromsbus_fifo width = {}, fromsbus_req_fifo width = {}\n".format(len(tosbus_fifo.din), len(fromsbus_fifo.dout), len(fromsbus_req_fifo.din)))
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@ -49,14 +56,14 @@ class ExchangeWithMem(Module, AutoCSR):
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self.comb += self.blk_size.status.eq(data_width)
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self.comb += self.blk_base.status.eq(soc.wb_mem_map["main_ram"] >> log2_int(data_width))
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self.blk_addr = CSRStorage(32, description = "SDRAM Block address to read/write from Wishbone memory (block of size {})".format(data_width))
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self.dma_addr = CSRStorage(32, description = "Host Base address where to write/read data (i.e. SPARC Virtual addr)")
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self.blk_cnt = CSRStorage(32, write_from_dev=True, description = "How many blk to read/write (max 2^{}-1); bit 31 is RD".format(max_block_bits), reset = 0)
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self.last_blk = CSRStatus(32, description = "Last Blk addr finished on WB side")
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self.last_dma = CSRStatus(32, description = "Last DMA addr finished on WB side")
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self.blk_rem = CSRStatus(32, description = "How many block remaining; bit 31 is RD", reset = 0)
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self.blk_addr = CSRStorage(32, description = "SDRAM Block address to read/write from Wishbone memory (block of size {})".format(data_width))
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self.dma_addr = CSRStorage(32, description = "Host Base address where to write/read data (i.e. SPARC Virtual addr)")
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self.blk_cnt = CSRStorage(32, write_from_dev=True, description = "How many blk to read/write (max 2^{}-1); bit 31 is RD".format(max_block_bits), reset = 0)
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self.last_blk = CSRStatus(32, description = "Last Blk addr finished on WB side")
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self.last_dma = CSRStatus(32, description = "Last DMA addr finished on WB side")
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self.blk_rem = CSRStatus(32, description = "How many block remaining; bit 31 is RD", reset = 0)
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self.dma_status = CSRStatus(32, description = "Status register")
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self.wr_tosdram = CSRStatus(32, description = "Last address written to SDRAM")
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self.wr_tosdram = CSRStatus(32, description = "Last address written to SDRAM")
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self.submodules.req_r_fsm = req_r_fsm = FSM(reset_state="Reset")
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self.submodules.req_w_fsm = req_w_fsm = FSM(reset_state="Reset")
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@ -68,17 +75,17 @@ class ExchangeWithMem(Module, AutoCSR):
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self.comb += self.dma_status.status[8:9].eq(req_w_fsm.ongoing("ReqToMemory"))
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self.comb += self.dma_status.status[9:10].eq(req_w_fsm.ongoing("WaitForAck"))
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self.comb += self.dma_status.status[16:17].eq(self.wishbone_w_master.cyc) # show the WB iface status (W)
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self.comb += self.dma_status.status[17:18].eq(self.wishbone_w_master.stb)
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self.comb += self.dma_status.status[18:19].eq(self.wishbone_w_master.we)
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self.comb += self.dma_status.status[19:20].eq(self.wishbone_w_master.ack)
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self.comb += self.dma_status.status[20:21].eq(self.wishbone_w_master.err)
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#self.comb += self.dma_status.status[16:17].eq(self.wishbone_w_master.cyc) # show the WB iface status (W)
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#self.comb += self.dma_status.status[17:18].eq(self.wishbone_w_master.stb)
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#self.comb += self.dma_status.status[18:19].eq(self.wishbone_w_master.we)
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#self.comb += self.dma_status.status[19:20].eq(self.wishbone_w_master.ack)
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#self.comb += self.dma_status.status[20:21].eq(self.wishbone_w_master.err)
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self.comb += self.dma_status.status[24:25].eq(self.wishbone_r_master.cyc) # show the WB iface status (R)
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self.comb += self.dma_status.status[25:26].eq(self.wishbone_r_master.stb)
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self.comb += self.dma_status.status[26:27].eq(self.wishbone_r_master.we)
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self.comb += self.dma_status.status[27:28].eq(self.wishbone_r_master.ack)
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self.comb += self.dma_status.status[28:29].eq(self.wishbone_r_master.err)
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#self.comb += self.dma_status.status[24:25].eq(self.wishbone_r_master.cyc) # show the WB iface status (R)
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#self.comb += self.dma_status.status[25:26].eq(self.wishbone_r_master.stb)
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#self.comb += self.dma_status.status[26:27].eq(self.wishbone_r_master.we)
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#self.comb += self.dma_status.status[27:28].eq(self.wishbone_r_master.ack)
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#self.comb += self.dma_status.status[28:29].eq(self.wishbone_r_master.err)
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req_r_fsm.act("Reset",
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NextState("Idle")
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@ -99,35 +106,31 @@ class ExchangeWithMem(Module, AutoCSR):
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)
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)
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req_r_fsm.act("ReqFromMemory",
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If(~self.wishbone_r_master.ack,
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NextValue(self.wishbone_r_master.cyc, 1),
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NextValue(self.wishbone_r_master.stb, 1),
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NextValue(self.wishbone_r_master.sel, 2**len(self.wishbone_r_master.sel)-1),
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NextValue(self.wishbone_r_master.we, 0),
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NextValue(self.wishbone_r_master.adr, local_r_addr),
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NextState("WaitForData")
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)
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self.dram_dma_reader.sink.address.eq(local_r_addr),
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self.dram_dma_reader.sink.valid.eq(1),
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If(self.dram_dma_reader.sink.ready,
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NextState("WaitForData")
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)
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)
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req_r_fsm.act("WaitForData",
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If(self.wishbone_r_master.ack &
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self.tosbus_fifo.writable,
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NextValue(self.wishbone_r_master.cyc, 0),
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NextValue(self.wishbone_r_master.stb, 0),
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tosbus_fifo.we.eq(1),
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tosbus_fifo.din.eq(Cat(dma_r_addr, self.wishbone_r_master.dat_r)),
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NextValue(self.last_blk.status, local_r_addr),
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NextValue(self.last_dma.status, dma_r_addr),
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NextValue(self.blk_rem.status, self.blk_rem.status - 1),
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If(self.blk_rem.status[0:max_block_bits] <= 1,
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self.blk_cnt.we.eq(1), ## auto-reset
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self.blk_cnt.dat_w.eq(0),
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NextState("Idle"),
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).Else(
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NextValue(local_r_addr, local_r_addr + 1),
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NextValue(dma_r_addr, dma_r_addr + data_width),
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NextState("ReqFromMemory"),
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)
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)
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If(self.dram_dma_reader.source.valid &
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self.tosbus_fifo.writable,
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self.tosbus_fifo.we.eq(1),
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self.tosbus_fifo.din.eq(Cat(dma_r_addr, self.dram_dma_reader.source.data)),
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self.dram_dma_reader.source.ready.eq(1),
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NextValue(self.last_blk.status, local_r_addr),
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NextValue(self.last_dma.status, dma_r_addr),
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NextValue(self.blk_rem.status, self.blk_rem.status - 1),
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If(self.blk_rem.status[0:max_block_bits] <= 1,
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self.blk_cnt.we.eq(1), ## auto-reset
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self.blk_cnt.dat_w.eq(0),
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NextState("Idle"),
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).Else(
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NextValue(local_r_addr, local_r_addr + 1),
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NextValue(dma_r_addr, dma_r_addr + data_width),
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NextState("ReqFromMemory"),
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)
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)
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)
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req_r_fsm.act("QueueReqToMemory",
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If(self.fromsbus_req_fifo.writable,
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@ -150,27 +153,42 @@ class ExchangeWithMem(Module, AutoCSR):
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)
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# req_w_fsm.act("Reset",
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# NextState("Idle")
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# )
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# req_w_fsm.act("Idle",
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# If(self.fromsbus_fifo.readable &
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# ~self.wishbone_w_master.ack,
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# self.fromsbus_fifo.re.eq(1),
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# NextValue(self.wishbone_w_master.cyc, 1),
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# NextValue(self.wishbone_w_master.stb, 1),
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# NextValue(self.wishbone_w_master.sel, 2**len(self.wishbone_w_master.sel)-1),
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# NextValue(self.wishbone_w_master.we, 1),
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# NextValue(self.wishbone_w_master.adr, self.fromsbus_fifo.dout[0:blk_addr_width]),
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# NextValue(self.wishbone_w_master.dat_w, self.fromsbus_fifo.dout[blk_addr_width:(blk_addr_width + data_width_bits)]),
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# NextValue(self.wr_tosdram.status, self.fromsbus_fifo.dout[0:blk_addr_width]),
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# NextState("WaitForAck")
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# )
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# )
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# req_w_fsm.act("WaitForAck",
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# If(self.wishbone_w_master.ack,
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# NextValue(self.wishbone_w_master.cyc, 0),
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# NextValue(self.wishbone_w_master.stb, 0),
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# NextState("Idle"),
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# )
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# )
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req_w_fsm.act("Reset",
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NextState("Idle")
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)
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req_w_fsm.act("Idle",
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If(self.fromsbus_fifo.readable &
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~self.wishbone_w_master.ack,
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self.fromsbus_fifo.re.eq(1),
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NextValue(self.wishbone_w_master.cyc, 1),
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NextValue(self.wishbone_w_master.stb, 1),
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NextValue(self.wishbone_w_master.sel, 2**len(self.wishbone_w_master.sel)-1),
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NextValue(self.wishbone_w_master.we, 1),
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NextValue(self.wishbone_w_master.adr, self.fromsbus_fifo.dout[0:blk_addr_width]),
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NextValue(self.wishbone_w_master.dat_w, self.fromsbus_fifo.dout[blk_addr_width:(blk_addr_width + data_width_bits)]),
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NextValue(self.wr_tosdram.status, self.fromsbus_fifo.dout[0:blk_addr_width]),
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NextState("WaitForAck")
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)
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)
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req_w_fsm.act("WaitForAck",
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If(self.wishbone_w_master.ack,
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NextValue(self.wishbone_w_master.cyc, 0),
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NextValue(self.wishbone_w_master.stb, 0),
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NextState("Idle"),
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)
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If(self.fromsbus_fifo.readable,
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self.dram_dma_writer.sink.address.eq(self.fromsbus_fifo.dout[0:blk_addr_width]),
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self.dram_dma_writer.sink.data.eq(self.fromsbus_fifo.dout[blk_addr_width:(blk_addr_width + data_width_bits)]),
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self.dram_dma_writer.sink.valid.eq(1),
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NextValue(self.wr_tosdram.status, self.fromsbus_fifo.dout[0:blk_addr_width]),
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If(self.dram_dma_writer.sink.ready,
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self.fromsbus_fifo.re.eq(1)
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)
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)
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)
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@ -16,8 +16,10 @@ from migen.genlib.fifo import *
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from sbus_to_fpga_fsm import *;
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from sbus_to_fpga_blk_dma import *;
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from sbus_to_fpga_fsm import *
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from sbus_to_fpga_blk_dma import *
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from litedram.frontend.dma import *
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import sbus_to_fpga_export;
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@ -156,6 +158,15 @@ class SBusFPGA(SoCCore):
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#getattr(self,"prom").mem.init = prom_data
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#getattr(self,"prom").mem.depth = 2**14
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 0,
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)
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# don't enable anything on the SBus side for 20 seconds after power up
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# this avoids FPGA initialization messing with the cold boot process
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# requires us to reset the SPARCstation afterward so the FPGA board
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@ -178,10 +189,20 @@ class SBusFPGA(SoCCore):
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+burst_size*32), depth=4))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+32), depth=16))
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self.submodules.dram_dma_writer = LiteDRAMDMAWriter(port=self.sdram.crossbar.get_port(mode="write", data_width=burst_size*32),
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fifo_depth=4,
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fifo_buffered=True)
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self.submodules.dram_dma_reader = LiteDRAMDMAReader(port=self.sdram.crossbar.get_port(mode="read", data_width=burst_size*32),
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fifo_depth=4,
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fifo_buffered=True)
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self.submodules.exchange_with_mem = ExchangeWithMem(soc=self,
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tosbus_fifo=self.tosbus_fifo,
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fromsbus_fifo=self.fromsbus_fifo,
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fromsbus_req_fifo=self.fromsbus_req_fifo,
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dram_dma_writer=self.dram_dma_writer,
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dram_dma_reader=self.dram_dma_reader,
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burst_size=burst_size)
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_sbus_bus = SBusFPGABus(platform=self.platform,
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@ -197,18 +218,8 @@ class SBusFPGA(SoCCore):
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self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
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self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
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self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_slave)
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self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_slave)
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 0,
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)
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#self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_slave)
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#self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_slave)
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#self.add_sdcard()
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