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This commit is contained in:
Romain Dolbeau
2022-06-26 09:44:08 +02:00
parent 5b26ac9c25
commit c5efbba648
7 changed files with 3950 additions and 3181 deletions
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4
NetBSD/9.0/usr/src/sys/dev/sbus/goblin.c
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@@ -161,9 +161,9 @@ static int jareth_fillrop(struct goblin_softc *sc, enum jareth_verbosity verbose
static int jareth_copy(struct goblin_softc *sc, enum jareth_verbosity verbose, int y0, int y1, int x0, int w, int n, int x1, int rop);
static int jareth_copyrev(struct goblin_softc *sc, enum jareth_verbosity verbose, int y0, int y1, int x0, int w, int n, int x1, int rop);
static const uint32_t program_fill[35] = { 0x10000089,0x0f8000c9,0x01bc0014,0x0780000d,0x013c2014,0x001400c0,0x00180000,0x403c0192,0xc03c1033,0x00184185,0x00161146,0xfd800148,0x00226007,0x00208946,0x0020220f,0x00008005,0x00088086,0x01048050,0x07000089,0x001a6087,0x013c6814,0x403c0012,0x00146086,0x01800149,0xe03c1013,0x00165146,0xfe800148,0x0080018d,0xc03c1033,0x000e10c6,0x010000c9,0x00004005,0xfa000809,0x0000000a,0x0000000a };
static const uint32_t program_fill[35] = { 0x10000089,0x0f8000c9,0x01bc0014,0x0780000d,0x013c2014,0x001400c0,0x00180000,0x403c0192,0xc03c1033,0x00184185,0x00161146,0xfd800148,0x00226007,0x00208946,0x0020220f,0x00008005,0x00088086,0x01048050,0x07000089,0x001a6087,0x013c6814,0x403c0012,0x00146086,0x01800149,0xe03c1013,0x00165146,0xfe800148,0x0080018e,0xc03c1033,0x000e10c6,0x010000c9,0x00004005,0xfa000809,0x0000000a,0x0000000a };
static const uint32_t program_fillrop[42] = { 0x13800089,0x130000c9,0x01bc0014,0x003c014c,0x0880000d,0x013c2014,0x002000c0,0x00180000,0x403c0192,0x801c0013,0x001c11e2,0xc03c7013,0x00184185,0x00221206,0xfc800208,0x00226007,0x00208946,0x0020220f,0x00008005,0x00088086,0x01048050,0x09000089,0x001a6087,0x013c6814,0x403c0012,0x00206086,0x02800209,0x801c0013,0x001c11c2,0xe03c7013,0x00225206,0xfd800208,0x0180018d,0x801c0013,0x001c11e2,0xc03c7013,0x000e10c6,0x010000c9,0x00004005,0xf8000809,0x0000000a,0x0000000a };
static const uint32_t program_fillrop[42] = { 0x13800089,0x130000c9,0x01bc0014,0x003c014c,0x0880000d,0x013c2014,0x002000c0,0x00180000,0x403c0192,0x801c0013,0x001c11e2,0xc03c7013,0x00184185,0x00221206,0xfc800208,0x00226007,0x00208946,0x0020220f,0x00008005,0x00088086,0x01048050,0x09000089,0x001a6087,0x013c6814,0x403c0012,0x00206086,0x02800209,0x801c0013,0x001c11c2,0xe03c7013,0x00225206,0xfd800208,0x0180018e,0x801c0013,0x001c11e2,0xc03c7013,0x000e10c6,0x010000c9,0x00004005,0xf8000809,0x0000000a,0x0000000a };
static const uint32_t program_copy[43] = { 0x14000089,0x138000c9,0x01bc0014,0x013c2014,0x00bf0054,0x0900000d,0x002400c0,0x00180000,0x403c0192,0x80a00013,0x403c8033,0x00184185,0x00261246,0xfd000248,0x0026f007,0x00249c06,0x0024224f,0x00240250,0x00009005,0x00089086,0x0a000089,0x013f0814,0x00049045,0x00bf0054,0x001af087,0x403c0012,0x00246086,0xa0a00013,0x02000249,0x603c8033,0x00270246,0x20a08015,0xfe000248,0x0180018d,0x013c6814,0x403c8033,0x013f0814,0x000e10c6,0x010000c9,0x00004005,0xf8000809,0x0000000a,0x0000000a };

6370
sbus-to-ztex-gateware-migen/VexRiscv_FbAccel.v
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File diff suppressed because it is too large Load Diff

77
sbus-to-ztex-gateware-migen/cg6_accel.py
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@@ -5,6 +5,9 @@ from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone
from litedram.common import LiteDRAMNativePort
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
#from cg6_blit import CG6Blit
class CG6Accel(Module): # AutoCSR ?
@@ -348,9 +351,59 @@ class CG6Accel(Module): # AutoCSR ?
]
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
#self.dbus = dbus = wishbone.Interface()
vex_reset = Signal()
dbus_raw = wishbone.Interface(data_width=128, adr_width=28) # wide interface from the Vex, master
dbus_sys = wishbone.Interface(data_width=128, adr_width=28) # wide interface to system wishbone
dbus_mem = wishbone.Interface(data_width=128, adr_width=28) # wide interface for direct memory access
self.dbus = dbus_sys
self.comb += [
If((dbus_raw.adr[24:28] == 0x8),
dbus_sys.cyc.eq(0),
dbus_sys.stb.eq(0),
dbus_mem.cyc.eq(dbus_raw.cyc),
dbus_mem.stb.eq(dbus_raw.stb),
dbus_raw.ack.eq(dbus_mem.ack),
dbus_raw.err.eq(dbus_mem.err),
dbus_raw.dat_r.eq(dbus_mem.dat_r),
).Else(
dbus_sys.cyc.eq(dbus_raw.cyc),
dbus_sys.stb.eq(dbus_raw.stb),
dbus_mem.cyc.eq(0),
dbus_mem.stb.eq(0),
dbus_raw.ack.eq(dbus_sys.ack),
dbus_raw.err.eq(dbus_sys.err),
dbus_raw.dat_r.eq(dbus_sys.dat_r),
),
dbus_sys.dat_w.eq(dbus_raw.dat_w),
dbus_mem.dat_w.eq(dbus_raw.dat_w),
dbus_sys.we.eq(dbus_raw.we),
dbus_mem.we.eq(dbus_raw.we),
dbus_sys.adr.eq(dbus_raw.adr),
dbus_mem.adr.eq(dbus_raw.adr),
dbus_sys.sel.eq(dbus_raw.sel),
dbus_mem.sel.eq(dbus_raw.sel),
dbus_sys.cti.eq(dbus_raw.cti),
dbus_mem.cti.eq(dbus_raw.cti),
dbus_sys.bte.eq(dbus_raw.bte),
dbus_mem.bte.eq(dbus_raw.bte),
]
# now connect the memory
# memory port
port = soc.sdram.crossbar.get_port()
assert(port.data_width == 128)
self.submodules.wb2native = LiteDRAMWishbone2Native(
wishbone = dbus_mem,
port = port,
base_address = soc.bus.regions["main_ram"].origin
)
self.comb += vex_reset.eq(ResetSignal("sys") | local_reset)
self.specials += Instance(self.get_netlist_name(),
i_clk = ClockSignal("sys"),
@@ -366,17 +419,17 @@ class CG6Accel(Module): # AutoCSR ?
i_iBusWishbone_ERR = ibus.err,
o_iBusWishbone_CTI = ibus.cti,
o_iBusWishbone_BTE = ibus.bte,
o_dBusWishbone_CYC = dbus.cyc,
o_dBusWishbone_STB = dbus.stb,
i_dBusWishbone_ACK = dbus.ack,
o_dBusWishbone_WE = dbus.we,
o_dBusWishbone_ADR = dbus.adr,
i_dBusWishbone_DAT_MISO = dbus.dat_r,
o_dBusWishbone_DAT_MOSI = dbus.dat_w,
o_dBusWishbone_SEL = dbus.sel,
i_dBusWishbone_ERR = dbus.err,
o_dBusWishbone_CTI = dbus.cti,
o_dBusWishbone_BTE = dbus.bte,)
o_dBusWishbone_CYC = dbus_raw.cyc,
o_dBusWishbone_STB = dbus_raw.stb,
i_dBusWishbone_ACK = dbus_raw.ack,
o_dBusWishbone_WE = dbus_raw.we,
o_dBusWishbone_ADR = dbus_raw.adr,
i_dBusWishbone_DAT_MISO = dbus_raw.dat_r,
o_dBusWishbone_DAT_MOSI = dbus_raw.dat_w,
o_dBusWishbone_SEL = dbus_raw.sel,
i_dBusWishbone_ERR = dbus_raw.err,
o_dBusWishbone_CTI = dbus_raw.cti,
o_dBusWishbone_BTE = dbus_raw.bte,)
self.add_sources(platform)

357
sbus-to-ztex-gateware-migen/jareth.py
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@@ -5,6 +5,9 @@ from litex.soc.interconnect.csr import *
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr_eventmanager import *
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
from cache import *
prime_string = "$2^{{255}}-19$" # 2\ :sup:`255`-19
field_latex = "$\mathbf{{F}}_{{{{2^{{255}}}}-19}}$"
@@ -52,7 +55,8 @@ opcodes = { # mnemonic : [bit coding, docstring] ; if bit 6 (0x20) is set, shif
# imm[0..2]: adr reg
"LOADH" : [21, "LOADH: high->low & load *Adr into high" ],
"LOADL" : [22, "LOADL: low->high & load *Adr into low" ],
"MAX" : [23, "Maximum opcode number (for bounds checking)"],
"PRF0" : [23, "PRF0: configure and start prefetch engine 0" ],
"MAX" : [24, "Maximum opcode number (for bounds checking)"],
}
num_registers = 32
@@ -447,8 +451,8 @@ class ExecRop(ExecUnit, AutoDoc):
NextState("IDLE"));
class ExecLS(ExecUnit, AutoDoc):
def __init__(self, width=256, interface=None, memoryport=None, r_dat_f=None, r_dat_m=None, granule=0):
ExecUnit.__init__(self, width, ["MEM", "SETM", "ADR", "LOADH", "LOADL", "GETM"])
def __init__(self, width=256, wish_nocache=None, wish_cache=None, prefetcher=None, r_dat_f=None, r_dat_m=None, granule=0):
ExecUnit.__init__(self, width, ["MEM", "SETM", "ADR", "LOADH", "LOADL", "GETM", "PRF0"])
self.notes = ModuleDoc(title=f"Load/Store ExecUnit Subclass", body=f"""
""")
@@ -458,9 +462,8 @@ class ExecLS(ExecUnit, AutoDoc):
]
assert(width == 256) # fixme
assert((len(interface.sel) == 16)) # 128 bits Wishbone
assert((len(memoryport.rdata.data) == 128)) # 128 bits memory
assert((len(memoryport.wdata.data) == 128)) # 128 bits memory
assert((len(wish_nocache.sel) == 16)) # 128 bits Wishbone
assert((len(wish_cache.sel) == 16)) # 128 bits Wishbone
start_pipe = Signal()
self.sync.mul_clk += start_pipe.eq(self.start) # break critical path of instruction decode -> SETUP_A state muxes
@@ -485,25 +488,27 @@ class ExecLS(ExecUnit, AutoDoc):
addresses = Array(Signal(28) for x in range(width//32)) # 128-bits chunk, so 16-bytes chunk, so low 4 bits are ignored
address = Signal(28)
wishbone = Signal()
#if ((interface != None) and (memoryport != None)):
# self.comb += [ wishbone.eq(addresses[self.instruction.immediate[0:log2_int(width//32)]][24:28] != 0x8), ] # fixme ; 0x8 is SDRAM memory map prefix
#else:
# if (interface == None):
# self.comb += [ wishbone.eq(0), ]
# else: # memoryport == None
# self.comb += [ wishbone.eq(1), ]
uncacheable = Signal()
#if (memoryport != None):
self.comb += [ memoryport.rdata.ready.eq(1),
memoryport.wdata.we.eq(Replicate(1, len(memoryport.wdata.we))), ]
if (prefetcher is not None):
handle_prefetch = [
Case(self.instruction.immediate[0:2], {
0x0: [ NextValue(prefetcher.start, 0), ],
0x1: [ NextValue(prefetcher.cnt_x, self.a[4:]), NextValue(prefetcher.cnt_y, self.b[0:]), ],
0x2: [ NextValue(prefetcher.inc_x, self.a[0:]), NextValue(prefetcher.inc_y, self.b[4:]), ], # fixme
0x3: [ NextValue(prefetcher.base, self.a[4:]), NextValue(prefetcher.start, 1),],
}),
]
else:
handle_prefetch = [
]
lsseq.act("IDLE",
If(start_pipe,
If((self.instruction.opcode == opcodes["MEM"][0]) | (self.instruction.opcode == opcodes["LOADH"][0]) | (self.instruction.opcode == opcodes["LOADL"][0]),
NextValue(cpar, 0),
NextValue(address, addresses[self.instruction.immediate[0:log2_int(width//32)]]),
NextValue(wishbone, ~(addresses[self.instruction.immediate[0:log2_int(width//32)]][24:28] == 0x8)),
NextValue(uncacheable, ~(addresses[self.instruction.immediate[0:log2_int(width//32)]][24:28] == 0x8)),
NextState("DOMEM"),
).Elif(self.instruction.opcode == opcodes["SETM"][0],
Case(self.instruction.immediate[0:2],
@@ -538,6 +543,9 @@ class ExecLS(ExecUnit, AutoDoc):
NextState("MEM_ODD")
).Elif(self.instruction.opcode == opcodes["GETM"][0],
NextState("MEM_ODD")
).Elif(self.instruction.opcode == opcodes["PRF0"][0],
*handle_prefetch,
NextState("MEM_ODD")
)
)
)
@@ -548,68 +556,76 @@ class ExecLS(ExecUnit, AutoDoc):
NextValue(self.has_timeout, 0),
NextValue(self.has_failure, 0),
NextValue(timeout, 2047),
If(wishbone,
NextValue(interface.cyc, 1),
NextValue(interface.stb, 1),
NextValue(interface.adr, address),
NextValue(interface.we, self.instruction.immediate[7]),
NextValue(interface.sel, 2**len(interface.sel)-1),
If(uncacheable,
NextValue(wish_nocache.cyc, 1),
NextValue(wish_nocache.stb, 1),
NextValue(wish_nocache.adr, address),
NextValue(wish_nocache.we, self.instruction.immediate[7]),
NextValue(wish_nocache.sel, 2**len(wish_nocache.sel)-1),
If(self.instruction.immediate[7], # do we need those tests or could we always update dat_w/dat_r ?
If(self.instruction.shift,
NextValue(interface.dat_w, (self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[0:128]),
NextValue(interface.sel, r_dat_m[2][0:16]),
NextValue(wish_nocache.dat_w, (self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[0:128]),
NextValue(wish_nocache.sel, r_dat_m[2][0:16]),
).Else(
NextValue(interface.dat_w, self.b[0:128]),
NextValue(wish_nocache.dat_w, self.b[0:128]),
),
),
NextState("MEMl") # MEMl
).Else(
memoryport.cmd.we.eq(self.instruction.immediate[7]),
memoryport.cmd.addr.eq(address[0:]),
memoryport.cmd.valid.eq(1),
If(memoryport.cmd.ready,
NextState("MEMl")
)
NextValue(wish_cache.cyc, 1),
NextValue(wish_cache.stb, 1),
NextValue(wish_cache.adr, address),
NextValue(wish_cache.we, self.instruction.immediate[7]),
NextValue(wish_cache.sel, 2**len(wish_cache.sel)-1),
If(self.instruction.immediate[7], # do we need those tests or could we always update dat_w/dat_r ?
If(self.instruction.shift,
NextValue(wish_cache.dat_w, (self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[0:128]),
NextValue(wish_cache.sel, r_dat_m[2][0:16]),
).Else(
NextValue(wish_cache.dat_w, self.b[0:128]),
),
),
NextState("MEMl") # MEMl
),
).Elif(self.instruction.opcode == opcodes["LOADH"][0],
NextValue(self.has_timeout, 0),
NextValue(self.has_failure, 0),
NextValue(timeout, 2047),
NextValue(lbuf[0:128], self.b[128:256]),
If(wishbone,
NextValue(interface.cyc, 1),
NextValue(interface.stb, 1),
NextValue(interface.sel, 2**len(interface.sel)-1),
NextValue(interface.adr, address),
NextValue(interface.we, self.instruction.immediate[7]),
If(uncacheable,
NextValue(wish_nocache.cyc, 1),
NextValue(wish_nocache.stb, 1),
NextValue(wish_nocache.sel, 2**len(wish_nocache.sel)-1),
NextValue(wish_nocache.adr, address),
NextValue(wish_nocache.we, self.instruction.immediate[7]),
NextState("MEMh") # MEMl
).Else(
memoryport.cmd.we.eq(self.instruction.immediate[7]),
memoryport.cmd.addr.eq(address[0:]),
memoryport.cmd.valid.eq(1),
If(memoryport.cmd.ready,
NextState("MEMh")
)
NextValue(wish_cache.cyc, 1),
NextValue(wish_cache.stb, 1),
NextValue(wish_cache.sel, 2**len(wish_cache.sel)-1),
NextValue(wish_cache.adr, address),
NextValue(wish_cache.we, self.instruction.immediate[7]),
NextState("MEMh") # MEMl
)
).Elif(self.instruction.opcode == opcodes["LOADL"][0],
NextValue(self.has_timeout, 0),
NextValue(self.has_failure, 0),
NextValue(timeout, 2047),
NextValue(lbuf[128:256], self.b[0:128]),
If(wishbone,
NextValue(interface.cyc, 1),
NextValue(interface.stb, 1),
NextValue(interface.sel, 2**len(interface.sel)-1),
NextValue(interface.adr, address),
NextValue(interface.we, self.instruction.immediate[7]),
If(uncacheable,
NextValue(wish_nocache.cyc, 1),
NextValue(wish_nocache.stb, 1),
NextValue(wish_nocache.sel, 2**len(wish_nocache.sel)-1),
NextValue(wish_nocache.adr, address),
NextValue(wish_nocache.we, self.instruction.immediate[7]),
NextState("MEMl")
).Else(
memoryport.cmd.we.eq(self.instruction.immediate[7]),
memoryport.cmd.addr.eq(address[0:]),
memoryport.cmd.valid.eq(1),
If(memoryport.cmd.ready,
NextState("MEMl")
)
NextValue(wish_cache.cyc, 1),
NextValue(wish_cache.stb, 1),
NextValue(wish_cache.sel, 2**len(wish_cache.sel)-1),
NextValue(wish_cache.adr, address),
NextValue(wish_cache.we, self.instruction.immediate[7]),
NextState("MEMl")
)
)
)
@@ -651,58 +667,60 @@ class ExecLS(ExecUnit, AutoDoc):
)
lsseq.act("MEMl",
NextValue(cpar, cpar ^ 1),
If(wishbone & interface.ack,
If(uncacheable & wish_nocache.ack,
If(~self.instruction.immediate[7],
NextValue(lbuf[0:128], interface.dat_r)),
NextValue(interface.cyc, 0),
NextValue(interface.stb, 0),
NextValue(lbuf[0:128], wish_nocache.dat_r)),
NextValue(wish_nocache.cyc, 0),
NextValue(wish_nocache.stb, 0),
NextState("MEMl2")
).Elif(wishbone & interface.err,
).Elif(uncacheable & wish_nocache.err,
NextValue(self.has_failure[0], 1),
NextValue(interface.cyc, 0),
NextValue(interface.stb, 0),
NextValue(wish_nocache.cyc, 0),
NextValue(wish_nocache.stb, 0),
NextState("ERR"),
).Elif(~uncacheable & wish_cache.ack,
If(~self.instruction.immediate[7],
NextValue(lbuf[0:128], wish_cache.dat_r)),
NextValue(wish_cache.cyc, 0),
NextValue(wish_cache.stb, 0),
NextState("MEMl2")
).Elif(~uncacheable & wish_cache.err,
NextValue(self.has_failure[0], 1),
NextValue(wish_cache.cyc, 0),
NextValue(wish_cache.stb, 0),
NextState("ERR"),
).Elif(~wishbone & ~self.instruction.immediate[7] & memoryport.rdata.valid,
NextValue(lbuf[0:128], memoryport.rdata.data),
NextState("MEMl2"),
).Elif(~wishbone & self.instruction.immediate[7],
memoryport.wdata.valid.eq(1),
If(self.instruction.shift,
memoryport.wdata.data.eq((self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[0:128]),
memoryport.wdata.we.eq(r_dat_m[2][0:16]),
).Else(
memoryport.wdata.data.eq(self.b[0:128]),
),
If(memoryport.wdata.ready,
NextState("MEMl2"),
),
).Elif(timeout == 0,
NextValue(self.has_timeout[0], 1),
NextValue(interface.cyc, 0),
NextValue(interface.stb, 0),
If(uncacheable,
NextValue(wish_nocache.cyc, 0),
NextValue(wish_nocache.stb, 0),
).Else(
NextValue(wish_cache.cyc, 0),
NextValue(wish_cache.stb, 0),
),
NextState("ERR"),
))
lsseq.act("MEMl2",
NextValue(cpar, cpar ^ 1),
If(wishbone & ~interface.ack,
If(uncacheable & ~wish_nocache.ack,
If(self.instruction.immediate[6], # post-inc
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] + 1),
).Elif(self.instruction.immediate[5], # post-dec
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] - 1),
),
If(self.instruction.immediate[8],
NextValue(interface.cyc, 1),
NextValue(interface.stb, 1),
NextValue(interface.adr, address + 1),
NextValue(interface.we, self.instruction.immediate[7]),
NextValue(interface.sel, 2**len(interface.sel)-1),
NextValue(wish_nocache.cyc, 1),
NextValue(wish_nocache.stb, 1),
NextValue(wish_nocache.adr, address + 1),
NextValue(wish_nocache.we, self.instruction.immediate[7]),
NextValue(wish_nocache.sel, 2**len(wish_nocache.sel)-1),
NextValue(timeout, 2047),
If(self.instruction.immediate[7],
If(self.instruction.shift,
NextValue(interface.dat_w, (self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[128:256]),
NextValue(interface.sel, r_dat_m[2][16:32]),
NextValue(wish_nocache.dat_w, (self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[128:256]),
NextValue(wish_nocache.sel, r_dat_m[2][16:32]),
).Else(
NextValue(interface.dat_w, self.b[128:256]),
NextValue(wish_nocache.dat_w, self.b[128:256]),
),
),
NextState("MEMh")
@@ -716,72 +734,79 @@ class ExecLS(ExecUnit, AutoDoc):
NextState("MEM_EVEN1")
)
)
).Elif(~wishbone,
If(self.instruction.immediate[8],
memoryport.cmd.we.eq(self.instruction.immediate[7]),
memoryport.cmd.addr.eq(address[0:] + 1),
memoryport.cmd.valid.eq(1),
NextValue(timeout, 2047),
If(memoryport.cmd.ready,
If(self.instruction.immediate[6], # post-inc
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] + 1),
).Elif(self.instruction.immediate[5], # post-dec
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] - 1),
),
NextState("MEMh"),
)
).Else( # no high
If(self.instruction.immediate[6], # post-inc
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] + 1),
).Elif(self.instruction.immediate[5], # post-dec
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] - 1),
),
If(self.instruction.opcode == opcodes["MEM"][0],
NextValue(lbuf[128:256], 0),
),
If(cpar,
NextState("MEM_ODD")
).Else(
NextState("MEM_EVEN1")
)
),
If(~uncacheable & ~wish_cache.ack,
If(self.instruction.immediate[6], # post-inc
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] + 1),
).Elif(self.instruction.immediate[5], # post-dec
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] - 1),
),
If(self.instruction.immediate[8],
NextValue(wish_cache.cyc, 1),
NextValue(wish_cache.stb, 1),
NextValue(wish_cache.adr, address + 1),
NextValue(wish_cache.we, self.instruction.immediate[7]),
NextValue(wish_cache.sel, 2**len(wish_cache.sel)-1),
NextValue(timeout, 2047),
If(self.instruction.immediate[7],
If(self.instruction.shift,
NextValue(wish_cache.dat_w, (self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[128:256]),
NextValue(wish_cache.sel, r_dat_m[2][16:32]),
).Else(
NextValue(wish_cache.dat_w, self.b[128:256]),
),
),
NextState("MEMh")
).Else(
If(self.instruction.opcode == opcodes["MEM"][0],
NextValue(lbuf[128:256], 0),
),
))
If(cpar,
NextState("MEM_ODD")
).Else(
NextState("MEM_EVEN1")
)
)
),
)
lsseq.act("MEMh",
NextValue(cpar, cpar ^ 1),
If(wishbone & interface.ack,
If(uncacheable & wish_nocache.ack,
If(~self.instruction.immediate[7],
NextValue(lbuf[128:256], interface.dat_r)),
NextValue(interface.cyc, 0),
NextValue(interface.stb, 0),
NextValue(lbuf[128:256], wish_nocache.dat_r)),
NextValue(wish_nocache.cyc, 0),
NextValue(wish_nocache.stb, 0),
NextState("MEMh2")
).Elif(wishbone & interface.err,
).Elif(uncacheable & wish_nocache.err,
NextValue(self.has_failure[1], 1),
NextValue(interface.cyc, 0),
NextValue(interface.stb, 0),
NextValue(wish_nocache.cyc, 0),
NextValue(wish_nocache.stb, 0),
NextState("ERR"),
).Elif(~uncacheable & wish_cache.ack,
If(~self.instruction.immediate[7],
NextValue(lbuf[128:256], wish_cache.dat_r)),
NextValue(wish_cache.cyc, 0),
NextValue(wish_cache.stb, 0),
NextState("MEMh2")
).Elif(~uncacheable & wish_cache.err,
NextValue(self.has_failure[1], 1),
NextValue(wish_cache.cyc, 0),
NextValue(wish_cache.stb, 0),
NextState("ERR"),
).Elif(~wishbone & ~self.instruction.immediate[7] & memoryport.rdata.valid,
NextValue(lbuf[128:256], memoryport.rdata.data),
NextState("MEMh2"),
).Elif(~wishbone & self.instruction.immediate[7],
memoryport.wdata.valid.eq(1),
If(self.instruction.shift,
memoryport.wdata.data.eq((self.b << (Cat(Signal(granule_bits, reset = 0), r_dat_f[2])))[128:256]),
memoryport.wdata.we.eq(r_dat_m[2][16:32]),
).Else(
memoryport.wdata.data.eq(self.b[128:256]),
),
If(memoryport.wdata.ready,
NextState("MEMh2"),
),
).Elif(timeout == 0,
NextValue(self.has_timeout[1], 1),
NextValue(interface.cyc, 0),
NextValue(interface.stb, 0),
If(uncacheable,
NextValue(wish_nocache.cyc, 0),
NextValue(wish_nocache.stb, 0),
).Else(
NextValue(wish_cache.cyc, 0),
NextValue(wish_cache.stb, 0),
),
NextState("ERR"),
))
lsseq.act("MEMh2",
NextValue(cpar, cpar ^ 1),
If(wishbone & ~interface.ack,
If(uncacheable & ~wish_nocache.ack,
If(self.instruction.immediate[6], # post-inc
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] + 1),
).Elif(self.instruction.immediate[5], # post-dec
@@ -793,18 +818,21 @@ class ExecLS(ExecUnit, AutoDoc):
).Else(
NextState("MEM_EVEN1")
)
).Elif(~wishbone,
If(self.instruction.immediate[6], # post-inc
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] + 1),
).Elif(self.instruction.immediate[5], # post-dec
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] - 1),
),
If(cpar,
NextState("MEM_ODD")
).Else(
NextState("MEM_EVEN1")
)
))
),
If(~uncacheable & ~wish_cache.ack,
If(self.instruction.immediate[6], # post-inc
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] + 1),
).Elif(self.instruction.immediate[5], # post-dec
NextValue(addresses[self.instruction.immediate[0:log2_int(width//32)]], addresses[self.instruction.immediate[0:log2_int(width//32)]] - 1),
),
#NextValue(tries, 0),
If(cpar,
NextState("MEM_ODD")
).Else(
NextState("MEM_EVEN1")
)
),
)
lsseq.act("MEM_ODD", # clock alignement cycle
NextState("MEM_EVEN1"))
lsseq.act("MEM_EVEN1",
@@ -813,7 +841,8 @@ class ExecLS(ExecUnit, AutoDoc):
NextValue(cpar, 0),
NextValue(self.has_failure, 0),
NextValue(self.has_timeout, 0),
NextState("IDLE"))
NextState("IDLE"),
)
lsseq.act("ERR",
#If(~tries, # second attempt
# NextValue(cpar, 0),
@@ -1442,15 +1471,25 @@ Here are the currently implemented opcodes for The Engine:
)
)
#pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
#led = Signal(reset = 1)
#self.comb += pad_SBUS_DATA_OE_LED.eq(led)
pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
led = Signal(reset = 1)
self.comb += pad_SBUS_DATA_OE_LED.eq(led)
self.busls = wishbone.Interface(data_width = 128, adr_width = 28) # FIXME: hardwired (here and elsewhere)
self.busls_cached = wishbone.Interface(data_width = 128, adr_width = 28)
self.busls_internal = wishbone.Interface(data_width = 128, adr_width = 28)
self.submodules.w2n = LiteDRAMWishbone2Native(self.busls_internal, memoryport, base_address=0x80000000) # fixme
self.submodules.cache = CacheWithPrefetch(cachesize=(32*1024)//(128//8), memsize=16*(1024**2), ahead=(16*1024)//(128//8), master=self.busls_cached, slave=self.busls_internal)
self.comb += led.eq(self.cache.cache.fsm.ongoing("PASSTHROUGH"))
#self.comb += led.eq(self.cache.cache.fsm.ongoing("PREFETCH") | self.cache.cache.fsm.ongoing("PREFETCH_FILL") | self.cache.cache.fsm.ongoing("PREFETCH_EVICT"))
#self.comb += led.eq(self.cache.pgen.gen.fifo.readable)
exec_units = {
"exec_logic" : ExecLogic(width=rf_width_raw),
"exec_addsub" : ExecAddSub(width=rf_width_raw),
"exec_rop" : ExecRop(width=rf_width_raw),
"exec_ls" : ExecLS(width=rf_width_raw, interface=self.busls, memoryport=memoryport, r_dat_f=r_dat_f, r_dat_m=r_dat_m, granule=granule),
"exec_ls" : ExecLS(width=rf_width_raw, wish_nocache=self.busls, wish_cache=self.busls_cached, prefetcher=self.cache, r_dat_f=r_dat_f, r_dat_m=r_dat_m, granule=granule),
##"exec_ls" : ExecLS(width=rf_width_raw, wish_nocache=self.busls, wish_cache=self.busls_internal, prefetcher=None, r_dat_f=r_dat_f, r_dat_m=r_dat_m, granule=granule),
}
exec_units_shift = {
"exec_logic": True,

258
sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
View File

@@ -183,7 +183,7 @@ LED_M_READ = 0x20
LED_M_CACHE = 0x40
class SBusFPGABus(Module):
def __init__(self, soc, platform, hold_reset, wishbone_slave, wishbone_master, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, version, burst_size = 8, cg3_fb_size = 0, cg3_base=0x8ff00000 ):
def __init__(self, soc, platform, stat, hold_reset, wishbone_slave, wishbone_master, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, version, burst_size = 8, cg3_fb_size = 0, cg3_base=0x8ff00000 ):
self.platform = platform
self.hold_reset = hold_reset
@@ -441,22 +441,47 @@ class SBusFPGABus(Module):
# slave_fsm.ongoing("Slave_Ack_Reg_Write_Byte_Wait_For_Wishbone"))
#self.sync += platform.request("user_led", 5).eq(~slave_fsm.ongoing("Idle"))
stat_slave_start_counter = Signal(32)
stat_slave_done_counter = Signal(32)
stat_slave_rerun_counter = Signal(32)
stat_slave_early_error_counter = Signal(32)
sbus_master_last_virtual = Signal(32) # last VDMA address put on the bus in master mode
if (stat):
stat_slave_early_error_counter = Signal(32)
increment_stat_slave_early_error_counter = [ NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1) ]
stat_slave_start_counter = Signal(32)
increment_stat_slave_start_counter = [ NextValue(stat_slave_start_counter, stat_slave_start_counter + 1) ]
stat_slave_done_counter = Signal(32)
increment_stat_slave_done_counter = [ NextValue(stat_slave_done_counter, stat_slave_done_counter + 1) ]
stat_slave_rerun_counter = Signal(32)
increment_stat_slave_rerun_counter = [ NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1) ]
else:
increment_stat_slave_early_error_counter = [ ]
increment_stat_slave_start_counter = [ ]
increment_stat_slave_done_counter = [ ]
increment_stat_slave_rerun_counter = [ ]
#self.stat_slave_rerun_last_pa = stat_slave_rerun_last_pa = Signal(32)
#self.stat_slave_rerun_last_state = stat_slave_rerun_last_state = Signal(32)
stat_master_start_counter = Signal(32)
stat_master_done_counter = Signal(32)
stat_master_error_counter = Signal(32)
stat_master_rerun_counter = Signal(32)
sbus_master_last_virtual = Signal(32) # last VDMA address put on the bus in master mode
sbus_master_error_virtual = Signal(32)
if (stat):
print("Enabling statistics collection on the SBus FSM")
stat_master_start_counter = Signal(32)
increment_stat_master_start_counter = [ NextValue(stat_master_start_counter, stat_master_start_counter + 1) ]
stat_master_done_counter = Signal(32)
increment_stat_master_done_counter = [ NextValue(stat_master_done_counter, stat_master_done_counter + 1) ]
stat_master_error_counter = Signal(32)
increment_stat_master_error_counter = [ NextValue(stat_master_error_counter, stat_master_error_counter + 1) ]
stat_master_rerun_counter = Signal(32)
increment_stat_master_rerun_counter = [ NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1) ]
sbus_master_error_virtual = Signal(32)
copy_sbus_master_last_virtual_to_error = [ NextValue(sbus_master_error_virtual, sbus_master_last_virtual) ]
else:
increment_stat_master_start_counter = [ ]
increment_stat_master_done_counter = [ ]
increment_stat_master_error_counter = [ ]
increment_stat_master_rerun_counter = [ ]
copy_sbus_master_last_virtual_to_error = [ ]
slave_fsm.act("Reset",
#NextValue(self.led_display.value, 0x0000000000),
NextValue(sbus_oe_data, 0),
@@ -499,7 +524,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_PARITY),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
@@ -522,7 +547,7 @@ class SBusFPGABus(Module):
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
*increment_stat_slave_start_counter,
If(self.wishbone_master.cyc == 0,
NextValue(self.wishbone_master.cyc, 1),
NextValue(self.wishbone_master.stb, 1),
@@ -559,7 +584,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
)
@@ -579,7 +604,7 @@ class SBusFPGABus(Module):
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
*increment_stat_slave_start_counter,
If(self.wishbone_master.cyc == 0,
NextValue(self.wishbone_master.cyc, 1),
NextValue(self.wishbone_master.stb, 1),
@@ -616,7 +641,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
)
@@ -630,7 +655,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_PARITY),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
@@ -644,7 +669,7 @@ class SBusFPGABus(Module):
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
*increment_stat_slave_start_counter,
If(self.wishbone_master.cyc == 0,
NextValue(self.wishbone_master.cyc, 1),
NextValue(self.wishbone_master.stb, 1),
@@ -681,7 +706,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
)
@@ -703,7 +728,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_PARITY),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
@@ -723,7 +748,7 @@ class SBusFPGABus(Module):
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
*increment_stat_slave_start_counter,
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
@@ -749,7 +774,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
)
@@ -766,7 +791,7 @@ class SBusFPGABus(Module):
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
*increment_stat_slave_start_counter,
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
@@ -792,7 +817,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
)
@@ -806,7 +831,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_PARITY),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
@@ -817,7 +842,7 @@ class SBusFPGABus(Module):
NextValue(sbus_wishbone_le,
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
NextValue(stat_slave_start_counter, stat_slave_start_counter + 1),
*increment_stat_slave_start_counter,
Case(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH], {
"default": [ NextValue(sbus_last_pa, Cat(SBUS_3V3_PA_i, Signal(4, reset = 0))),
],
@@ -843,7 +868,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(led0123, led0123 | LED_ADDRESS),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
)
@@ -874,7 +899,7 @@ class SBusFPGABus(Module):
NextValue(burst_counter, 0),
NextValue(SBUS_3V3_D_o, sbus_master_last_virtual),
NextValue(SBUS_3V3_PPRD_o, 1),
#NextValue(stat_master_start_counter, stat_master_start_counter + 1),
#*increment_stat_master_start_counter,
NextState("Master_Translation"),
).Elif(SBUS_3V3_BGs_i &
self.wishbone_slave.cyc &
@@ -961,7 +986,7 @@ class SBusFPGABus(Module):
NextValue(master_we, 1),
#NextValue(self.led_display.value, 0x0000000010 | Cat(Signal(8, reset = 0x00), self.wishbone_slave.adr)),
#NextValue(self.led_display.value, Cat(Signal(8, reset = LED_M_WRITE), Signal(2, reset = 0), self.wishbone_slave.adr)),
NextValue(stat_master_start_counter, stat_master_start_counter + 1),
*increment_stat_master_start_counter,
NextState("Master_Translation")
).Elif(SBUS_3V3_BGs_i &
self.master_read_buffer_start &
@@ -985,7 +1010,7 @@ class SBusFPGABus(Module):
NextValue(master_we, 0),
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0x00), self.wishbone_slave.adr)),
#NextValue(self.led_display.value, Cat(Signal(8, reset = LED_M_READ), Signal(2, reset = 0), self.master_read_buffer_addr)),
NextValue(stat_master_start_counter, stat_master_start_counter + 1),
*increment_stat_master_start_counter,
NextState("Master_Translation")
).Elif(SBUS_3V3_BGs_i &
self.tosbus_fifo.readable &
@@ -1019,7 +1044,7 @@ class SBusFPGABus(Module):
}),
NextValue(SBUS_3V3_PPRD_o, 0),
NextValue(master_we, 1),
NextValue(stat_master_start_counter, stat_master_start_counter + 1),
*increment_stat_master_start_counter,
NextState("Master_Translation")
).Elif(SBUS_3V3_BGs_i &
self.fromsbus_req_fifo.readable &
@@ -1053,7 +1078,7 @@ class SBusFPGABus(Module):
}),
NextValue(SBUS_3V3_PPRD_o, 1),
NextValue(master_we, 0),
NextValue(stat_master_start_counter, stat_master_start_counter + 1),
*increment_stat_master_start_counter,
NextState("Master_Translation")
).Elif(((SBUS_3V3_SELs_i == 0) &
(SBUS_3V3_ASs_i == 0)),
@@ -1062,7 +1087,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ERRs_o, 1),
#NextValue(self.led_display.value, 0x000000000F | Cat(Signal(8, reset = 0x00), SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, SBUS_3V3_PPRD_i)),
#NextValue(led0123, led0123 | LED_UNKNOWNREQ),
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
*increment_stat_slave_early_error_counter,
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
NextState("Slave_Error")
).Elif(~SBUS_3V3_BGs_i,
@@ -1080,7 +1105,7 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
If(((SBUS_3V3_ASs_i == 1) | ((SBUS_3V3_ASs_i == 0) & (SBUS_3V3_SELs_i == 1))),
NextValue(stat_slave_done_counter, stat_slave_done_counter + 1),
*increment_stat_slave_done_counter,
NextState("Idle")
)
)
@@ -1128,7 +1153,7 @@ class SBusFPGABus(Module):
NextValue(wishbone_master_timeout, 0),
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WORD | LED_RERUN_LATE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000001),
NextState("Slave_Error")
@@ -1149,7 +1174,7 @@ class SBusFPGABus(Module):
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WORD),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000002),
NextState("Slave_Error")
@@ -1194,7 +1219,7 @@ class SBusFPGABus(Module):
NextValue(wishbone_master_timeout, 0),
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_LATE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000003),
NextState("Slave_Error")
@@ -1215,7 +1240,7 @@ class SBusFPGABus(Module):
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000004),
NextState("Slave_Error")
@@ -1258,7 +1283,7 @@ class SBusFPGABus(Module):
NextValue(wishbone_master_timeout, 0),
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_LATE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000005),
NextState("Slave_Error")
@@ -1279,7 +1304,7 @@ class SBusFPGABus(Module):
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000006),
NextState("Slave_Error")
@@ -1320,7 +1345,7 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
If(((SBUS_3V3_ASs_i == 1) | ((SBUS_3V3_ASs_i == 0) & (SBUS_3V3_SELs_i == 1))),
NextValue(stat_slave_done_counter, stat_slave_done_counter + 1),
*increment_stat_slave_done_counter,
NextState("Idle")
)
)
@@ -1334,7 +1359,7 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(self.led_display.value, Cat(Signal(8, reset = LED_RERUN | LED_RERUN_WRITE | LED_RERUN_WORD), sbus_last_pa)),
#NextValue(led0123, LED_RERUN | LED_RERUN_WRITE | LED_RERUN_WORD),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000007),
NextState("Slave_Error")
@@ -1379,7 +1404,7 @@ class SBusFPGABus(Module):
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WRITE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000008),
NextState("Slave_Error")
@@ -1424,7 +1449,7 @@ class SBusFPGABus(Module):
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WRITE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
*increment_stat_slave_rerun_counter,
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000009),
NextState("Slave_Error")
@@ -1501,8 +1526,8 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_error_counter, stat_master_error_counter + 1),
NextValue(sbus_master_error_virtual, sbus_master_last_virtual),
*increment_stat_master_error_counter,
*copy_sbus_master_last_virtual_to_error,
NextState("Idle")],
ACK_RERUN: ### dunno how to handle that yet,
[Case(master_src, {
@@ -1518,7 +1543,7 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1),
*increment_stat_master_rerun_counter,
NextState("Idle")],
ACK_IDLE:
[If(master_we,
@@ -1564,7 +1589,7 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1),
*increment_stat_master_rerun_counter,
NextState("Idle")
],
ACK_ERR: ## ### burst not handled
@@ -1584,8 +1609,8 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_error_counter, stat_master_error_counter + 1),
NextValue(sbus_master_error_virtual, sbus_master_last_virtual),
*increment_stat_master_error_counter,
*copy_sbus_master_last_virtual_to_error,
NextState("Idle")
],
"default": ## other ### burst not handled
@@ -1602,7 +1627,7 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_error_counter, stat_master_error_counter + 1),
*increment_stat_master_error_counter,
NextState("Idle")
],
})
@@ -1651,22 +1676,22 @@ class SBusFPGABus(Module):
[NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1),
*increment_stat_master_rerun_counter,
NextState("Idle")
],
ACK_ERR:
[NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_error_counter, stat_master_error_counter + 1),
NextValue(sbus_master_error_virtual, sbus_master_last_virtual),
*increment_stat_master_error_counter,
*copy_sbus_master_last_virtual_to_error,
NextState("Idle")
],
"default":
[NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_error_counter, stat_master_error_counter + 1),
*increment_stat_master_error_counter,
NextState("Idle")
],
}),
@@ -1685,7 +1710,7 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(sbus_master_throttle, sbus_default_master_throttle),
NextValue(stat_master_done_counter, stat_master_done_counter + 1),
*increment_stat_master_done_counter,
NextValue(master_src_retry, 0),
NextState("Idle")
)
@@ -1735,22 +1760,22 @@ class SBusFPGABus(Module):
[NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1),
*increment_stat_master_rerun_counter,
NextState("Idle")
],
ACK_ERR: ## ACK_ERRS or other
[NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_error_counter, stat_master_error_counter + 1),
NextValue(sbus_master_error_virtual, sbus_master_last_virtual),
*increment_stat_master_error_counter,
*copy_sbus_master_last_virtual_to_error,
NextState("Idle"),
],
"default": ## other
[NextValue(sbus_oe_data, 0),
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(stat_master_error_counter, stat_master_error_counter + 1),
*increment_stat_master_error_counter,
NextState("Idle"),
],
})
@@ -1761,7 +1786,7 @@ class SBusFPGABus(Module):
NextValue(sbus_oe_slave_in, 0),
NextValue(sbus_oe_master_in, 0),
NextValue(sbus_master_throttle, sbus_default_master_throttle),
NextValue(stat_master_done_counter, stat_master_done_counter + 1),
*increment_stat_master_done_counter,
NextValue(master_src_retry, 0),
NextState("Idle")
)
@@ -1982,55 +2007,56 @@ class SBusFPGABus(Module):
# )
#)
self.stat_cycle_counter = Signal(32)
self.buf_stat_cycle_counter = Signal(32)
self.buf_stat_slave_start_counter = Signal(32)
self.buf_stat_slave_done_counter = Signal(32)
self.buf_stat_slave_rerun_counter = Signal(32)
self.buf_stat_slave_early_error_counter = Signal(32)
self.buf_stat_master_start_counter = Signal(32)
self.buf_stat_master_done_counter = Signal(32)
self.buf_stat_master_error_counter = Signal(32)
self.buf_stat_master_rerun_counter = Signal(32)
self.buf_sbus_master_error_virtual = Signal(32)
self.stat_update = Signal()
stat_update_prev = Signal()
self.sync += stat_update_prev.eq(self.stat_update)
self.sync += self.stat_cycle_counter.eq(self.stat_cycle_counter + 1)
self.sync += If(~stat_update_prev & self.stat_update, ## raising edge: copy to buffer and reset active
self.buf_stat_cycle_counter.eq(self.stat_cycle_counter),
self.buf_stat_slave_start_counter.eq(stat_slave_start_counter),
self.buf_stat_slave_done_counter.eq(stat_slave_done_counter),
self.buf_stat_slave_rerun_counter.eq(stat_slave_rerun_counter),
self.buf_stat_slave_early_error_counter.eq(stat_slave_early_error_counter),
self.buf_stat_master_start_counter.eq(stat_master_start_counter),
self.buf_stat_master_done_counter.eq(stat_master_done_counter),
self.buf_stat_master_error_counter.eq(stat_master_error_counter),
self.buf_stat_master_rerun_counter.eq(stat_master_rerun_counter),
self.buf_sbus_master_error_virtual.eq(sbus_master_error_virtual),
self.stat_cycle_counter.eq(0),
stat_slave_start_counter.eq(0),
stat_slave_done_counter.eq(0),
stat_slave_rerun_counter.eq(0),
stat_slave_early_error_counter.eq(0),
stat_master_start_counter.eq(0),
stat_master_done_counter.eq(0),
stat_master_error_counter.eq(0),
stat_master_rerun_counter.eq(0),
sbus_master_error_virtual.eq(0),
)
self.sync += If(stat_update_prev & ~self.stat_update, ## falling edge: reset buffer
self.buf_stat_cycle_counter.eq(0),
self.buf_stat_slave_start_counter.eq(0),
self.buf_stat_slave_done_counter.eq(0),
self.buf_stat_slave_rerun_counter.eq(0),
self.buf_stat_slave_early_error_counter.eq(0),
self.buf_stat_master_start_counter.eq(0),
self.buf_stat_master_done_counter.eq(0),
self.buf_stat_master_error_counter.eq(0),
self.buf_stat_master_rerun_counter.eq(0),
self.buf_sbus_master_error_virtual.eq(0),
)
if (stat):
self.stat_cycle_counter = Signal(32)
self.buf_stat_cycle_counter = Signal(32)
self.buf_stat_slave_start_counter = Signal(32)
self.buf_stat_slave_done_counter = Signal(32)
self.buf_stat_slave_rerun_counter = Signal(32)
self.buf_stat_slave_early_error_counter = Signal(32)
self.buf_stat_master_start_counter = Signal(32)
self.buf_stat_master_done_counter = Signal(32)
self.buf_stat_master_error_counter = Signal(32)
self.buf_stat_master_rerun_counter = Signal(32)
self.buf_sbus_master_error_virtual = Signal(32)
self.stat_update = Signal()
stat_update_prev = Signal()
self.sync += stat_update_prev.eq(self.stat_update)
self.sync += self.stat_cycle_counter.eq(self.stat_cycle_counter + 1)
self.sync += If(~stat_update_prev & self.stat_update, ## raising edge: copy to buffer and reset active
self.buf_stat_cycle_counter.eq(self.stat_cycle_counter),
self.buf_stat_slave_start_counter.eq(stat_slave_start_counter),
self.buf_stat_slave_done_counter.eq(stat_slave_done_counter),
self.buf_stat_slave_rerun_counter.eq(stat_slave_rerun_counter),
self.buf_stat_slave_early_error_counter.eq(stat_slave_early_error_counter),
self.buf_stat_master_start_counter.eq(stat_master_start_counter),
self.buf_stat_master_done_counter.eq(stat_master_done_counter),
self.buf_stat_master_error_counter.eq(stat_master_error_counter),
self.buf_stat_master_rerun_counter.eq(stat_master_rerun_counter),
self.buf_sbus_master_error_virtual.eq(sbus_master_error_virtual),
self.stat_cycle_counter.eq(0),
stat_slave_start_counter.eq(0),
stat_slave_done_counter.eq(0),
stat_slave_rerun_counter.eq(0),
stat_slave_early_error_counter.eq(0),
stat_master_start_counter.eq(0),
stat_master_done_counter.eq(0),
stat_master_error_counter.eq(0),
stat_master_rerun_counter.eq(0),
sbus_master_error_virtual.eq(0),
)
self.sync += If(stat_update_prev & ~self.stat_update, ## falling edge: reset buffer
self.buf_stat_cycle_counter.eq(0),
self.buf_stat_slave_start_counter.eq(0),
self.buf_stat_slave_done_counter.eq(0),
self.buf_stat_slave_rerun_counter.eq(0),
self.buf_stat_slave_early_error_counter.eq(0),
self.buf_stat_master_start_counter.eq(0),
self.buf_stat_master_done_counter.eq(0),
self.buf_stat_master_error_counter.eq(0),
self.buf_stat_master_rerun_counter.eq(0),
self.buf_sbus_master_error_virtual.eq(0),
)

44
sbus-to-ztex-gateware-migen/sbus_to_fpga_prom.py
View File

@@ -102,6 +102,7 @@ def get_header_mapx_stuff(gname, names, sizes, types, doreg=True):
def get_prom(soc,
version,
sys_clk_freq,
stat=False,
trng=False,
usb=False,
sdram=True,
@@ -123,13 +124,13 @@ def get_prom(soc,
r += "\" RDOL,led\" device-name\n"
r += get_header_map_stuff("leds", "leds", 4)
r += ": setled! ( pattern -- )\nmap-in-leds\nleds-virt l! ( pattern virt -- )\nmap-out-leds\n;\n"
r += "finish-device\nnew-device\n"
r += "finish-device\nnew-device\n" # this assumes at least one device is active, which is true for sdram (we always have at least initialization)
r += "\" RDOL,sbusstat\" device-name\n"
r += get_header_map_stuff("sbus_bus_stat", "sbus_bus_stat", 256)
if (trng or usb or (sdram or not sdram) or engine or i2c or framebuffer or sdcard or (jareth and not goblin)):
r += "finish-device\nnew-device\n"
if (stat):
r += "\" RDOL,sbusstat\" device-name\n"
r += get_header_map_stuff("sbus_bus_stat", "sbus_bus_stat", 256)
if (trng or usb or (sdram or not sdram) or engine or i2c or framebuffer or sdcard or (jareth and not goblin)):
r += "finish-device\nnew-device\n"
if (trng):
r += "\" RDOL,neorv32trng\" device-name\n"
@@ -167,24 +168,25 @@ def get_prom(soc,
r += "\" RDOL,sdram\" device-name\n"
r += get_header_mapx_stuff("mregs", [ "ddrphy", "sdram", "exchange_with_mem" ], [ 4096, 4096, 4096 ], [ "csr", "csr", "csr" ])
r += "sbusfpga_irq_sdram encode-int \" interrupts\" property\n"
if (sys_clk_freq == 100e6):
r += "h# 19 constant m0_delay\n"
r += "h# 19 constant m1_delay\n"
r += "h# 1 constant m0_bitslip\n"
r += "h# 1 constant m1_bitslip\n"
elif (sys_clk_freq == 90e6):
r += "h# 1c constant m0_delay\n"
r += "h# 1c constant m1_delay\n"
r += "h# 1 constant m0_bitslip\n"
r += "h# 1 constant m1_bitslip\n"
else:
print("UNCALIBRATED FREQUENCY for SDRAM!")
assert(False)
r += "fload sdram_init.fth\ninit!\n"
else:
r += "\" RDOL,hidden_sdram\" device-name\n"
r += get_header_mapx_stuff("mregs", [ "ddrphy", "sdram" ], [ 4096, 4096 ], [ "csr", "csr" ])
r += "fload sdram_init.fth\ninit!\n"
if (sys_clk_freq == 100e6):
r += "h# 19 constant m0_delay\n"
r += "h# 19 constant m1_delay\n"
r += "h# 1 constant m0_bitslip\n"
r += "h# 1 constant m1_bitslip\n"
elif (sys_clk_freq == 90e6):
r += "h# 1c constant m0_delay\n"
r += "h# 1c constant m1_delay\n"
r += "h# 1 constant m0_bitslip\n"
r += "h# 1 constant m1_bitslip\n"
else:
print("UNCALIBRATED FREQUENCY for SDRAM!")
assert(False)
r += "fload sdram_init.fth\ninit!\n"
if (engine or i2c or framebuffer or sdcard or (jareth and not goblin)):
r += "finish-device\nnew-device\n"

21
sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
View File

@@ -210,10 +210,11 @@ class SBusFPGA(SoCCore):
#if self.irq.enabled:
#self.irq.add(name, use_loc_if_exists=True)
def __init__(self, variant, version, sys_clk_freq, trng, usb, sdram, engine, i2c, bw2, cg3, cg6, goblin, cg3_res, sdcard, jareth, **kwargs):
def __init__(self, variant, version, sys_clk_freq, trng, stat, usb, sdram, engine, i2c, bw2, cg3, cg6, goblin, cg3_res, sdcard, jareth, **kwargs):
framebuffer = (bw2 or cg3 or cg6 or goblin)
print(f"Building SBusFPGA for board version {version}")
print(f"Summary: variant={variant} sys_clk_freq={sys_clk_freq} trng={trng} stat={stat} usb={usb} sdram={sdram} engine={engine} i2c={i2c} bw2={bw2} cg3={cg3} cg6={cg6} goblin={goblin} (framebuffer={framebuffer}) fb_res={cg3_res} sdcard={sdcard} jareth={jareth}")
kwargs["cpu_type"] = "None"
kwargs["integrated_sram_size"] = 0
@@ -371,7 +372,7 @@ class SBusFPGA(SoCCore):
)
avail_sdram = self.bus.regions["main_ram"].size
###from sdram_init import DDR3FBInit
###self.submodules.sdram_init = DDR3FBInit(sys_clk_freq=sys_clk_freq, bitslip=1, delay=25)
###self.submodules.sdram_init = DDR3FBInit(sys_clk_freq=sys_clk_freq, bitslip=1, delay=25) # for 100 MHz sysclk
###self.bus.add_master(name="DDR3Init", master=self.sdram_init.bus)
base_fb = self.wb_mem_map["main_ram"] + avail_sdram - 1048576 # placeholder
@@ -458,6 +459,7 @@ class SBusFPGA(SoCCore):
_sbus_bus = SBusFPGABus(soc=self,
platform=self.platform,
stat=stat,
hold_reset=hold_reset,
wishbone_slave=wishbone_slave_sbus,
wishbone_master=self.wishbone_master_sbus,
@@ -470,7 +472,9 @@ class SBusFPGA(SoCCore):
cg3_base=base_fb)
#self.submodules.sbus_bus = _sbus_bus
self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus)
self.submodules.sbus_bus_stat = SBusFPGABusStat(soc = self, sbus_bus = self.sbus_bus)
if (stat):
self.submodules.sbus_bus_stat = SBusFPGABusStat(soc = self, sbus_bus = self.sbus_bus)
self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
@@ -525,7 +529,7 @@ class SBusFPGA(SoCCore):
self.submodules.cg6 = cg6_fb.cg6(soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga") # clock_domain for the VGA side, cg6 is running in cd_sys
self.bus.add_slave("cg6_bt", self.cg6.bus, SoCRegion(origin=self.mem_map.get("cg6_bt", None), size=0x1000, cached=False))
elif (goblin):
self.submodules.goblin = goblin_fb.goblin(soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga", irq_line=Signal()) # clock_domain for the VGA side, cg6 is running in cd_sys
self.submodules.goblin = goblin_fb.goblin(soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga", irq_line=Signal(), endian="big", hwcursor=True, truecolor=True) # clock_domain for the VGA side, goblin is running in cd_sys
self.bus.add_slave("goblin_bt", self.goblin.bus, SoCRegion(origin=self.mem_map.get("cg6_bt", None), size=0x1000, cached=False))
#pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
#SBUS_DATA_OE_LED_o = Signal()
@@ -578,18 +582,19 @@ def main():
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--variant", default="ztex2.13a", help="ZTex board variant (default ztex2.13a)")
parser.add_argument("--version", default="V1.2", help="SBusFPGA board version (default V1.2)")
parser.add_argument("--stat", action="store_true", help="device with some SBus FSM statistics for debug [all]")
parser.add_argument("--sys-clk-freq", default=100e6, help="SBusFPGA system clock (default 100e6 = 100 MHz)")
parser.add_argument("--trng", action="store_true", help="add true random number generator [all]")
parser.add_argument("--sdram", action="store_true", help="expose the sdram to the host [all]")
parser.add_argument("--usb", action="store_true", help="add a USB OHCI controller [V1.2]")
parser.add_argument("--engine", action="store_true", help="add a Engine crypto core [all]")
parser.add_argument("--i2c", action="store_true", help="add an I2C bus [none, placeholder]")
parser.add_argument("--i2c", action="store_true", help="add an I2C bus [V1.2+custom temp. pmod]")
parser.add_argument("--bw2", action="store_true", help="add a BW2 framebuffer [V1.2+VGA_RGB222 pmod]")
parser.add_argument("--cg3", action="store_true", help="add a CG3 framebuffer [V1.2+VGA_RGB222 pmod]")
parser.add_argument("--cg3-res", default="1152x900@76Hz", help="Specify the CG3/CG6 resolution")
parser.add_argument("--cg6", action="store_true", help="add a CG6 framebuffer [V1.2+VGA_RGB222 pmod]")
parser.add_argument("--goblin", action="store_true", help="add a Goblin framebuffer [V1.2+VGA_RGB222 pmod]")
parser.add_argument("--sdcard", action="store_true", help="add a sdcard {no SW yet}")
parser.add_argument("--sdcard", action="store_true", help="add a sdcard controller [all]")
parser.add_argument("--jareth", action="store_true", help="add a Jareth vector core [all]")
builder_args(parser)
vivado_build_args(parser)
@@ -616,11 +621,14 @@ def main():
if (fbcount > 1):
print(" ***** ERROR ***** : can't have more than one of BW2, CG3, CG6 and Goblin\n")
assert(False)
if ((fbcount > 0) and args.i2c):
print(" ***** ERROR ***** : Framebuffers and I2C are incompatible in V1.2\n")
soc = SBusFPGA(**soc_core_argdict(args),
variant=args.variant,
version=args.version,
sys_clk_freq=int(float(args.sys_clk_freq)),
stat=args.stat,
trng=args.trng,
sdram=args.sdram,
usb=args.usb,
@@ -671,6 +679,7 @@ def main():
write_to_file(os.path.join(f"prom_csr_{version_for_filename}.fth"), csr_forth_contents)
prom_content = sbus_to_fpga_prom.get_prom(soc=soc, version=args.version, sys_clk_freq=int(float(args.sys_clk_freq)),
stat=args.stat,
trng=args.trng,
usb=args.usb,
sdram=args.sdram,