github.com/rdolbeau.SBusFPGA
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named parameters for more compatibility

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This commit is contained in:
Romain Dolbeau
2022-10-09 12:09:03 +02:00
parent c8a8ddeedb
commit d133e95ca6
1 changed files with 3 additions and 3 deletions
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6
sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
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@@ -350,7 +350,7 @@ class SBusFPGA(SoCCore):
#prom_file = "SUNW,501-2325.bin" # real TGX
#prom_file = "SUNW,501-1415.bin" # real cg3
#prom_file = "SUNW,501-2253.bin" # real TGX+
prom_data = soc_core.get_mem_data(prom_file, "big")
prom_data = soc_core.get_mem_data(filename_or_regions=prom_file, endianness="big")
# prom = Array(prom_data)
#print("\n****************************************\n")
#for i in range(len(prom)):
@@ -548,7 +548,7 @@ class SBusFPGA(SoCCore):
self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus)
self.bus.add_master(name="cg6_accel_r5_d", master=self.cg6_accel.dbus)
cg6_rom_file = "blit_cg6.raw"
cg6_rom_data = soc_core.get_mem_data(cg6_rom_file, "little")
cg6_rom_data = soc_core.get_mem_data(filename_or_regions=cg6_rom_file, endianness="little")
cg6_rom_len = 4*len(cg6_rom_data);
rounded_cg6_rom_len = 2**log2_int(cg6_rom_len, False)
print(f"CG6 ROM is {cg6_rom_len} bytes, using {rounded_cg6_rom_len}")
@@ -562,7 +562,7 @@ class SBusFPGA(SoCCore):
self.bus.add_master(name="goblin_accel_r5_i", master=self.goblin_accel.ibus)
self.bus.add_master(name="goblin_accel_r5_d", master=self.goblin_accel.dbus)
goblin_rom_file = "blit_goblin.raw"
goblin_rom_data = soc_core.get_mem_data(goblin_rom_file, "little")
goblin_rom_data = soc_core.get_mem_data(filename_or_regions=goblin_rom_file, endianness="little")
goblin_rom_len = 4*len(goblin_rom_data);
rounded_goblin_rom_len = 2**log2_int(goblin_rom_len, False)
print(f"GOBLIN ROM is {goblin_rom_len} bytes, using {rounded_goblin_rom_len}")