deleted
This commit is contained in:
Romain Dolbeau
@@ -1,174 +0,0 @@
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import os
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import argparse
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from migen import *
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import litex
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from litex.build.generic_platform import *
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.integration.soc import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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from litex_boards.platforms import ztex213
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from migen.genlib.fifo import *
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from sbus_to_fpga_slave import *;
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from sbus_to_fpga_wishbone import *;
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_sbus_sbus = [
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("SBUS_3V3_CLK", 0, Pins("D15"), IOStandard("lvttl")),
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("SBUS_3V3_ASs", 0, Pins("T4"), IOStandard("lvttl")),
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("SBUS_3V3_BGs", 0, Pins("T6"), IOStandard("lvttl")),
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("SBUS_3V3_BRs", 0, Pins("R6"), IOStandard("lvttl")),
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("SBUS_3V3_ERRs", 0, Pins("V2"), IOStandard("lvttl")),
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("SBUS_DATA_OE_LED", 0, Pins("U1"), IOStandard("lvttl")),
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("SBUS_DATA_OE_LED_2", 0, Pins("T3"), IOStandard("lvttl")),
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("SBUS_3V3_RSTs", 0, Pins("U2"), IOStandard("lvttl")),
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("SBUS_3V3_SELs", 0, Pins("K6"), IOStandard("lvttl")),
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("SBUS_3V3_INT1s", 0, Pins("R3"), IOStandard("lvttl")),
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("SBUS_3V3_INT7s", 0, Pins("N5"), IOStandard("lvttl")),
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("SBUS_3V3_PPRD", 0, Pins("N6"), IOStandard("lvttl")),
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("SBUS_OE", 0, Pins("P5"), IOStandard("lvttl")),
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("SBUS_3V3_ACKs", 0, Pins("M6 L6 N4"), IOStandard("lvttl")),
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("SBUS_3V3_SIZ", 0, Pins("R7 U3 V1"), IOStandard("lvttl")),
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("SBUS_3V3_D", 0, Pins("J18 K16 J17 K15 K13 J15 J13 J14 H14 H17 G14 G17 G16 G18 H16 F18 F16 E18 F15 D18 E17 G13 D17 F13 F14 E16 E15 C17 C16 A18 B18 C15"), IOStandard("lvttl")),
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("SBUS_3V3_PA", 0, Pins("B16 B17 D14 C14 D12 A16 A15 B14 B13 B12 C12 A14 A13 B11 A11 M4 R2 M3 P2 M2 N2 K5 N1 L4 M1 L3 L1 K3"), IOStandard("lvttl")),
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]
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_native = ClockDomain(reset_less=True)
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self.clock_domains.cd_sbus = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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# # #
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clk48 = platform.request("clk48")
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self.cd_native.clk = clk48
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clk_sbus = platform.request("SBUS_3V3_CLK")
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self.cd_sbus.clk = clk_sbus
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rst_sbus = platform.request("SBUS_3V3_RSTs")
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self.comb += self.cd_sbus.rst.eq(~rst_sbus)
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_native.clk, self.cd_sbus.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, self.cd_sbus.clk)
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platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_native.clk)
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platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_sys.clk)
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# Power on reset, reset propagate from SBus to SYS
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.comb += pll.reset.eq(~por_done | ~rst_sbus)
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class SBusFPGA(SoCCore):
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def __init__(self, **kwargs):
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kwargs["cpu_type"] = "None"
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kwargs["integrated_sram_size"] = 0
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kwargs["with_uart"] = True
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kwargs["with_timer"] = False
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self.sys_clk_freq = sys_clk_freq = 100e6
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self.platform = platform = ztex213.Platform(variant="ztex2.13a", expansion="sbus")
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self.platform.add_extension(_sbus_sbus)
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SoCCore.__init__(self, platform=platform, sys_clk_freq=sys_clk_freq, clk_freq=sys_clk_freq, **kwargs)
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wb_mem_map = {
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"prom": 0x00000000,
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"csr" : 0x00040000,
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}
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self.mem_map.update(wb_mem_map)
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self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq)
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self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6) # SBus max
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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prom_file = "prom_mini.fc"
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prom_data = soc_core.get_mem_data(prom_file, "big")
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prom = Array(prom_data)
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#print("\n****************************************\n")
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#for i in range(len(prom)):
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# print(hex(prom[i]))
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#print("\n****************************************\n")
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self.add_ram("prom", origin=self.mem_map["prom"], size=2**16, contents=prom_data, mode="r") # for show
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#getattr(self,"prom").mem.init = prom_data
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#getattr(self,"prom").mem.depth = 2**14
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# don't enable anything on the SBus side for 20 seconds after power up
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# this avoids FPGA initialization messing with the cold boot process
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# requires us to reset the SPARCstation afterward so the FPGA board
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# is properly identified
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# This is in the 'native' ClockDomain that is never reset
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hold_reset_ctr = Signal(30, reset=960000000)
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self.sync.native += If(hold_reset_ctr>0, hold_reset_ctr.eq(hold_reset_ctr - 1))
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hold_reset = Signal(reset=1)
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self.comb += hold_reset.eq(~(hold_reset_ctr == 0))
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sbus_to_wishbone_wr_fifo = AsyncFIFOBuffered(width=32+30, depth=16)
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sbus_to_wishbone_wr_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(sbus_to_wishbone_wr_fifo)
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self.submodules += sbus_to_wishbone_wr_fifo
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sbus_to_wishbone_rd_fifo_addr = AsyncFIFOBuffered(width=30, depth=16)
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sbus_to_wishbone_rd_fifo_addr = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(sbus_to_wishbone_rd_fifo_addr)
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self.submodules += sbus_to_wishbone_rd_fifo_addr
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sbus_to_wishbone_rd_fifo_data = AsyncFIFOBuffered(width=32, depth=16)
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sbus_to_wishbone_rd_fifo_data = ClockDomainsRenamer({"write": "sys", "read": "sbus"})(sbus_to_wishbone_rd_fifo_data)
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self.submodules += sbus_to_wishbone_rd_fifo_data
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self.submodules.sbus_to_wishbone = SBusToWishbone(wr_fifo=sbus_to_wishbone_wr_fifo,
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rd_fifo_addr=sbus_to_wishbone_rd_fifo_addr,
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rd_fifo_data=sbus_to_wishbone_rd_fifo_data,
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wishbone=wishbone.Interface(data_width=self.bus.data_width))
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_sbus_slave = SBusFPGASlave(platform=self.platform,
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prom=prom,
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hold_reset=hold_reset,
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wr_fifo=sbus_to_wishbone_wr_fifo,
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rd_fifo_addr=sbus_to_wishbone_rd_fifo_addr,
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rd_fifo_data=sbus_to_wishbone_rd_fifo_data,)
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self.submodules.sbus_slave = ClockDomainsRenamer("sbus")(_sbus_slave)
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self.bus.add_master(name="SBusBridgeToWishbone", master=self.sbus_to_wishbone.wishbone)
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# self.soc = Module()
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# self.soc.mem_regions = self.mem_regions = {}
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# region = litex.soc.integration.soc.SoCRegion(origin=0x0, size=0x0)
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# region.length = 0
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# self.mem_regions['csr'] = region
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# self.soc.constants = self.constants = {}
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# self.soc.csr_regions = self.csr_regions = {}
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# self.soc.cpu_type = self.cpu_type = None
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# def do_finalize(self):
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# self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6)
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def main():
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parser = argparse.ArgumentParser(description="SbusFPGA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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builder_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = SBusFPGA(**soc_core_argdict(args))
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#soc.add_uart(name="uart", baudrate=115200, fifo_depth=16)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if __name__ == "__main__":
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main()
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@@ -1,501 +0,0 @@
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from migen import *
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from migen.fhdl.specials import Tristate
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SIZ_WORD = 0x0
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SIZ_BYTE = 0x1
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SIZ_HWORD = 0x2
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SIZ_EXT = 0x3
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SIZ_BURST4 = 0x4
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SIZ_BURST8 = 0x5
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SIZ_BURST16 = 0x6
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SIZ_BURST2 = 0x7
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ACK_IDLE = 0x7
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ACK_ERR = 0x6
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ACK_BYTE = 0x5
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ACK_RERUN = 0x4
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ACK_WORD = 0x3
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ACK_DWORD = 0x2
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ACK_HWORD = 0x1
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ACK_RECV = 0x0
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ADDR_PHYS_HIGH = 27
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ADDR_PHYS_LOW = 0
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ADDR_PFX_HIGH = ADDR_PHYS_HIGH
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ADDR_PFX_LOW = 16 ## 64 KiB per prefix
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ADDR_PFX_LENGTH = 12 #(1 + ADDR_PFX_HIGH - ADDR_PFX_LOW)
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ROM_ADDR_PFX = Signal(12, reset = 0)
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WISHBONE_CSR_ADDR_PFX = Signal(12, reset = 4)
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def siz_is_word(siz):
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return (SIZ_WORD == siz) | (SIZ_BURST2 == siz) | (SIZ_BURST4 == siz) | (SIZ_BURST8 == siz) | (SIZ_BURST16 == siz)
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# FIXME: this doesn't work. Verilog aways use value[0:4]
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#def _index_with_wrap(counter, limit_m1, value):
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# if (limit_m1 == 0):
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# return value[0:4]
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# elif (limit_m1 == 1):
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# return Cat((value + counter)[0:1], value[1:4])
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# elif (limit_m1 == 3):
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# return Cat((value + counter)[0:2], value[2:4])
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# elif (limit_m1 == 7):
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# return Cat((value + counter)[0:3], value[3:4])
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# elif (limit_m1 == 15):
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# return (value + counter)[0:4]
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# return value[0:4]
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def index_with_wrap(counter, limit_m1, value):
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return ((value+counter) & limit_m1)[0:4] | (value&(~limit_m1))[0:4]
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# FIXME: this doesn't work. Verilog aways use 1
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def siz_to_burst_size_m1(siz):
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if (SIZ_WORD == siz):
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return 0
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elif (SIZ_BURST2 == siz):
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return 1
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elif (SIZ_BURST4 == siz):
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return 3
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elif (SIZ_BURST8 == siz):
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return 7
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elif (SIZ_BURST16 == siz):
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return 15
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return 1
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class LedDisplay(Module):
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def __init__(self, pads):
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n = len(pads)
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self.value = Signal(32, reset = 0x18244281)
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old_value = Signal(32)
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display = Signal(8)
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self.submodules.fsm = fsm = FSM(reset_state="Reset")
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time_counter = Signal(32, reset = 0)
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blink_counter = Signal(4, reset = 0)
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self.comb += pads.eq(display)
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fsm.act("Reset",
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NextValue(time_counter, 25000000//10),
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NextValue(blink_counter, 10),
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NextValue(display, 0x00),
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NextValue(old_value, self.value),
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NextState("Quick"))
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fsm.act("Quick",
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If (old_value != self.value,
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NextState("Reset")
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).Elif(time_counter == 0,
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If (blink_counter == 0,
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NextValue(time_counter, 25000000//2),
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NextValue(display, self.value[0:8]),
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NextState("Byte0")
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).Else(
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NextValue(display, ~display),
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NextValue(time_counter, 25000000//10),
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NextValue(blink_counter, blink_counter - 1)
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)
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).Else(
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NextValue(time_counter, time_counter - 1)
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)
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)
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fsm.act("Byte0",
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If (old_value != self.value,
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NextState("Reset")
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).Elif(time_counter == 0,
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NextValue(time_counter, 25000000//2),
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NextValue(display, self.value[8:16]),
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NextState("Byte1")
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).Else(
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NextValue(time_counter, time_counter - 1)
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)
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)
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fsm.act("Byte1",
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If (old_value != self.value,
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NextState("Reset")
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).Elif(time_counter == 0,
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NextValue(time_counter, 25000000//2),
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NextValue(display, self.value[16:24]),
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NextState("Byte2")
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).Else(
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NextValue(time_counter, time_counter - 1)
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)
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)
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fsm.act("Byte2",
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If (old_value != self.value,
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NextState("Reset")
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).Elif(time_counter == 0,
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NextValue(time_counter, 25000000//2),
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NextValue(display, self.value[24:32]),
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NextState("Byte3")
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).Else(
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NextValue(time_counter, time_counter - 1)
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)
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)
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fsm.act("Byte3",
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If (old_value != self.value,
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NextState("Reset")
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).Elif(time_counter == 0,
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NextValue(time_counter, 25000000//10),
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NextValue(blink_counter, 10),
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NextValue(display, 0x00),
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NextState("Quick")
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).Else(
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NextValue(time_counter, time_counter - 1)
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)
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)
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class SBusFPGASlave(Module):
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def __init__(self, platform, prom, hold_reset, wr_fifo, rd_fifo_addr, rd_fifo_data):
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self.platform = platform
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self.hold_reset = hold_reset
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self.wr_fifo = wr_fifo
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self.rd_fifo_addr = rd_fifo_addr
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self.rd_fifo_data = rd_fifo_data
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#self.submodules.led_display = LedDisplay(pads=platform.request_all("user_led"))
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#pad_SBUS_3V3_CLK = platform.request("SBUS_3V3_CLK")
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pad_SBUS_3V3_ASs = platform.request("SBUS_3V3_ASs")
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pad_SBUS_3V3_BGs = platform.request("SBUS_3V3_BGs")
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pad_SBUS_3V3_BRs = platform.request("SBUS_3V3_BRs")
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pad_SBUS_3V3_ERRs = platform.request("SBUS_3V3_ERRs")
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pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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pad_SBUS_DATA_OE_LED_2 = platform.request("SBUS_DATA_OE_LED_2")
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#pad_SBUS_3V3_RSTs = platform.request("SBUS_3V3_RSTs")
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pad_SBUS_3V3_SELs = platform.request("SBUS_3V3_SELs")
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pad_SBUS_3V3_INT1s = platform.request("SBUS_3V3_INT1s")
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pad_SBUS_3V3_INT7s = platform.request("SBUS_3V3_INT7s")
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pad_SBUS_3V3_PPRD = platform.request("SBUS_3V3_PPRD")
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pad_SBUS_OE = platform.request("SBUS_OE")
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pad_SBUS_3V3_ACKs = platform.request("SBUS_3V3_ACKs")
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pad_SBUS_3V3_SIZ = platform.request("SBUS_3V3_SIZ")
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pad_SBUS_3V3_D = platform.request("SBUS_3V3_D")
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pad_SBUS_3V3_PA = platform.request("SBUS_3V3_PA")
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assert len(pad_SBUS_3V3_D) == 32, "len(pad_SBUS_3V3_D) should be 32"
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assert len(pad_SBUS_3V3_PA) == 28, "len(pad_SBUS_3V3_PA) should be 28"
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#leds = Signal(8, reset=0xF0)
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#self.comb += platform.request("user_led", 0).eq(leds[0])
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#self.comb += platform.request("user_led", 1).eq(leds[1])
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#self.comb += platform.request("user_led", 2).eq(leds[2])
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#self.comb += platform.request("user_led", 3).eq(leds[3])
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#self.comb += platform.request("user_led", 4).eq(leds[4])
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#self.comb += platform.request("user_led", 5).eq(leds[5])
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#self.comb += platform.request("user_led", 6).eq(leds[6])
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#self.comb += platform.request("user_led", 7).eq(leds[7])
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sbus_oe_data = Signal(reset=0)
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sbus_oe_slave_in = Signal(reset=0)
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sbus_oe_master_in = Signal(reset=0)
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sbus_oe_int1 = Signal(reset=0)
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sbus_oe_int7 = Signal(reset=0)
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sbus_oe_master_br = Signal(reset=0)
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sbus_last_pa = Signal(28)
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burst_index = Signal(4)
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burst_counter = Signal(4)
|
||||
burst_limit_m1 = Signal(4)
|
||||
|
||||
#SBUS_3V3_CLK = Signal()
|
||||
SBUS_3V3_ASs_i = Signal()
|
||||
self.comb += SBUS_3V3_ASs_i.eq(pad_SBUS_3V3_ASs)
|
||||
SBUS_3V3_BGs_i = Signal()
|
||||
self.comb += SBUS_3V3_BGs_i.eq(pad_SBUS_3V3_BGs)
|
||||
SBUS_3V3_BRs_o = Signal(reset=1)
|
||||
self.specials += Tristate(pad_SBUS_3V3_BRs, SBUS_3V3_BRs_o, sbus_oe_master_br, None)
|
||||
SBUS_3V3_ERRs_i = Signal()
|
||||
SBUS_3V3_ERRs_o = Signal()
|
||||
self.specials += Tristate(pad_SBUS_3V3_ERRs, SBUS_3V3_ERRs_o, sbus_oe_master_in, SBUS_3V3_ERRs_i)
|
||||
SBUS_DATA_OE_LED_o = Signal()
|
||||
self.comb += pad_SBUS_DATA_OE_LED.eq(SBUS_DATA_OE_LED_o)
|
||||
SBUS_DATA_OE_LED_2_o = Signal()
|
||||
self.comb += pad_SBUS_DATA_OE_LED_2.eq(SBUS_DATA_OE_LED_2_o)
|
||||
#SBUS_3V3_RSTs = Signal()
|
||||
SBUS_3V3_SELs_i = Signal()
|
||||
self.comb += SBUS_3V3_SELs_i.eq(pad_SBUS_3V3_SELs)
|
||||
SBUS_3V3_INT1s_o = Signal(reset=1)
|
||||
self.specials += Tristate(pad_SBUS_3V3_INT1s, SBUS_3V3_INT1s_o, sbus_oe_int1, None)
|
||||
SBUS_3V3_INT7s_o = Signal(reset=1)
|
||||
self.specials += Tristate(pad_SBUS_3V3_INT7s, SBUS_3V3_INT7s_o, sbus_oe_int7, None)
|
||||
SBUS_3V3_PPRD_i = Signal()
|
||||
SBUS_3V3_PPRD_o = Signal()
|
||||
self.specials += Tristate(pad_SBUS_3V3_PPRD, SBUS_3V3_PPRD_o, sbus_oe_slave_in, SBUS_3V3_PPRD_i)
|
||||
#SBUS_OE_o = Signal()
|
||||
self.comb += pad_SBUS_OE.eq(self.hold_reset)
|
||||
SBUS_3V3_ACKs_i = Signal(3)
|
||||
SBUS_3V3_ACKs_o = Signal(3)
|
||||
self.specials += Tristate(pad_SBUS_3V3_ACKs, SBUS_3V3_ACKs_o, sbus_oe_master_in, SBUS_3V3_ACKs_i)
|
||||
SBUS_3V3_SIZ_i = Signal(3)
|
||||
SBUS_3V3_SIZ_o = Signal(3)
|
||||
self.specials += Tristate(pad_SBUS_3V3_SIZ, SBUS_3V3_SIZ_o, sbus_oe_slave_in, SBUS_3V3_SIZ_i)
|
||||
SBUS_3V3_D_i = Signal(32)
|
||||
SBUS_3V3_D_o = Signal(32)
|
||||
self.specials += Tristate(pad_SBUS_3V3_D, SBUS_3V3_D_o, sbus_oe_data, SBUS_3V3_D_i)
|
||||
SBUS_3V3_PA_i = Signal(28)
|
||||
self.comb += SBUS_3V3_PA_i.eq(pad_SBUS_3V3_PA)
|
||||
|
||||
p_data = Signal(32) # data to read/write
|
||||
|
||||
data_read_addr = Signal(30) # first addr of req. when reading from WB
|
||||
data_read_enable = Signal() # start enqueuing req. to read from WB
|
||||
|
||||
self.submodules.slave_fsm = slave_fsm = FSM(reset_state="Reset")
|
||||
|
||||
slave_fsm.act("Reset",
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 0),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 0),
|
||||
NextValue(sbus_oe_int1, 0),
|
||||
NextValue(sbus_oe_int7, 0),
|
||||
NextValue(sbus_oe_data, 0),
|
||||
NextValue(sbus_oe_slave_in, 0),
|
||||
NextValue(sbus_oe_master_in, 0),
|
||||
NextValue(sbus_oe_master_br, 0),
|
||||
NextValue(p_data, 0),
|
||||
#NextValue(leds, 0x0F),
|
||||
NextState("Start")
|
||||
)
|
||||
slave_fsm.act("Start",
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 0),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 0),
|
||||
NextValue(sbus_oe_int1, 0),
|
||||
NextValue(sbus_oe_int7, 0),
|
||||
NextValue(sbus_oe_data, 0),
|
||||
NextValue(sbus_oe_slave_in, 0),
|
||||
NextValue(sbus_oe_master_in, 0),
|
||||
NextValue(sbus_oe_master_br, 0),
|
||||
NextValue(p_data, 0),
|
||||
#NextValue(leds, 0x01),
|
||||
If((self.hold_reset == 0), NextState("Idle"))
|
||||
)
|
||||
slave_fsm.act("Idle",
|
||||
#NextValue(leds, 0x11),
|
||||
If(((SBUS_3V3_SELs_i == 0) &
|
||||
(SBUS_3V3_ASs_i == 0) &
|
||||
(siz_is_word(SBUS_3V3_SIZ_i)) &
|
||||
(SBUS_3V3_PPRD_i == 1) &
|
||||
(SBUS_3V3_PA_i[0:2] == 0)),
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 1),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 0),
|
||||
NextValue(sbus_oe_master_in, 1),
|
||||
NextValue(sbus_last_pa, SBUS_3V3_PA_i),
|
||||
NextValue(burst_counter, 0),
|
||||
Case(SBUS_3V3_SIZ_i, {
|
||||
SIZ_WORD: NextValue(burst_limit_m1, 0),
|
||||
SIZ_BURST2: NextValue(burst_limit_m1, 1),
|
||||
SIZ_BURST4: NextValue(burst_limit_m1, 3),
|
||||
SIZ_BURST8: NextValue(burst_limit_m1, 7),
|
||||
SIZ_BURST16: NextValue(burst_limit_m1, 15)}),
|
||||
If((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(p_data, prom[SBUS_3V3_PA_i[ADDR_PHYS_LOW+2:ADDR_PFX_LOW]]),
|
||||
NextValue(SBUS_DATA_OE_LED_o, 1),
|
||||
NextState("Slave_Ack_Read_Prom_Burst")
|
||||
).Elif((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(p_data, 0xDEADBEEF),
|
||||
NextValue(data_read_addr, (Cat(SBUS_3V3_PA_i[2:], Signal(4, reset=0)))), # enqueue all the request to the wishbone
|
||||
NextValue(data_read_enable, 1), # enqueue all the request to the wishbone
|
||||
NextValue(SBUS_DATA_OE_LED_2_o, 1),
|
||||
NextState("Slave_Ack_Read_Reg_Burst_Wait_For_Data")
|
||||
).Else(
|
||||
#NextValue(self.led_display.value, Cat(SBUS_3V3_PA_i, Signal(2, reset = 1), SBUS_3V3_PA_i[1:2], SBUS_3V3_PPRD_i)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextState("Slave_Error")
|
||||
)
|
||||
).Elif(((SBUS_3V3_SELs_i == 0) &
|
||||
(SBUS_3V3_ASs_i == 0) &
|
||||
(SIZ_BYTE == SBUS_3V3_SIZ_i) &
|
||||
(SBUS_3V3_PPRD_i == 1)),
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 0),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 1),
|
||||
NextValue(sbus_oe_master_in, 1),
|
||||
NextValue(sbus_last_pa, SBUS_3V3_PA_i),
|
||||
If((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_BYTE),
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextValue(p_data, prom[SBUS_3V3_PA_i[ADDR_PHYS_LOW+2:ADDR_PFX_LOW]]),
|
||||
NextState("Slave_Ack_Read_Prom_Byte")
|
||||
).Else(
|
||||
#NextValue(self.led_display.value, Cat(SBUS_3V3_PA_i, Signal(2, reset = 2), SBUS_3V3_PA_i[1:2], SBUS_3V3_PPRD_i)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextState("Slave_Error")
|
||||
)
|
||||
).Elif(((SBUS_3V3_SELs_i == 0) &
|
||||
(SBUS_3V3_ASs_i == 0) &
|
||||
(siz_is_word(SBUS_3V3_SIZ_i)) &
|
||||
(SBUS_3V3_PPRD_i == 0) &
|
||||
(SBUS_3V3_PA_i[0:2] == 0) &
|
||||
(self.wr_fifo.writable)), # maybe we should check for enough space? not that we'll encounter write burst...
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 1),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 1),
|
||||
NextValue(sbus_oe_master_in, 1),
|
||||
NextValue(sbus_last_pa, SBUS_3V3_PA_i),
|
||||
NextValue(burst_counter, 0),
|
||||
Case(SBUS_3V3_SIZ_i, {
|
||||
SIZ_WORD: NextValue(burst_limit_m1, 0),
|
||||
SIZ_BURST2: NextValue(burst_limit_m1, 1),
|
||||
SIZ_BURST4: NextValue(burst_limit_m1, 3),
|
||||
SIZ_BURST8: NextValue(burst_limit_m1, 7),
|
||||
SIZ_BURST16: NextValue(burst_limit_m1, 15)}),
|
||||
If((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextState("Slave_Ack_Reg_Write_Burst")
|
||||
).Else(
|
||||
#NextValue(self.led_display.value, Cat(SBUS_3V3_PA_i, Signal(2, reset = 3), SBUS_3V3_PA_i[1:2], SBUS_3V3_PPRD_i)),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_ERR),
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
NextState("Slave_Error")
|
||||
)
|
||||
)
|
||||
)
|
||||
# ##### READ #####
|
||||
slave_fsm.act("Slave_Ack_Read_Prom_Burst",
|
||||
#NextValue(leds, 0x03),
|
||||
NextValue(sbus_oe_data, 1),
|
||||
NextValue(SBUS_3V3_D_o, p_data),
|
||||
#NextValue(burst_index, index_with_wrap((burst_counter+1), burst_limit_m1, sbus_last_pa[ADDR_PHYS_LOW+2:ADDR_PHYS_LOW+6])),
|
||||
NextValue(p_data, prom[Cat(index_with_wrap((burst_counter+1), burst_limit_m1, sbus_last_pa[ADDR_PHYS_LOW+2:ADDR_PHYS_LOW+6]), sbus_last_pa[ADDR_PHYS_LOW+6:ADDR_PFX_LOW])]),
|
||||
If((burst_counter == burst_limit_m1),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE),
|
||||
NextState("Slave_Do_Read")
|
||||
).Else(
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
|
||||
NextValue(burst_counter, burst_counter + 1)
|
||||
)
|
||||
)
|
||||
slave_fsm.act("Slave_Ack_Read_Prom_Byte",
|
||||
#NextValue(leds, 0x0c),
|
||||
NextValue(sbus_oe_data, 1),
|
||||
#NextValue(self.led_display.value, sbus_last_pa[0:2]),
|
||||
If((sbus_last_pa[0:2] == 0x0),
|
||||
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[24:32]))
|
||||
).Elif((sbus_last_pa[0:2] == 0x1),
|
||||
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[16:24]))
|
||||
).Elif((sbus_last_pa[0:2] == 0x2),
|
||||
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[ 8:16]))
|
||||
).Elif((sbus_last_pa[0:2] == 0x3),
|
||||
NextValue(SBUS_3V3_D_o, Cat(Signal(24), p_data[ 0: 8]))
|
||||
),
|
||||
NextState("Slave_Do_Read")
|
||||
)
|
||||
slave_fsm.act("Slave_Do_Read",
|
||||
#NextValue(leds, 0x30),
|
||||
NextValue(sbus_oe_int1, 0),
|
||||
NextValue(sbus_oe_int7, 0),
|
||||
NextValue(sbus_oe_data, 0),
|
||||
NextValue(sbus_oe_slave_in, 0),
|
||||
NextValue(sbus_oe_master_in, 0),
|
||||
NextValue(sbus_oe_master_br, 0),
|
||||
If((SBUS_3V3_ASs_i == 1),
|
||||
NextState("Idle")
|
||||
)
|
||||
)
|
||||
slave_fsm.act("Slave_Ack_Read_Reg_Burst",
|
||||
NextValue(sbus_oe_data, 1),
|
||||
NextValue(SBUS_3V3_D_o, p_data),
|
||||
If((burst_counter == burst_limit_m1),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE),
|
||||
NextState("Slave_Do_Read")
|
||||
).Else(
|
||||
NextValue(burst_counter, burst_counter + 1),
|
||||
If(rd_fifo_data.readable,
|
||||
NextValue(p_data, rd_fifo_data.dout),
|
||||
rd_fifo_data.re.eq(1),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_WORD)
|
||||
).Else(
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE),
|
||||
NextState("Slave_Ack_Read_Reg_Burst_Wait_For_Data")
|
||||
)
|
||||
)
|
||||
)
|
||||
slave_fsm.act("Slave_Ack_Read_Reg_Burst_Wait_For_Data",
|
||||
If(rd_fifo_data.readable,
|
||||
NextValue(p_data, rd_fifo_data.dout),
|
||||
rd_fifo_data.re.eq(1),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
|
||||
NextState("Slave_Ack_Read_Reg_Burst")
|
||||
)
|
||||
)
|
||||
# ##### WRITE #####
|
||||
slave_fsm.act("Slave_Ack_Reg_Write_Burst",
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 1),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 1),
|
||||
#NextValue(leds, 0x03),
|
||||
#NextValue(burst_index, index_with_wrap((burst_counter+1), burst_limit_m1, sbus_last_pa[ADDR_PHYS_LOW+2:ADDR_PHYS_LOW+6])),
|
||||
#NextValue(csr_data_w_addr, Cat(Signal(2, reset = 0),
|
||||
# index_with_wrap(burst_counter, burst_limit_m1, sbus_last_pa[ADDR_PHYS_LOW+2:ADDR_PHYS_LOW+6]),
|
||||
# sbus_last_pa[ADDR_PHYS_LOW+6:ADDR_PFX_LOW],
|
||||
# WISHBONE_CSR_ADDR_PFX)),
|
||||
#NextValue(csr_data_w_data, SBUS_3V3_D_i),
|
||||
#NextValue(csr_data_w_addr, 0x00040000),
|
||||
#NextValue(csr_data_w_we, 1),
|
||||
self.wr_fifo.din.eq(Cat(index_with_wrap(burst_counter, burst_limit_m1, sbus_last_pa[ADDR_PHYS_LOW+2:ADDR_PHYS_LOW+6]), # 4 bits, adr FIXME
|
||||
sbus_last_pa[ADDR_PHYS_LOW+6:ADDR_PFX_LOW], # 10 bits, adr
|
||||
WISHBONE_CSR_ADDR_PFX, # 12 bits, adr
|
||||
Signal(4, reset = 0), # 4 bits, adr (could be removed)
|
||||
SBUS_3V3_D_i)), # 32 bits, data
|
||||
self.wr_fifo.we.eq(1),
|
||||
If((burst_counter == burst_limit_m1),
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_IDLE),
|
||||
NextState("Slave_Ack_Reg_Write_Final")
|
||||
).Else(
|
||||
NextValue(SBUS_3V3_ACKs_o, ACK_WORD),
|
||||
NextValue(burst_counter, burst_counter + 1)
|
||||
)
|
||||
)
|
||||
slave_fsm.act("Slave_Ack_Reg_Write_Final",
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 1),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 0),
|
||||
NextValue(sbus_oe_int1, 0),
|
||||
NextValue(sbus_oe_int7, 0),
|
||||
NextValue(sbus_oe_data, 0),
|
||||
NextValue(sbus_oe_slave_in, 0),
|
||||
NextValue(sbus_oe_master_in, 0),
|
||||
NextValue(sbus_oe_master_br, 0),
|
||||
If((SBUS_3V3_ASs_i == 1),
|
||||
NextState("Idle")
|
||||
)
|
||||
)
|
||||
# ##### ERROR #####
|
||||
slave_fsm.act("Slave_Error",
|
||||
#NextValue(leds, 0xc0),
|
||||
#NextValue(SBUS_DATA_OE_LED_o, 1),
|
||||
#NextValue(SBUS_DATA_OE_LED_2_o, 1),
|
||||
NextValue(sbus_oe_int1, 0),
|
||||
NextValue(sbus_oe_int7, 0),
|
||||
NextValue(sbus_oe_data, 0),
|
||||
NextValue(sbus_oe_slave_in, 0),
|
||||
NextValue(sbus_oe_master_in, 0),
|
||||
NextValue(sbus_oe_master_br, 0),
|
||||
If((SBUS_3V3_ASs_i == 1),
|
||||
NextState("Idle")
|
||||
)
|
||||
)
|
||||
|
||||
self.submodules.request_fsm = request_fsm = FSM(reset_state="Reset")
|
||||
request_fsm.act("Reset",
|
||||
NextState("Idle")
|
||||
)
|
||||
request_fsm.act("Idle",
|
||||
If(data_read_enable,
|
||||
NextValue(data_read_enable, 0),
|
||||
self.rd_fifo_addr.we.eq(1),
|
||||
self.rd_fifo_addr.din.eq(data_read_addr),
|
||||
If (burst_limit_m1 != burst_counter, # 0 the first time
|
||||
NextValue(burst_counter, burst_counter + 1),
|
||||
NextState("Queue")
|
||||
)
|
||||
)
|
||||
)
|
||||
request_fsm.act("Queue",
|
||||
self.rd_fifo_addr.we.eq(1),
|
||||
self.rd_fifo_addr.din.eq(Cat(index_with_wrap(burst_counter, burst_limit_m1, data_read_addr[0:4]), data_read_addr[4:])),
|
||||
If (burst_limit_m1 != burst_counter,
|
||||
NextValue(burst_counter, burst_counter + 1),
|
||||
).Else(
|
||||
NextState("Idle")
|
||||
)
|
||||
)
|
||||
Reference in New Issue
Block a user