details

sbus-to-ztex/pmod.sch

@@ -13,8 +13,6 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
-Text Notes 7300 2850 0    50   ~ 0
-Dual-row "extended" Pmod\nExternal, in line w/ the carrier
 Text GLabel 7150 3500 0    50   Input ~ 0
 PMOD-56-
 Text GLabel 7150 3600 0    50   Input ~ 0

sbus-to-ztex/sbus-to-ztex-all-pos-jlcpcb.csv

@@ -7,7 +7,7 @@ Designator,"Mid X" ,"Mid Y",Layer,Rotation
 "C5",48.995980 ,-80.067460,Top,90.000000
 "C6",62.995980 ,-80.359960,Top,90.000000
 "C8",30.495980 ,-43.197460,Top,0.000000
-"C9",79.745980 ,-5.487460,Top,270.000000
+"C9",77.495980 ,-5.487460,Top,270.000000
 "C10",70.995980 ,-19.247460,Top,180.000000
 "C11",70.995980 ,-39.247460,Top,180.000000
 "C12",70.995980 ,-59.247460,Top,180.000000
@@ -22,13 +22,13 @@ Designator,"Mid X" ,"Mid Y",Layer,Rotation
 "C21",3.295980 ,-37.747460,Top,0.000000
 "C22",37.495980 ,-70.972460,Top,180.000000
 "C24",52.745980 ,-45.737460,Top,180.000000
-"C25",12.930980 ,-35.902460,Top,270.000000
+"C25",17.090980 ,-33.037460,Top,180.000000
 "C26",15.180980 ,-35.902460,Top,270.000000
 "C27",75.495980 ,-78.947460,Top,180.000000
 "C31",83.495980 ,-47.997460,Top,0.000000
 "FB1",38.995980 ,-80.547460,Top,180.000000
-"GRAPHIC1",42.465980 ,-22.787460,Top,90.000000
-"GRAPHIC2",41.415980 ,-53.717460,Top,90.000000
+"GRAPHIC1",42.505980 ,-22.927460,Top,90.000000
+"GRAPHIC2",47.615980 ,-58.627460,Top,90.000000
 "J1",12.495980 ,-14.997460,Top,0.000000
 "J2",2.645980 ,-76.647460,Top,270.000000
 "J4",5.245980 ,-48.997460,Top,270.000000

sbus-to-ztex/sbus-to-ztex-drl.rpt

@@ -1,5 +1,5 @@
 Drill report for /home/dolbeau/SPARC/SBusFPGA.V1_X/sbus-to-ztex/sbus-to-ztex.kicad_pcb
-Created on Tue Sep 19 10:22:30 2023
+Created on Sat Sep 23 08:26:59 2023
 
 Copper Layer Stackup:
     =============================================================
@@ -12,8 +12,8 @@ Copper Layer Stackup:
 Drill file 'sbus-to-ztex-PTH.drl' contains
     plated through holes:
     =============================================================
-    T1  0.30mm  0.012"  (15 holes)
-    T2  0.40mm  0.016"  (75 holes)
+    T1  0.30mm  0.012"  (16 holes)
+    T2  0.40mm  0.016"  (80 holes)
     T3  0.50mm  0.020"  (2 holes)  (with 2 slots)
     T4  0.55mm  0.022"  (2 holes)  (with 2 slots)
     T5  0.80mm  0.031"  (96 holes)
@@ -24,7 +24,7 @@ Drill file 'sbus-to-ztex-PTH.drl' contains
     T10  1.30mm  0.051"  (4 holes)
     T11  2.20mm  0.087"  (1 hole)
 
-    Total plated holes count 352
+    Total plated holes count 358
 
 
 Drill file 'sbus-to-ztex-NPTH.drl' contains

sbus-to-ztex/sbus-to-ztex.xml

@@ -2,7 +2,7 @@
 <export version="D">
   <design>
     <source>/home/dolbeau/SPARC/SBusFPGA.V1_X/sbus-to-ztex/sbus-to-ztex.sch</source>
-    <date>Tue Sep 19 10:23:17 2023</date>
+    <date>Sat Sep 23 08:27:57 2023</date>
     <tool>Eeschema 5.1.9+dfsg1-1~bpo10+1</tool>
     <sheet number="1" name="/" tstamps="/">
       <title_block>