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Add the sbus-to-zex gateware

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This commit is contained in:
Romain Dolbeau 2020-12-13 14:58:52 +01:00
parent 322e8afc61
commit e105dcb274
10 changed files with 2928 additions and 0 deletions
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1
sbus-to-ztex-gateware/.cvsignore Normal file
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sbus_fsm_TB*.vhd

33
sbus-to-ztex-gateware/Makefile Normal file
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TESTBENCHES_FILES=\
sbus_fsm_TB_write_leds_word.vhd \
sbus_fsm_TB_write_leds_byte.vhd \
sbus_fsm_TB_read_prom_word.vhd \
sbus_fsm_TB_read_prom_burst4.vhd \
sbus_fsm_TB_read_prom_byte.vhd \
sbus_fsm_TB_read_prom_hword.vhd \
sbus_fsm_TB_do_gcm.vhd
CPP=cpp -P
all: $(TESTBENCHES_FILES)
sbus_fsm_TB_write_leds_word.vhd: sbus_fsm_TB.vhd.cpp
$(CPP) -DWRITE_LEDS_WORD $< -o $@
sbus_fsm_TB_write_leds_byte.vhd: sbus_fsm_TB.vhd.cpp
$(CPP) -DWRITE_LEDS_BYTE $< -o $@
sbus_fsm_TB_read_prom_word.vhd: sbus_fsm_TB.vhd.cpp
$(CPP) -DREAD_PROM_WORD $< -o $@
sbus_fsm_TB_read_prom_burst4.vhd: sbus_fsm_TB.vhd.cpp
$(CPP) -DREAD_PROM_BURST4 $< -o $@
sbus_fsm_TB_read_prom_byte.vhd: sbus_fsm_TB.vhd.cpp
$(CPP) -DREAD_PROM_BYTE $< -o $@
sbus_fsm_TB_read_prom_hword.vhd: sbus_fsm_TB.vhd.cpp
$(CPP) -DREAD_PROM_HWORD $< -o $@
sbus_fsm_TB_do_gcm.vhd: sbus_fsm_TB.vhd.cpp
$(CPP) -DDO_GCM $< -o $@

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sbus-to-ztex-gateware/UART_TX.vhd Normal file
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----------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
----------------------------------------------------------------------
-- This file contains the UART Transmitter. This transmitter is able
-- to transmit 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When transmit is complete o_TX_Done will be
-- driven high for one clock cycle.
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART_TX is
generic (
g_CLKS_PER_BIT : integer := 417 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end UART_TX;
architecture RTL of UART_TX is
type t_SM_Main is (s_Idle, s_TX_Start_Bit, s_TX_Data_Bits,
s_TX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_TX_Data : std_logic_vector(7 downto 0) := (others => '0');
signal r_TX_Done : std_logic := '0';
begin
p_UART_TX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
o_TX_Active <= '0';
o_TX_Serial <= '1'; -- Drive Line High for Idle
r_TX_Done <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if i_TX_DV = '1' then
r_TX_Data <= i_TX_Byte;
r_SM_Main <= s_TX_Start_Bit;
else
r_SM_Main <= s_Idle;
end if;
-- Send out Start Bit. Start bit = 0
when s_TX_Start_Bit =>
o_TX_Active <= '1';
o_TX_Serial <= '0';
-- Wait g_CLKS_PER_BIT-1 clock cycles for start bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Start_Bit;
else
r_Clk_Count <= 0;
r_SM_Main <= s_TX_Data_Bits;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles for data bits to finish
when s_TX_Data_Bits =>
o_TX_Serial <= r_TX_Data(r_Bit_Index);
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Clk_Count <= 0;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Bit_Index <= 0;
r_SM_Main <= s_TX_Stop_Bit;
end if;
end if;
-- Send out Stop bit. Stop bit = 1
when s_TX_Stop_Bit =>
o_TX_Serial <= '1';
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Stop_Bit;
else
r_TX_Done <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
o_TX_Active <= '0';
r_TX_Done <= '1';
r_SM_Main <= s_Idle;
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_TX;
o_TX_Done <= r_TX_Done;
end RTL;

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sbus-to-ztex-gateware/led8.vhd Normal file
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-- include libraries
-- standard stuff
library IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE LedHandlerPkg IS
END LedHandlerPkg;
PACKAGE BODY LedHandlerPkg IS
END LedHandlerPkg;
-- include libraries
-- standard stuff
library IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY LedHandler IS
PORT(
l_ifclk: IN std_logic; -- 48 MHz FX clock or SBus clock to avoid cross-domain clocking
l_LED_RESET: IN std_logic := '0';
l_LED_DATA: IN std_logic_vector(31 downto 0) := (others => '0');
l_LED0 : OUT std_logic := '0';
l_LED1 : OUT std_logic := '0';
l_LED2 : OUT std_logic := '0';
l_LED3 : OUT std_logic := '0';
l_LED4 : OUT std_logic := '0';
l_LED5 : OUT std_logic := '0';
l_LED6 : OUT std_logic := '0';
l_LED7 : OUT std_logic := '0'
);
END ENTITY;
ARCHITECTURE RTL OF LedHandler IS
TYPE Led_States IS (Led_Off,
Led_On,
Led_b0,
Led_b1,
Led_b2,
Led_b3);
SIGNAL State : Led_States := Led_Off;
-- FOURTH/FORTIETH was too fast, double
-- 48 MHz Clock
-- CONSTANT ONE_FOURTH : natural := 24000000;
-- CONSTANT ONE_FORTIETH : natural := 2400000;
-- SBus Clock @ 25 MHz
CONSTANT ONE_FOURTH : natural := 12500000;
CONSTANT ONE_FORTIETH : natural := 1250000;
-- Simulation time frame
-- CONSTANT ONE_FOURTH : natural := 3;
-- CONSTANT ONE_FORTIETH : natural := 1;
SIGNAL TIME_COUNTER : natural range 0 to ONE_FOURTH := 0;
SIGNAL BLINK_COUNTER : natural range 0 to 5 := 0;
BEGIN
PROCESS (l_ifclk, l_LED_RESET)
BEGIN
IF (l_LED_RESET = '1') THEN
State <= Led_Off;
TIME_COUNTER <= 0;
BLINK_COUNTER <= 0;
END IF;
IF rising_edge(l_ifclk) THEN
CASE State IS
WHEN Led_Off =>
l_LED0 <= '0';
l_LED1 <= '0';
l_LED2 <= '0';
l_LED3 <= '0';
l_LED4 <= '0';
l_LED5 <= '0';
l_LED6 <= '0';
l_LED7 <= '0';
if (TIME_COUNTER = ONE_FORTIETH-1) then
TIME_COUNTER <= 0;
State <= Led_On;
else
TIME_COUNTER <= TIME_COUNTER+1;
end if;
WHEN Led_On =>
l_LED0 <= '1';
l_LED1 <= '1';
l_LED2 <= '1';
l_LED3 <= '1';
l_LED4 <= '1';
l_LED5 <= '1';
l_LED6 <= '1';
l_LED7 <= '1';
if (TIME_COUNTER = ONE_FORTIETH-1) then
TIME_COUNTER <= 0;
if (BLINK_COUNTER = 4) then
BLINK_COUNTER <= 0;
State <= Led_b0;
else
BLINK_COUNTER <= BLINK_COUNTER +1;
State <= Led_Off;
end if;
else
TIME_COUNTER <= TIME_COUNTER+1;
end if;
when Led_b0 =>
l_LED0 <= l_LED_DATA(0);
l_LED1 <= l_LED_DATA(1);
l_LED2 <= l_LED_DATA(2);
l_LED3 <= l_LED_DATA(3);
l_LED4 <= l_LED_DATA(4);
l_LED5 <= l_LED_DATA(5);
l_LED6 <= l_LED_DATA(6);
l_LED7 <= l_LED_DATA(7);
if (TIME_COUNTER = ONE_FOURTH-1) then
TIME_COUNTER <= 0;
State <= Led_b1;
else
TIME_COUNTER <= TIME_COUNTER+1;
end if;
when Led_b1 =>
l_LED0 <= l_LED_DATA(8);
l_LED1 <= l_LED_DATA(9);
l_LED2 <= l_LED_DATA(10);
l_LED3 <= l_LED_DATA(11);
l_LED4 <= l_LED_DATA(12);
l_LED5 <= l_LED_DATA(13);
l_LED6 <= l_LED_DATA(14);
l_LED7 <= l_LED_DATA(15);
if (TIME_COUNTER = ONE_FOURTH-1) then
TIME_COUNTER <= 0;
State <= Led_b2;
else
TIME_COUNTER <= TIME_COUNTER+1;
end if;
when Led_b2 =>
l_LED0 <= l_LED_DATA(16);
l_LED1 <= l_LED_DATA(17);
l_LED2 <= l_LED_DATA(18);
l_LED3 <= l_LED_DATA(19);
l_LED4 <= l_LED_DATA(20);
l_LED5 <= l_LED_DATA(21);
l_LED6 <= l_LED_DATA(22);
l_LED7 <= l_LED_DATA(23);
if (TIME_COUNTER = ONE_FOURTH-1) then
TIME_COUNTER <= 0;
State <= Led_b3;
else
TIME_COUNTER <= TIME_COUNTER+1;
end if;
when Led_b3 =>
l_LED0 <= l_LED_DATA(24);
l_LED1 <= l_LED_DATA(25);
l_LED2 <= l_LED_DATA(26);
l_LED3 <= l_LED_DATA(27);
l_LED4 <= l_LED_DATA(28);
l_LED5 <= l_LED_DATA(29);
l_LED6 <= l_LED_DATA(30);
l_LED7 <= l_LED_DATA(31);
if (TIME_COUNTER = ONE_FOURTH-1) then
TIME_COUNTER <= 0;
State <= Led_Off;
else
TIME_COUNTER <= TIME_COUNTER+1;
end if;
END case;
END if;
end process;
end RTL;

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sbus-to-ztex-gateware/mastrovito_v2_multiplier.vhd Normal file
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-- from http://www.arithmetic-circuits.org/finite-field/vhdl_codes.htm
-- only change is to hardwire the proper M and F for GHASH (GCM)
----------------------------------------------------------------------------
-- Mastrovito Multiplier, second version (mastrovito_V2_multiplier.vhd)
--
-- Computes the polynomial multiplication mod f in GF(2**m)
-- The hardware is genenerate for a specific f.
--
--
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
package mastrovito_V2_multiplier_parameters is
constant M: integer := 128;
constant F: std_logic_vector(M-1 downto 0):= (0 => '1', 1 => '1', 2 => '1', 7 => '1', others => '0'); --for GHASH
--constant F: std_logic_vector(M-1 downto 0):= "00011011";
--constant F: std_logic_vector(M-1 downto 0):= x"001B"; --for M=16 bits
--constant F: std_logic_vector(M-1 downto 0):= x"0101001B"; --for M=32 bits
--constant F: std_logic_vector(M-1 downto 0):= x"010100000101001B"; --for M=64 bits
--constant F: std_logic_vector(M-1 downto 0):= x"0000000000000000010100000101001B"; --for M=128 bits
--constant F: std_logic_vector(M-1 downto 0):= "000"&x"00000000000000000000000000000000000000C9"; --for M=163
--constant F: std_logic_vector(M-1 downto 0):= (0=> '1', 74 => '1', others => '0'); --for M=233
type matrix_reductionR is array (0 to M-1) of STD_LOGIC_VECTOR(M-2 downto 0);
function reduction_matrix_R return matrix_reductionR;
end mastrovito_V2_multiplier_parameters;
package body mastrovito_V2_multiplier_parameters is
function reduction_matrix_R return matrix_reductionR is
variable R: matrix_reductionR;
begin
for j in 0 to M-1 loop
for i in 0 to M-2 loop
R(j)(i) := '0';
end loop;
end loop;
for j in 0 to M-1 loop
R(j)(0) := f(j);
end loop;
for i in 1 to M-2 loop
for j in 0 to M-1 loop
if j = 0 then
R(j)(i) := R(M-1)(i-1) and R(j)(0);
else
R(j)(i) := R(j-1)(i-1) xor (R(M-1)(i-1) and R(j)(0));
end if;
end loop;
end loop;
return R;
end reduction_matrix_R;
end mastrovito_V2_multiplier_parameters;
------------------------------------------------------------
-- Classic Multiplication
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mastrovito_V2_multiplier_parameters.all;
entity mastrovito_V2_multiplication is
port (
a, b: in std_logic_vector(M-1 downto 0);
c: out std_logic_vector(M-1 downto 0)
);
end mastrovito_V2_multiplication;
architecture simple of mastrovito_V2_multiplication is
constant R: matrix_reductionR := reduction_matrix_R;
signal D: std_logic_vector (M-1 downto 0);
signal E: std_logic_vector (M-2 downto 0);
begin
genD: process(a,b)
variable di: std_logic_vector(M-1 downto 0);
begin
for i in 0 to M-1 loop
di(i) := '0';
for k in 0 to i loop
di(i) := (di(i) xor (a(k) and b(i-k)));
end loop;
end loop;
D <= di;
end process genD;
genE: process(a,b)
variable ei: std_logic_vector(M-2 downto 0);
begin
for i in 0 to M-2 loop
ei(i) := '0';
for k in i to M-2 loop
ei(i) := (ei(i) xor (a(M-1-(k-i)) and b(k+1)));
end loop;
end loop;
E <= ei;
end process genE;
--Mastrovito multiplication, second version
mastrovitoV2: process(e,d)
variable ci, re: std_logic_vector(M-1 downto 0);
begin
for i in 0 to M-1 loop
re(i) := (R(i)(0) and E(0));
--re(i) := '0';
for j in 1 to M-2 loop
re(i) := (re(i) xor (R(i)(j) and E(j)));
end loop;
ci(i) := (D(i) xor re(i));
end loop;
C <= ci;
end process;
end simple;

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-- include libraries
-- standard stuff
library IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE PromPkg IS
END PromPkg;
PACKAGE BODY PromPkg IS
END PromPkg;
library IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Prom is
GENERIC(
addr_width : integer := 128; -- store 128 elements (512 bytes)
addr_bits : integer := 7; -- required bits to store 128 elements
data_width : integer := 32 -- each element has 32-bits
);
PORT(
addr : IN std_logic_vector(addr_bits-1 downto 0);
data : OUT std_logic_vector(data_width-1 downto 0)
);
end Prom;
architecture arch of Prom is
type rom_type is array (0 to addr_width-1) of std_logic_vector(data_width-1 downto 0);
signal Prom_ROM : rom_type := (
-- copy/paste the ROM content here --
"11111101000010000000010001111001", -- 1
"00000000000000000000000000101011", -- 2
"00010010000011010101001001000100", -- 3
"01001111010011000010110001010011", -- 4
"01000010011101010111001101000110", -- 5
"01010000010001110100000100000010", -- 6
"00000001000000010000001000010000", -- 7
"00000000000000000000001000000000", -- 8
"00011110000000010000001100010000", -- 9
"00000000000000000000000100000000", -- 10
"00000001000101100000000000000000", -- 11
-- "11111101000010000001001000110001", -- 1
-- "00000000000000000000000001100001", -- 2
-- "10000111000100100000110101010010", -- 3
-- "01000100010011110100110000101100", -- 4
-- "01010011010000100111010101110011", -- 5
-- "01000110010100000100011101000001", -- 6
-- "00000001000101000001001000000100", -- 7
-- "01101110011000010110110101100101", -- 8
-- "00000001000100000000000100000010", -- 9
-- "00010000000000000000000000000010", -- 10
-- "00000000000111100000000100000011", -- 11
-- "00010000000000000000000000000000", -- 12
-- "00000100000100100000001101110010", -- 13
-- "01100101011001110000000100010000", -- 14
-- "00010000000000000000000000000000", -- 15
-- "00010101000100100001000101110011", -- 16
-- "01101100011000010111011001100101", -- 17
-- "00101101011000100111010101110010", -- 18
-- "01110011011101000010110101110011", -- 19
-- "01101001011110100110010101110011", -- 20
-- "00000001000100001011010100001000", -- 21
-- "00000000101101110000000100000010", -- 22
-- "00010000000000000000000000000010", -- 23
-- "00000000000111100111001011000010", -- 24
-- ROM then filled with zero
others => (others => '0'));
begin
data <= Prom_ROM(conv_integer(unsigned(addr)));
end arch;

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sbus-to-ztex-gateware/sbus-to-ztex-timings.xdc Normal file
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# keep those for which timings are irrelevant
# timing doesn't matter for LEDs
set_false_path -from * -to [get_ports { SBUS_DATA_OE_LED } ]
set_false_path -from * -to [get_ports { SBUS_DATA_OE_LED_2 } ]
set_false_path -from * -to [get_ports { LED0 } ]
set_false_path -from * -to [get_ports { LED1 } ]
set_false_path -from * -to [get_ports { LED2 } ]
set_false_path -from * -to [get_ports { LED3 } ]
set_false_path -from * -to [get_ports { LED4 } ]
set_false_path -from * -to [get_ports { LED5 } ]
set_false_path -from * -to [get_ports { LED6 } ]
set_false_path -from * -to [get_ports { LED7 } ]
# timing doesn't matter for INTs, slow and async
set_false_path -from * -to [get_ports { SBUS_3V3_INT1s } ]
set_false_path -from * -to [get_ports { SBUS_3V3_INT7s } ]
# slow
set_false_path -from * -to [get_ports { TX } ]
# unrelated
set_clock_groups -asynchronous -group [get_clocks SBUS_3V3_CLK] -group [get_clocks fxclk_in]
# timing doesn't matter for RST, very long hold
set_false_path -from [get_ports { SBUS_3V3_RSTs } ] -to *
# shut up the warning for the LEDs (the set_false_path already lower severity)
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { SBUS_DATA_OE_LED } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { SBUS_DATA_OE_LED_2 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED0 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED1 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED2 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED3 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED4 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED5 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED6 } ]
set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED7 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { SBUS_DATA_OE_LED } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { SBUS_DATA_OE_LED_2 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED0 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED1 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED2 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED3 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED4 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED5 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED6 } ]
set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED7 } ]
# COPY/PASTE here, same fixes needed as in the other XDC file
set_input_delay -clock SBUS_3V3_CLK -min 0.838 [get_ports {SBUS_3V3_D[1]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.368 [get_ports {SBUS_3V3_D[1]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.738 [get_ports {SBUS_3V3_D[1]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.516 [get_ports {SBUS_3V3_D[1]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.874 [get_ports {SBUS_3V3_D[0]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.415 [get_ports {SBUS_3V3_D[0]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.702 [get_ports {SBUS_3V3_D[0]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.564 [get_ports {SBUS_3V3_D[0]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.841 [get_ports {SBUS_3V3_D[3]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.371 [get_ports {SBUS_3V3_D[3]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.736 [get_ports {SBUS_3V3_D[3]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.519 [get_ports {SBUS_3V3_D[3]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.838 [get_ports {SBUS_3V3_D[2]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.368 [get_ports {SBUS_3V3_D[2]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.738 [get_ports {SBUS_3V3_D[2]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.516 [get_ports {SBUS_3V3_D[2]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.842 [get_ports {SBUS_3V3_D[5]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.373 [get_ports {SBUS_3V3_D[5]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.734 [get_ports {SBUS_3V3_D[5]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.522 [get_ports {SBUS_3V3_D[5]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.882 [get_ports {SBUS_3V3_D[4]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.426 [get_ports {SBUS_3V3_D[4]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.694 [get_ports {SBUS_3V3_D[4]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.575 [get_ports {SBUS_3V3_D[4]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.839 [get_ports {SBUS_3V3_D[6]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.369 [get_ports {SBUS_3V3_D[6]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.737 [get_ports {SBUS_3V3_D[6]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.517 [get_ports {SBUS_3V3_D[6]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.810 [get_ports {SBUS_3V3_D[7]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.330 [get_ports {SBUS_3V3_D[7]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.766 [get_ports {SBUS_3V3_D[7]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.478 [get_ports {SBUS_3V3_D[7]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.810 [get_ports {SBUS_3V3_D[8]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.330 [get_ports {SBUS_3V3_D[8]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.766 [get_ports {SBUS_3V3_D[8]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.479 [get_ports {SBUS_3V3_D[8]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.751 [get_ports {SBUS_3V3_D[9]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.251 [get_ports {SBUS_3V3_D[9]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.825 [get_ports {SBUS_3V3_D[9]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.400 [get_ports {SBUS_3V3_D[9]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.804 [get_ports {SBUS_3V3_D[10]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.322 [get_ports {SBUS_3V3_D[10]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.772 [get_ports {SBUS_3V3_D[10]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.470 [get_ports {SBUS_3V3_D[10]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.756 [get_ports {SBUS_3V3_D[11]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.258 [get_ports {SBUS_3V3_D[11]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.820 [get_ports {SBUS_3V3_D[11]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.407 [get_ports {SBUS_3V3_D[11]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.778 [get_ports {SBUS_3V3_D[12]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.287 [get_ports {SBUS_3V3_D[12]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.798 [get_ports {SBUS_3V3_D[12]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.436 [get_ports {SBUS_3V3_D[12]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.729 [get_ports {SBUS_3V3_D[13]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.222 [get_ports {SBUS_3V3_D[13]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.847 [get_ports {SBUS_3V3_D[13]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.371 [get_ports {SBUS_3V3_D[13]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.750 [get_ports {SBUS_3V3_D[14]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.250 [get_ports {SBUS_3V3_D[14]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.826 [get_ports {SBUS_3V3_D[14]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.398 [get_ports {SBUS_3V3_D[14]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.708 [get_ports {SBUS_3V3_D[15]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.193 [get_ports {SBUS_3V3_D[15]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.869 [get_ports {SBUS_3V3_D[15]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.342 [get_ports {SBUS_3V3_D[15]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.817 [get_ports {SBUS_3V3_D[16]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.339 [get_ports {SBUS_3V3_D[16]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.759 [get_ports {SBUS_3V3_D[16]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.488 [get_ports {SBUS_3V3_D[16]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.707 [get_ports {SBUS_3V3_D[17]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.192 [get_ports {SBUS_3V3_D[17]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.870 [get_ports {SBUS_3V3_D[17]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.341 [get_ports {SBUS_3V3_D[17]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.724 [get_ports {SBUS_3V3_D[18]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.215 [get_ports {SBUS_3V3_D[18]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.852 [get_ports {SBUS_3V3_D[18]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.364 [get_ports {SBUS_3V3_D[18]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.711 [get_ports {SBUS_3V3_D[19]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.198 [get_ports {SBUS_3V3_D[19]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.865 [get_ports {SBUS_3V3_D[19]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.347 [get_ports {SBUS_3V3_D[19]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.708 [get_ports {SBUS_3V3_D[20]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.194 [get_ports {SBUS_3V3_D[20]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.868 [get_ports {SBUS_3V3_D[20]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.342 [get_ports {SBUS_3V3_D[20]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.758 [get_ports {SBUS_3V3_D[21]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.261 [get_ports {SBUS_3V3_D[21]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.818 [get_ports {SBUS_3V3_D[21]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.410 [get_ports {SBUS_3V3_D[21]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.707 [get_ports {SBUS_3V3_D[22]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.192 [get_ports {SBUS_3V3_D[22]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.870 [get_ports {SBUS_3V3_D[22]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.341 [get_ports {SBUS_3V3_D[22]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.695 [get_ports {SBUS_3V3_D[23]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.177 [get_ports {SBUS_3V3_D[23]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.881 [get_ports {SBUS_3V3_D[23]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.325 [get_ports {SBUS_3V3_D[23]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.654 [get_ports {SBUS_3V3_D[24]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.122 [get_ports {SBUS_3V3_D[24]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.922 [get_ports {SBUS_3V3_D[24]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.271 [get_ports {SBUS_3V3_D[24]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.682 [get_ports {SBUS_3V3_D[25]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.159 [get_ports {SBUS_3V3_D[25]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.894 [get_ports {SBUS_3V3_D[25]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.308 [get_ports {SBUS_3V3_D[25]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.633 [get_ports {SBUS_3V3_D[26]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.094 [get_ports {SBUS_3V3_D[26]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.943 [get_ports {SBUS_3V3_D[26]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.243 [get_ports {SBUS_3V3_D[26]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.655 [get_ports {SBUS_3V3_D[27]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.123 [get_ports {SBUS_3V3_D[27]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.921 [get_ports {SBUS_3V3_D[27]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.272 [get_ports {SBUS_3V3_D[27]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.632 [get_ports {SBUS_3V3_D[28]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.093 [get_ports {SBUS_3V3_D[28]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.944 [get_ports {SBUS_3V3_D[28]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.241 [get_ports {SBUS_3V3_D[28]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.662 [get_ports {SBUS_3V3_D[29]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.133 [get_ports {SBUS_3V3_D[29]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.914 [get_ports {SBUS_3V3_D[29]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.281 [get_ports {SBUS_3V3_D[29]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.618 [get_ports {SBUS_3V3_D[30]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.074 [get_ports {SBUS_3V3_D[30]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.958 [get_ports {SBUS_3V3_D[30]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.222 [get_ports {SBUS_3V3_D[30]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.688 [get_ports {SBUS_3V3_D[31]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.168 [get_ports {SBUS_3V3_D[31]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.888 [get_ports {SBUS_3V3_D[31]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.316 [get_ports {SBUS_3V3_D[31]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.645 [get_ports {SBUS_3V3_PA[1]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.109 [get_ports {SBUS_3V3_PA[1]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.649 [get_ports {SBUS_3V3_PA[0]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.116 [get_ports {SBUS_3V3_PA[0]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.658 [get_ports {SBUS_3V3_PA[3]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.127 [get_ports {SBUS_3V3_PA[3]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.656 [get_ports {SBUS_3V3_PA[2]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.125 [get_ports {SBUS_3V3_PA[2]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.679 [get_ports {SBUS_3V3_PA[4]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.155 [get_ports {SBUS_3V3_PA[4]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.666 [get_ports {SBUS_3V3_PA[5]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.138 [get_ports {SBUS_3V3_PA[5]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.680 [get_ports {SBUS_3V3_PA[6]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.157 [get_ports {SBUS_3V3_PA[6]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.682 [get_ports {SBUS_3V3_PA[7]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.160 [get_ports {SBUS_3V3_PA[7]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.685 [get_ports {SBUS_3V3_PA[8]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.164 [get_ports {SBUS_3V3_PA[8]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.714 [get_ports {SBUS_3V3_PA[9]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.202 [get_ports {SBUS_3V3_PA[9]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.703 [get_ports {SBUS_3V3_PA[10]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.188 [get_ports {SBUS_3V3_PA[10]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.714 [get_ports {SBUS_3V3_PA[11]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.201 [get_ports {SBUS_3V3_PA[11]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.715 [get_ports {SBUS_3V3_PA[12]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.203 [get_ports {SBUS_3V3_PA[12]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.733 [get_ports {SBUS_3V3_PA[13]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.227 [get_ports {SBUS_3V3_PA[13]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.729 [get_ports {SBUS_3V3_PA[14]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.221 [get_ports {SBUS_3V3_PA[14]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.996 [get_ports {SBUS_3V3_SIZ[0]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.578 [get_ports {SBUS_3V3_SIZ[0]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.936 [get_ports {SBUS_3V3_ASs}]
set_input_delay -clock SBUS_3V3_CLK -max 25.497 [get_ports {SBUS_3V3_ASs}]
set_input_delay -clock SBUS_3V3_CLK -min 1.025 [get_ports {SBUS_3V3_BGs}]
set_input_delay -clock SBUS_3V3_CLK -max 25.617 [get_ports {SBUS_3V3_BGs}]
set_output_delay -clock SBUS_3V3_CLK -min -1.625 [get_ports {SBUS_3V3_BRs}]
set_output_delay -clock SBUS_3V3_CLK -max 21.667 [get_ports {SBUS_3V3_BRs}]
set_input_delay -clock SBUS_3V3_CLK -min 0.921 [get_ports {SBUS_3V3_SIZ[1]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.478 [get_ports {SBUS_3V3_SIZ[1]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.932 [get_ports {SBUS_3V3_SIZ[2]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.493 [get_ports {SBUS_3V3_SIZ[2]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.649 [get_ports {SBUS_3V3_ERRs}]
set_output_delay -clock SBUS_3V3_CLK -max 21.634 [get_ports {SBUS_3V3_ERRs}]
set_input_delay -clock SBUS_3V3_CLK -min 1.100 [get_ports {SBUS_3V3_RSTs}]
set_input_delay -clock SBUS_3V3_CLK -max 25.717 [get_ports {SBUS_3V3_RSTs}]
set_input_delay -clock SBUS_3V3_CLK -min 0.931 [get_ports {SBUS_3V3_SELs}]
set_input_delay -clock SBUS_3V3_CLK -max 25.491 [get_ports {SBUS_3V3_SELs}]
set_output_delay -clock SBUS_3V3_CLK -min -1.443 [get_ports {SBUS_3V3_INT1s}]
set_output_delay -clock SBUS_3V3_CLK -max 21.909 [get_ports {SBUS_3V3_INT1s}]
set_input_delay -clock SBUS_3V3_CLK -min 0.831 [get_ports {SBUS_3V3_PPRD}]
set_input_delay -clock SBUS_3V3_CLK -max 25.358 [get_ports {SBUS_3V3_PPRD}]
set_output_delay -clock SBUS_3V3_CLK -min -1.743 [get_ports {SBUS_3V3_ACKs[0]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.510 [get_ports {SBUS_3V3_ACKs[0]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.678 [get_ports {SBUS_3V3_INT7s}]
set_output_delay -clock SBUS_3V3_CLK -max 21.597 [get_ports {SBUS_3V3_INT7s}]
set_output_delay -clock SBUS_3V3_CLK -min -1.747 [get_ports {SBUS_3V3_ACKs[1]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.504 [get_ports {SBUS_3V3_ACKs[1]}]
set_output_delay -clock SBUS_3V3_CLK -min -1.778 [get_ports {SBUS_3V3_ACKs[2]}]
set_output_delay -clock SBUS_3V3_CLK -max 21.463 [get_ports {SBUS_3V3_ACKs[2]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.788 [get_ports {SBUS_3V3_PA[15]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.301 [get_ports {SBUS_3V3_PA[15]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.797 [get_ports {SBUS_3V3_PA[17]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.313 [get_ports {SBUS_3V3_PA[17]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.855 [get_ports {SBUS_3V3_PA[16]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.389 [get_ports {SBUS_3V3_PA[16]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.811 [get_ports {SBUS_3V3_PA[19]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.332 [get_ports {SBUS_3V3_PA[19]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.852 [get_ports {SBUS_3V3_PA[18]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.386 [get_ports {SBUS_3V3_PA[18]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.812 [get_ports {SBUS_3V3_PA[21]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.332 [get_ports {SBUS_3V3_PA[21]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.849 [get_ports {SBUS_3V3_PA[20]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.382 [get_ports {SBUS_3V3_PA[20]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.818 [get_ports {SBUS_3V3_PA[23]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.340 [get_ports {SBUS_3V3_PA[23]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.859 [get_ports {SBUS_3V3_PA[22]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.395 [get_ports {SBUS_3V3_PA[22]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.827 [get_ports {SBUS_3V3_PA[25]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.352 [get_ports {SBUS_3V3_PA[25]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.863 [get_ports {SBUS_3V3_PA[24]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.401 [get_ports {SBUS_3V3_PA[24]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.824 [get_ports {SBUS_3V3_PA[27]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.348 [get_ports {SBUS_3V3_PA[27]}]
set_input_delay -clock SBUS_3V3_CLK -min 0.871 [get_ports {SBUS_3V3_PA[26]}]
set_input_delay -clock SBUS_3V3_CLK -max 25.412 [get_ports {SBUS_3V3_PA[26]}]

514
sbus-to-ztex-gateware/sbus-to-ztex.xdc Normal file
View File

@ -0,0 +1,514 @@
# !!! Constraint files are application specific !!!
# !!! This is a template only !!!
# on-board signals
# CLKOUT/FXCLK
create_clock -name fxclk_in -period 20.833 [get_ports fxclk_in]
set_property PACKAGE_PIN P15 [get_ports fxclk_in]
set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
# IFCLK
#create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in]
#set_property PACKAGE_PIN P17 [get_ports ifclk_in]
#set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
#set_property PACKAGE_PIN M16 [get_ports {PB[0]}] ;# PB0/FD0
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[0]}]
#set_property PACKAGE_PIN L16 [get_ports {PB[1]}] ;# PB1/FD1
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[1]}]
#set_property PACKAGE_PIN L14 [get_ports {PB[2]}] ;# PB2/FD2
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[2]}]
#set_property PACKAGE_PIN M14 [get_ports {PB[3]}] ;# PB3/FD3
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[3]}]
#set_property PACKAGE_PIN L18 [get_ports {PB[4]}] ;# PB4/FD4
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[4]}]
#set_property PACKAGE_PIN M18 [get_ports {PB[5]}] ;# PB5/FD5
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[5]}]
#set_property PACKAGE_PIN R12 [get_ports {PB[6]}] ;# PB6/FD6
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[6]}]
#set_property PACKAGE_PIN R13 [get_ports {PB[7]}] ;# PB7/FD7
#set_property IOSTANDARD LVCMOS33 [get_ports {PB[7]}]
#set_property PACKAGE_PIN T9 [get_ports {PD[0]}] ;# PD0/FD8
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[0]}]
#set_property PACKAGE_PIN V10 [get_ports {PD[1]}] ;# PD1/FD9
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[1]}]
#set_property PACKAGE_PIN U11 [get_ports {PD[2]}] ;# PD2/FD10
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[2]}]
#set_property PACKAGE_PIN V11 [get_ports {PD[3]}] ;# PD3/FD11
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[3]}]
#set_property PACKAGE_PIN V12 [get_ports {PD[4]}] ;# PD4/FD12
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[4]}]
#set_property PACKAGE_PIN U13 [get_ports {PD[5]}] ;# PD5/FD13
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[5]}]
#set_property PACKAGE_PIN U14 [get_ports {PD[6]}] ;# PD6/FD14
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[6]}]
#set_property PACKAGE_PIN V14 [get_ports {PD[7]}] ;# PD7/FD15
#set_property IOSTANDARD LVCMOS33 [get_ports {PD[7]}]
#set_property PACKAGE_PIN R15 [get_ports {PA[0]}] ;# PA0/INT0#
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}]
#set_property PACKAGE_PIN T15 [get_ports {PA[1]}] ;# PA1/INT1#
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}]
#set_property PACKAGE_PIN T14 [get_ports {PA[2]}] ;# PA2/SLOE
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}]
#set_property PACKAGE_PIN T13 [get_ports {PA[3]}] ;# PA3/WU2
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}]
#set_property PACKAGE_PIN R11 [get_ports {PA[4]}] ;# PA4/FIFOADR0
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}]
#set_property PACKAGE_PIN T11 [get_ports {PA[5]}] ;# PA5/FIFOADR1
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}]
#set_property PACKAGE_PIN R10 [get_ports {PA[6]}] ;# PA6/PKTEND
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}]
#set_property PACKAGE_PIN T10 [get_ports {PA[7]}] ;# PA7/FLAGD/SLCS#
#set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}]
#set_property PACKAGE_PIN R17 [get_ports {PC[0]}] ;# PC0/GPIFADR0
#set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
#set_property PACKAGE_PIN R18 [get_ports {PC[1]}] ;# PC1/GPIFADR1
#set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
#set_property PACKAGE_PIN P18 [get_ports {PC[2]}] ;# PC2/GPIFADR2
#set_property IOSTANDARD LVCMOS33 [get_ports {PC[2]}]
#set_property PACKAGE_PIN P14 [get_ports {PC[3]}] ;# PC3/GPIFADR3
#set_property IOSTANDARD LVCMOS33 [get_ports {PC[3]}]
#set_property PACKAGE_PIN K18 [get_ports {FLASH_DO}] ;# PC4/GPIFADR4
#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DO}]
#set_property PACKAGE_PIN L13 [get_ports {FLASH_CS}] ;# PC5/GPIFADR5
#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CS}]
#set_property PACKAGE_PIN E9 [get_ports {FLASH_CLK}] ;# PC6/GPIFADR6
#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CLK}]
#set_property PACKAGE_PIN K17 [get_ports {FLASH_DI}] ;# PC7/GPIFADR7
#set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DI}]
#set_property PACKAGE_PIN P10 [get_ports {PE[0]}] ;# PE0/T0OUT
#set_property IOSTANDARD LVCMOS33 [get_ports {PE[0]}]
#set_property PACKAGE_PIN P7 [get_ports {PE[1]}] ;# PE1/T1OUT
#set_property IOSTANDARD LVCMOS33 [get_ports {PE[1]}]
#set_property PACKAGE_PIN V15 [get_ports {PE[2]}] ;# PE2/T2OUT
#set_property IOSTANDARD LVCMOS33 [get_ports {PE[2]}]
#set_property PACKAGE_PIN R16 [get_ports {PE[5]}] ;# PE5/INT6
#set_property IOSTANDARD LVCMOS33 [get_ports {PE[5]}]
#set_property PACKAGE_PIN T16 [get_ports {PE[6]}] ;# PE6/T2EX
#set_property IOSTANDARD LVCMOS33 [get_ports {PE[6]}]
#set_property PACKAGE_PIN V16 [get_ports {SLRD}] ;# RDY0/SLRD
#set_property IOSTANDARD LVCMOS33 [get_ports {SLRD}]
#set_property PACKAGE_PIN U16 [get_ports {SLWR}] ;# RDY1/SLWR
#set_property IOSTANDARD LVCMOS33 [get_ports {SLWR}]
#set_property PACKAGE_PIN V17 [get_ports {RDY2}] ;# RDY2
#set_property IOSTANDARD LVCMOS33 [get_ports {RDY2}]
#set_property PACKAGE_PIN U17 [get_ports {RDY3}] ;# RDY3
#set_property IOSTANDARD LVCMOS33 [get_ports {RDY3}]
#set_property PACKAGE_PIN U18 [get_ports {RDY4}] ;# RDY4
#set_property IOSTANDARD LVCMOS33 [get_ports {RDY4}]
#set_property PACKAGE_PIN T18 [get_ports {RDY5}] ;# RDY5
#set_property IOSTANDARD LVCMOS33 [get_ports {RDY5}]
#set_property PACKAGE_PIN N16 [get_ports {FLAGA}] ;# CTL0/FLAGA
#set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}]
#set_property PACKAGE_PIN N15 [get_ports {FLAGB}] ;# CTL1/FLAGB
#set_property IOSTANDARD LVCMOS33 [get_ports {FLAGB}]
#set_property PACKAGE_PIN N14 [get_ports {FLAGC}] ;# CTL2/FLAGC
#set_property IOSTANDARD LVCMOS33 [get_ports {FLAGC}]
#set_property PACKAGE_PIN N17 [get_ports {CTL3}] ;# CTL3
#set_property IOSTANDARD LVCMOS33 [get_ports {CTL3}]
#set_property PACKAGE_PIN M13 [get_ports {CTL4}] ;# CTL4
#set_property IOSTANDARD LVCMOS33 [get_ports {CTL4}]
#set_property PACKAGE_PIN D10 [get_ports {INT4}] ;# INT4
#set_property IOSTANDARD LVCMOS33 [get_ports {INT4}]
#set_property PACKAGE_PIN U12 [get_ports {INT5_N}] ;# INT5#
#set_property IOSTANDARD LVCMOS33 [get_ports {INT5_N}]
#set_property PACKAGE_PIN M17 [get_ports {T0}] ;# T0
#set_property IOSTANDARD LVCMOS33 [get_ports {T0}]
#set_property PACKAGE_PIN B8 [get_ports {SCL}] ;# SCL
#set_property IOSTANDARD LVCMOS33 [get_ports {SCL}]
#set_property PACKAGE_PIN A10 [get_ports {SDA}] ;# SDA
#set_property IOSTANDARD LVCMOS33 [get_ports {SDA}]
#set_property PACKAGE_PIN A8 [get_ports {RxD0}] ;# RxD0
#set_property IOSTANDARD LVCMOS33 [get_ports {RxD0}]
#set_property PACKAGE_PIN A9 [get_ports {TxD0}] ;# TxD0
#set_property IOSTANDARD LVCMOS33 [get_ports {TxD0}]
# external I/O
create_clock -name SBUS_3V3_CLK -period 40 [get_ports SBUS_3V3_CLK]
# COPY/PASTE here then fix
# * -> s
# ]s -> s earlier (ACK ; INT have no brackets)
# leading 0 in [0x (but not [0]!)
# comment out TX, RX, SD_*
# EER -> ERR
set_property PACKAGE_PIN K16 [get_ports {SBUS_3V3_D[1]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[1]}]
set_property PACKAGE_PIN J18 [get_ports {SBUS_3V3_D[0]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[0]}]
set_property PACKAGE_PIN K15 [get_ports {SBUS_3V3_D[3]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[3]}]
set_property PACKAGE_PIN J17 [get_ports {SBUS_3V3_D[2]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[2]}]
set_property PACKAGE_PIN J15 [get_ports {SBUS_3V3_D[5]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[5]}]
set_property PACKAGE_PIN K13 [get_ports {SBUS_3V3_D[4]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[4]}]
set_property PACKAGE_PIN J13 [get_ports {SBUS_3V3_D[6]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[6]}]
set_property PACKAGE_PIN J14 [get_ports {SBUS_3V3_D[7]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[7]}]
set_property PACKAGE_PIN H14 [get_ports {SBUS_3V3_D[8]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[8]}]
set_property PACKAGE_PIN H17 [get_ports {SBUS_3V3_D[9]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[9]}]
set_property PACKAGE_PIN G14 [get_ports {SBUS_3V3_D[10]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[10]}]
set_property PACKAGE_PIN G17 [get_ports {SBUS_3V3_D[11]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[11]}]
set_property PACKAGE_PIN G16 [get_ports {SBUS_3V3_D[12]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[12]}]
set_property PACKAGE_PIN G18 [get_ports {SBUS_3V3_D[13]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[13]}]
set_property PACKAGE_PIN H16 [get_ports {SBUS_3V3_D[14]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[14]}]
set_property PACKAGE_PIN F18 [get_ports {SBUS_3V3_D[15]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[15]}]
set_property PACKAGE_PIN F16 [get_ports {SBUS_3V3_D[16]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[16]}]
set_property PACKAGE_PIN E18 [get_ports {SBUS_3V3_D[17]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[17]}]
set_property PACKAGE_PIN F15 [get_ports {SBUS_3V3_D[18]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[18]}]
set_property PACKAGE_PIN D18 [get_ports {SBUS_3V3_D[19]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[19]}]
set_property PACKAGE_PIN E17 [get_ports {SBUS_3V3_D[20]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[20]}]
set_property PACKAGE_PIN G13 [get_ports {SBUS_3V3_D[21]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[21]}]
set_property PACKAGE_PIN D17 [get_ports {SBUS_3V3_D[22]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[22]}]
set_property PACKAGE_PIN F13 [get_ports {SBUS_3V3_D[23]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[23]}]
set_property PACKAGE_PIN F14 [get_ports {SBUS_3V3_D[24]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[24]}]
set_property PACKAGE_PIN E16 [get_ports {SBUS_3V3_D[25]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[25]}]
set_property PACKAGE_PIN E15 [get_ports {SBUS_3V3_D[26]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[26]}]
set_property PACKAGE_PIN C17 [get_ports {SBUS_3V3_D[27]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[27]}]
set_property PACKAGE_PIN C16 [get_ports {SBUS_3V3_D[28]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[28]}]
set_property PACKAGE_PIN A18 [get_ports {SBUS_3V3_D[29]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[29]}]
set_property PACKAGE_PIN B18 [get_ports {SBUS_3V3_D[30]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[30]}]
set_property PACKAGE_PIN C15 [get_ports {SBUS_3V3_D[31]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_D[31]}]
set_property PACKAGE_PIN D15 [get_ports {SBUS_3V3_CLK}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_CLK}]
set_property PACKAGE_PIN B17 [get_ports {SBUS_3V3_PA[1]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[1]}]
set_property PACKAGE_PIN B16 [get_ports {SBUS_3V3_PA[0]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[0]}]
set_property PACKAGE_PIN C14 [get_ports {SBUS_3V3_PA[3]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[3]}]
set_property PACKAGE_PIN D14 [get_ports {SBUS_3V3_PA[2]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[2]}]
set_property PACKAGE_PIN D12 [get_ports {SBUS_3V3_PA[4]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[4]}]
set_property PACKAGE_PIN A16 [get_ports {SBUS_3V3_PA[5]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[5]}]
set_property PACKAGE_PIN A15 [get_ports {SBUS_3V3_PA[6]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[6]}]
set_property PACKAGE_PIN B14 [get_ports {SBUS_3V3_PA[7]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[7]}]
set_property PACKAGE_PIN B13 [get_ports {SBUS_3V3_PA[8]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[8]}]
set_property PACKAGE_PIN B12 [get_ports {SBUS_3V3_PA[9]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[9]}]
set_property PACKAGE_PIN C12 [get_ports {SBUS_3V3_PA[10]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[10]}]
set_property PACKAGE_PIN A14 [get_ports {SBUS_3V3_PA[11]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[11]}]
set_property PACKAGE_PIN A13 [get_ports {SBUS_3V3_PA[12]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[12]}]
set_property PACKAGE_PIN B11 [get_ports {SBUS_3V3_PA[13]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[13]}]
set_property PACKAGE_PIN A11 [get_ports {SBUS_3V3_PA[14]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[14]}]
#set_property PACKAGE_PIN U9 [get_ports {RX}]
#set_property IOSTANDARD LVTTL [get_ports {RX}]
set_property PACKAGE_PIN V9 [get_ports {TX}]
set_property IOSTANDARD LVTTL [get_ports {TX}]
set_property PACKAGE_PIN U8 [get_ports {LED0}]
set_property IOSTANDARD LVTTL [get_ports {LED0}]
#set_property PACKAGE_PIN V7 [get_ports {SD_D2}]
#set_property IOSTANDARD LVTTL [get_ports {SD_D2}]
set_property PACKAGE_PIN U7 [get_ports {LED1}]
set_property IOSTANDARD LVTTL [get_ports {LED1}]
#set_property PACKAGE_PIN V6 [get_ports {SD_D3}]
#set_property IOSTANDARD LVTTL [get_ports {SD_D3}]
set_property PACKAGE_PIN U6 [get_ports {LED2}]
set_property IOSTANDARD LVTTL [get_ports {LED2}]
#set_property PACKAGE_PIN V5 [get_ports {SD_D0}]
#set_property IOSTANDARD LVTTL [get_ports {SD_D0}]
set_property PACKAGE_PIN T8 [get_ports {LED3}]
set_property IOSTANDARD LVTTL [get_ports {LED3}]
#set_property PACKAGE_PIN V4 [get_ports {SD_D1}]
#set_property IOSTANDARD LVTTL [get_ports {SD_D1}]
#set_property PACKAGE_PIN R8 [get_ports {SD_CLK}]
#set_property IOSTANDARD LVTTL [get_ports {SD_CLK}]
#set_property PACKAGE_PIN T5 [get_ports {SD_CMD}]
#set_property IOSTANDARD LVTTL [get_ports {SD_CMD}]
set_property PACKAGE_PIN R7 [get_ports {SBUS_3V3_SIZ[0]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[0]}]
set_property PACKAGE_PIN T4 [get_ports {SBUS_3V3_ASs}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ASs}]
set_property PACKAGE_PIN T6 [get_ports {SBUS_3V3_BGs}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_BGs}]
set_property PACKAGE_PIN R6 [get_ports {SBUS_3V3_BRs}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_BRs}]
set_property PACKAGE_PIN U3 [get_ports {SBUS_3V3_SIZ[1]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[1]}]
set_property PACKAGE_PIN V1 [get_ports {SBUS_3V3_SIZ[2]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[2]}]
set_property PACKAGE_PIN V2 [get_ports {SBUS_3V3_ERRs}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ERRs}]
set_property PACKAGE_PIN U1 [get_ports {SBUS_DATA_OE_LED}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_DATA_OE_LED}]
set_property PACKAGE_PIN U2 [get_ports {SBUS_3V3_RSTs}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_RSTs}]
set_property PACKAGE_PIN T3 [get_ports {SBUS_DATA_OE_LED_2}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_DATA_OE_LED_2}]
set_property PACKAGE_PIN K6 [get_ports {SBUS_3V3_SELs}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SELs}]
set_property PACKAGE_PIN R3 [get_ports {SBUS_3V3_INT1s}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT1s}]
set_property PACKAGE_PIN N6 [get_ports {SBUS_3V3_PPRD}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PPRD}]
set_property PACKAGE_PIN P5 [get_ports {SBUS_OE}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_OE}]
set_property PACKAGE_PIN M6 [get_ports {SBUS_3V3_ACKs[0]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ACKs[0]}]
set_property PACKAGE_PIN N5 [get_ports {SBUS_3V3_INT7s}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_INT7s}]
set_property PACKAGE_PIN L6 [get_ports {SBUS_3V3_ACKs[1]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ACKs[1]}]
set_property PACKAGE_PIN P4 [get_ports {LED4}]
set_property IOSTANDARD LVTTL [get_ports {LED4}]
set_property PACKAGE_PIN P3 [get_ports {LED5}]
set_property IOSTANDARD LVTTL [get_ports {LED5}]
set_property PACKAGE_PIN N4 [get_ports {SBUS_3V3_ACKs[2]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_ACKs[2]}]
set_property PACKAGE_PIN T1 [get_ports {LED6}]
set_property IOSTANDARD LVTTL [get_ports {LED6}]
set_property PACKAGE_PIN M4 [get_ports {SBUS_3V3_PA[15]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[15]}]
set_property PACKAGE_PIN R1 [get_ports {LED7}]
set_property IOSTANDARD LVTTL [get_ports {LED7}]
set_property PACKAGE_PIN M3 [get_ports {SBUS_3V3_PA[17]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[17]}]
set_property PACKAGE_PIN R2 [get_ports {SBUS_3V3_PA[16]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[16]}]
set_property PACKAGE_PIN M2 [get_ports {SBUS_3V3_PA[19]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[19]}]
set_property PACKAGE_PIN P2 [get_ports {SBUS_3V3_PA[18]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[18]}]
set_property PACKAGE_PIN K5 [get_ports {SBUS_3V3_PA[21]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[21]}]
set_property PACKAGE_PIN N2 [get_ports {SBUS_3V3_PA[20]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[20]}]
set_property PACKAGE_PIN L4 [get_ports {SBUS_3V3_PA[23]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[23]}]
set_property PACKAGE_PIN N1 [get_ports {SBUS_3V3_PA[22]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[22]}]
set_property PACKAGE_PIN L3 [get_ports {SBUS_3V3_PA[25]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[25]}]
set_property PACKAGE_PIN M1 [get_ports {SBUS_3V3_PA[24]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[24]}]
set_property PACKAGE_PIN K3 [get_ports {SBUS_3V3_PA[27]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[27]}]
set_property PACKAGE_PIN L1 [get_ports {SBUS_3V3_PA[26]}]
set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_PA[26]}]

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sbus-to-ztex-gateware/sbus_fsm.vhd Normal file
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-- include libraries
-- standard stuff
library IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- For Xilinx IOBUF ; UG953
Library UNISIM;
use UNISIM.vcomponents.all;
library work;
USE work.LedHandlerPkg.all;
USE work.PromPkg.all;
use work.mastrovito_V2_multiplier_parameters.all;
ENTITY SBusFSM is
PORT (
fxclk_in: IN std_logic; -- 48 MHz FX2 clock
-- true SBus signals
SBUS_3V3_CLK : IN STD_LOGIC; -- 16.67..25 MHz SBus Clock
SBUS_3V3_RSTs : IN STD_LOGIC;
SBUS_3V3_SELs : IN STD_LOGIC;
SBUS_3V3_ASs : IN STD_LOGIC;
SBUS_3V3_PPRD : IN STD_LOGIC; -- OUT during extended transfers and on masters; input for masters only during ET
SBUS_3V3_SIZ : IN std_logic_vector(2 downto 0); -- OUT during extended transfers and on masters; input for masters only during ET
SBUS_3V3_ACKs : OUT std_logic_vector(2 downto 0) := (others => 'Z'); -- IN on masters
SBUS_3V3_PA : IN std_logic_vector(27 downto 0); -- OUT during extended transfers and on masters
SBUS_3V3_ERRs : OUT STD_LOGIC := 'Z'; -- IN on masters
SBUS_3V3_D : INOUT std_logic_vector(31 downto 0);
SBUS_3V3_INT1s : OUT STD_LOGIC := 'Z';
SBUS_3V3_INT7s : OUT STD_LOGIC := 'Z';
-- master-only signals
SBUS_3V3_BGs : IN STD_LOGIC; -- bus granted
SBUS_3V3_BRs : OUT STD_LOGIC := 'Z'; -- bus request
-- support signals
SBUS_OE : OUT STD_LOGIC := '1'; -- always off when powered up
-- support leds
SBUS_DATA_OE_LED : OUT std_logic := '0'; -- light during read cycle
SBUS_DATA_OE_LED_2 : OUT std_logic := '0'; -- light during write cycle
-- data leds
LED0 : OUT std_logic := '0';
LED1 : OUT std_logic := '0';
LED2 : OUT std_logic := '0';
LED3 : OUT std_logic := '0';
LED4 : OUT std_logic := '0';
LED5 : OUT std_logic := '0';
LED6 : OUT std_logic := '0';
LED7 : OUT std_logic := '0';
-- UART
TX : OUT std_logic := 'Z'
);
-- SIZ[2..0] is positive true
CONSTANT SIZ_WORD : std_logic_vector(2 downto 0):= "000";
CONSTANT SIZ_BYTE : std_logic_vector(2 downto 0):= "001";
CONSTANT SIZ_HWORD : std_logic_vector(2 downto 0):= "010";
CONSTANT SIZ_EXT : std_logic_vector(2 downto 0):= "011";
CONSTANT SIZ_BURST4 : std_logic_vector(2 downto 0):= "100";
CONSTANT SIZ_BURST8 : std_logic_vector(2 downto 0):= "101";
CONSTANT SIZ_BURST16 : std_logic_vector(2 downto 0):= "110";
CONSTANT SIZ_BURST2 : std_logic_vector(2 downto 0):= "111";
-- ACKs[2-0] is negative true
CONSTANT ACK_DISABLED : std_logic_vector(2 downto 0):= "ZZZ";
CONSTANT ACK_IDLE : std_logic_vector(2 downto 0):= "111";
CONSTANT ACK_ERR : std_logic_vector(2 downto 0):= "110";
CONSTANT ACK_BYTE : std_logic_vector(2 downto 0):= "101";
CONSTANT ACK_RERUN : std_logic_vector(2 downto 0):= "100";
CONSTANT ACK_WORD : std_logic_vector(2 downto 0):= "011";
CONSTANT ACK_DWORD : std_logic_vector(2 downto 0):= "010";
CONSTANT ACK_HWORD : std_logic_vector(2 downto 0):= "001";
CONSTANT ACK_RESV : std_logic_vector(2 downto 0):= "000";
-- ADDR RANGES ; (27 downto 9) so 19 bits
CONSTANT ROM_ADDR_PFX : std_logic_vector(18 downto 0) := "0000000000000000000";
CONSTANT REG_ADDR_PFX : std_logic_vector(18 downto 0) := "0000000000000000001";
-- OFFSET to REGS; (8 downto 0) so 9 bits
CONSTANT REG_OFFSET_LED : std_logic_vector(8 downto 0) := conv_std_logic_vector( 0, 9);
-- starts at 64 so we can do 64 bytes burst (see address wrapping)
CONSTANT REG_INDEX_GCM_H1 : integer := 0;
CONSTANT REG_INDEX_GCM_H2 : integer := 1;
CONSTANT REG_INDEX_GCM_H3 : integer := 2;
CONSTANT REG_INDEX_GCM_H4 : integer := 3;
CONSTANT REG_INDEX_GCM_C1 : integer := 4;
CONSTANT REG_INDEX_GCM_C2 : integer := 5;
CONSTANT REG_INDEX_GCM_C3 : integer := 6;
CONSTANT REG_INDEX_GCM_C4 : integer := 7;
CONSTANT REG_INDEX_GCM_INPUT1 : integer := 8;
CONSTANT REG_INDEX_GCM_INPUT2 : integer := 9;
CONSTANT REG_INDEX_GCM_INPUT3 : integer := 10;
CONSTANT REG_INDEX_GCM_INPUT4 : integer := 11;
CONSTANT REG_INDEX_GCM_INPUT5 : integer := 12; -- placeholder
CONSTANT REG_INDEX_GCM_INPUT6 : integer := 13; -- placeholder
CONSTANT REG_INDEX_GCM_INPUT7 : integer := 14; -- placeholder
CONSTANT REG_INDEX_GCM_INPUT8 : integer := 15; -- placeholder
CONSTANT REG_OFFSET_GCM_H1 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H1*4, 9);
CONSTANT REG_OFFSET_GCM_H2 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H2*4, 9);
CONSTANT REG_OFFSET_GCM_H3 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H3*4, 9);
CONSTANT REG_OFFSET_GCM_H4 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H4*4, 9);
CONSTANT REG_OFFSET_GCM_C1 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C1*4, 9);
CONSTANT REG_OFFSET_GCM_C2 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C2*4, 9);
CONSTANT REG_OFFSET_GCM_C3 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C3*4, 9);
CONSTANT REG_OFFSET_GCM_C4 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C4*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT1 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT1*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT2 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT2*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT3 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT3*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT4 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT4*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT5 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT5*4, 9); -- placeholder
CONSTANT REG_OFFSET_GCM_INPUT6 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT6*4, 9); -- placeholder
CONSTANT REG_OFFSET_GCM_INPUT7 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT7*4, 9); -- placeholder
CONSTANT REG_OFFSET_GCM_INPUT8 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT8*4, 9); -- placeholder
constant c_CLKS_PER_BIT : integer := 417; -- 48M/115200
-- constant c_CLKS_PER_BIT : integer := 50; -- 5.76M/115200
END ENTITY;
ARCHITECTURE RTL OF SBusFSM IS
TYPE SBus_States IS (
-- after reset, move to Idle
SBus_Start,
-- waiting, all outputs should be set Z
-- includes the detection logic for the next cycle
-- also capture PA immediately (useful for address wrapping,
-- might become useful for extended transfer)
SBus_Idle,
-- cycle during which ACK is IDLE to end SBus Cycle
-- also check for deasserting of AS
SBus_Slave_Ack_Reg_Write,
-- cycle after ACK is idle, everything goes back to Z before Idle
-- also check for deasserting of AS
SBus_Slave_Ack_Reg_Write_Final,
-- cycle after ACK is idle, everything goes back to Z before Idle
-- we have already seen the deasserting of AS
SBus_Slave_Ack_Reg_Write_Final_Idle,
-- cycle(s) with data acquired from the bus & ACK of the next acquisition
-- between 1 and 16 words (so 1 to 16 cycles in the state)
SBus_Slave_Ack_Reg_Write_Burst,
-- cycle we put the data on the bus when reading from Prom
-- also ACK goes to idle
-- byte-wide
SBus_Slave_Ack_Read_Prom_Byte,
-- cycle we put the data on the bus when reading from Prom
-- also ACK goes to idle
-- half-word-wide
SBus_Slave_Ack_Read_Prom_HWord,
-- cycle(s) we put the data on the bus when reading from Prom
-- also ACK the next word we will put, or goes to idle for last
-- word-wide, burst from 1 to 16
SBus_Slave_Ack_Read_Prom_Burst,
-- cycle we put the data on the bus when reading from registers
-- also ACK goes to idle
-- byte-wide
SBus_Slave_Ack_Read_Reg_Byte,
-- cycle we put the data on the bus when reading from registers
-- also ACK goes to idle
-- half-word-wide
SBus_Slave_Ack_Read_Reg_HWord,
-- cycle(s) we put the data on the bus when reading from registers
-- also ACK the next word we will put, or goes to idle for last
-- word-wide, burst from 1 to 16
SBus_Slave_Ack_Read_Reg_Burst,
-- last cycle where the master read our data from the bus
-- everything goes to Z before Idle
SBus_Slave_Do_Read,
-- delay cycle to assert late error
SBus_Slave_Delay_Error,
-- cycle where master detect the error (ACK or late)
-- everything goes to Z before Idle
SBus_Slave_Error,
SBus_Slave_Heartbeat);
TYPE Uart_States IS ( UART_IDLE, UART_WAITING );
SIGNAL State : SBus_States := SBus_Start;
SIGNAL Uart_State : Uart_States := UART_IDLE;
SIGNAL LED_RESET: std_logic := '0';
SIGNAL LED_DATA: std_logic_vector(31 downto 0) := (others => '0');
signal DATA_T : std_logic := '1'; -- I/O control for IOBUF, default to input
signal BUF_DATA_I, BUF_DATA_O : std_logic_vector(31 downto 0); --buffers for data from/to
SIGNAL p_addr : std_logic_vector(6 downto 0) := "1111111"; -- addr lines to prom
SIGNAL p_data : std_logic_vector(31 downto 0); -- data lines to prom
-- signal uart_clk : std_logic; -- 5.76 MHz clock for FIFO write & UART
signal fifo_rst : STD_LOGIC := '1'; -- start in reset mode
signal fifo_din : STD_LOGIC_VECTOR ( 7 downto 0 );
signal fifo_wr_en : STD_LOGIC;
signal fifo_rd_en : STD_LOGIC;
signal fifo_dout : STD_LOGIC_VECTOR ( 7 downto 0 );
signal fifo_full : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal r_TX_DV : std_logic := '0';
signal w_TX_DONE : std_logic;
signal r_TX_BYTE : std_logic_vector(7 downto 0) := (others => '0');
-- SIGNAL LIFE_COUNTER48 : natural range 0 to 48000000 := 300;
SIGNAL LIFE_COUNTER25 : natural range 0 to 25000000 := 300;
SIGNAL RES_COUNTER : natural range 0 to 5 := 5;
-- counter to wait 12s before enabling SBus signals, without this the SS20 won't POST reliably...
-- this means a need to probe-sbus from the PROM to find the board
SIGNAL OE_COUNTER : natural range 0 to 960000000 := 960000000;
type GCM_REGISTERS_TYPE is array(0 to 15) of std_logic_vector(31 downto 0);
SIGNAL GCM_REGISTERS : GCM_REGISTERS_TYPE;
pure function REG_OFFSET_IS_GCMINPUT(value : in std_logic_vector(8 downto 0)) return boolean is
begin
return (REG_OFFSET_GCM_INPUT1 = value) OR
(REG_OFFSET_GCM_INPUT2 = value) OR
(REG_OFFSET_GCM_INPUT3 = value) OR
(REG_OFFSET_GCM_INPUT4 = value);
end function;
pure function REG_OFFSET_IS_GCMH (value : in std_logic_vector(8 downto 0)) return boolean is
begin
return (REG_OFFSET_GCM_H1 = value) OR
(REG_OFFSET_GCM_H2 = value) OR
(REG_OFFSET_GCM_H3 = value) OR
(REG_OFFSET_GCM_H4 = value);
end function;
pure function REG_OFFSET_IS_GCMC (value : in std_logic_vector(8 downto 0)) return boolean is
begin
return (REG_OFFSET_GCM_C1 = value) OR
(REG_OFFSET_GCM_C2 = value) OR
(REG_OFFSET_GCM_C3 = value) OR
(REG_OFFSET_GCM_C4 = value);
end function;
pure function REG_OFFSET_IS_ANYGCM (value : in std_logic_vector(8 downto 0)) return boolean is
begin
return REG_OFFSET_IS_GCMINPUT(value) or REG_OFFSET_IS_GCMH(value) or REG_OFFSET_IS_GCMC(value);
end function;
pure function SIZ_IS_WORD(value : in std_logic_vector(2 downto 0)) return boolean is
begin
return (SIZ_WORD = value) OR
(SIZ_BURST2 = value) OR
(SIZ_BURST4 = value) OR
(SIZ_BURST8 = value) OR
(SIZ_BURST16 = value);
end function;
pure function SIZ_TO_BURSTSIZE(value : in std_logic_vector(2 downto 0)) return integer is
begin
case value is
WHEN SIZ_WORD => return 1;
WHEN SIZ_BURST2 => return 2;
WHEN SIZ_BURST4 => return 4;
WHEN SIZ_BURST8 => return 8;
WHEN SIZ_BURST16 => return 16;
WHEN OTHERS => return 1; -- should not happen
end case;
end function;
pure function INDEX_WITH_WRAP(counter: in integer;
limit: in integer;
value : in std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case limit is
WHEN 1 => return value(3 downto 0);
WHEN 2 => return value(3 downto 1) & conv_std_logic_vector(conv_integer(value(0)) +counter,1);
WHEN 4 => return value(3 downto 2) & conv_std_logic_vector(conv_integer(value(1 downto 0))+counter,2);
WHEN 8 => return value(3 downto 3) & conv_std_logic_vector(conv_integer(value(2 downto 0))+counter,3);
WHEN 16 => return conv_std_logic_vector(conv_integer(value(3 downto 0))+counter,4);
WHEN others => return value(3 downto 0); -- should not happen
end case;
end function;
--COMPONENT LedHandler
--PORT( l_ifclk: IN std_logic; -- 48 MHz interface clock
-- l_LED_RESET: IN std_logic := '0';
-- l_LED_DATA: IN std_logic_vector(31 downto 0) := (others => '0');
-- l_LED0 : OUT std_logic := '0';
-- l_LED1 : OUT std_logic := '0';
-- l_LED2 : OUT std_logic := '0';
-- l_LED3 : OUT std_logic := '0');
--END COMPONENT;
COMPONENT LedHandler
PORT( l_ifclk: IN std_logic; -- 48 MHz interface clock
l_LED_RESET: IN std_logic := '0';
l_LED_DATA: IN std_logic_vector(31 downto 0) := (others => '0');
l_LED0 : OUT std_logic := '0';
l_LED1 : OUT std_logic := '0';
l_LED2 : OUT std_logic := '0';
l_LED3 : OUT std_logic := '0';
l_LED4 : OUT std_logic := '0';
l_LED5 : OUT std_logic := '0';
l_LED6 : OUT std_logic := '0';
l_LED7 : OUT std_logic := '0');
END COMPONENT;
COMPONENT Prom
GENERIC(
addr_width : integer := 128; -- store 128 elements (512 bytes)
addr_bits : integer := 7; -- required bits to store 128 elements
data_width : integer := 32 -- each element has 32-bits
);
PORT(
addr : IN std_logic_vector(addr_bits-1 downto 0);
data : OUT std_logic_vector(data_width-1 downto 0));
END COMPONENT;
COMPONENT mastrovito_V2_multiplication
PORT(
a : IN std_logic_vector(M-1 downto 0);
b : IN std_logic_vector(M-1 downto 0);
c : OUT std_logic_vector(M-1 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL mas_a : std_logic_vector(M-1 downto 0) := (others=>'0');
SIGNAL mas_b : std_logic_vector(M-1 downto 0) := (others=>'0');
--Outputs
SIGNAL mas_c : std_logic_vector(M-1 downto 0);
function reverse_bit_in_byte (a: in std_logic_vector(31 downto 0))
return std_logic_vector is
variable t: std_logic_vector(31 downto 0);
begin
t( 7 downto 0) := a( 0)&a( 1)&a( 2)&a( 3)&a( 4)&a( 5)&a( 6)&a( 7);
t(15 downto 8) := a( 8)&a( 9)&a(10)&a(11)&a(12)&a(13)&a(14)&a(15);
t(23 downto 16) := a(16)&a(17)&a(18)&a(19)&a(20)&a(21)&a(22)&a(23);
t(31 downto 24) := a(24)&a(25)&a(26)&a(27)&a(28)&a(29)&a(30)&a(31);
return t;
end;
component fifo_generator_0 is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end component;
component uart_tx is
generic (
g_CLKS_PER_BIT : integer := 417 -- Needs to be set correctly
);
port (
i_clk : in std_logic;
i_tx_dv : in std_logic;
i_tx_byte : in std_logic_vector(7 downto 0);
o_tx_active : out std_logic;
o_tx_serial : out std_logic;
o_tx_done : out std_logic
);
end component uart_tx;
component clk_wiz_0 is
port(clk_in1 : in std_logic;
clk_out1 : out std_logic);
end component clk_wiz_0;
PROCEDURE SBus_Set_Default(
signal SBUS_3V3_ACKs : OUT std_logic_vector(2 downto 0);
signal SBUS_3V3_ERRs : OUT STD_LOGIC;
signal SBUS_3V3_INT1s : OUT STD_LOGIC;
signal SBUS_3V3_INT7s : OUT STD_LOGIC;
-- support leds
signal SBUS_DATA_OE_LED : OUT std_logic; -- light during read cycle
signal SBUS_DATA_OE_LED_2 : OUT std_logic; -- light during write cycle)
-- ROM
signal p_addr : OUT std_logic_vector(6 downto 0); -- TODO: how to reference the add_bits from PROM ?
-- Data buffers
signal DATA_T : OUT std_logic; -- I/O control for IOBUF
-- Data LEDS
signal LED_RESET: OUT std_logic -- force LED cycling from start
) IS
BEGIN
SBUS_DATA_OE_LED <= '0'; -- off
SBUS_DATA_OE_LED_2 <= '0'; -- off
SBUS_3V3_ACKs <= ACK_DISABLED; -- no drive
SBUS_3V3_ERRs <= 'Z'; -- idle
SBUS_3V3_INT1s <= 'Z';
SBUS_3V3_INT7s <= 'Z';
p_addr <= "1111111"; -- look-up last element, all-0
DATA_T <= '1'; -- set buffer as input
LED_RESET <= '0'; -- let data LEDs do their thing
END PROCEDURE;
BEGIN
GENDATABUF: for i IN 0 to 31 generate
IOBx : IOBUF
GENERIC MAP(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
PORT MAP (
O => BUF_DATA_I(i), -- Buffer output (warning - data coming from SBUS so I)
IO => SBUS_3V3_D(i), -- Buffer INOUT PORT (connect directly to top-level PORT)
I => BUF_DATA_O(i), -- Buffer input (warning - data going to SBUS so O)
T => DATA_T -- 3-state enable input, high=input, low=output
);
end generate GENDATABUF;
--label_led_handler: LedHandler PORT MAP( l_ifclk => SBUS_3V3_CLK, l_LED_RESET => LED_RESET, l_LED_DATA => LED_DATA, l_LED0 => LED0, l_LED1 => LED1, l_LED2 => LED2, l_LED3 => LED3 );
label_led_handler: LedHandler PORT MAP( l_ifclk => SBUS_3V3_CLK, l_LED_RESET => LED_RESET, l_LED_DATA => LED_DATA, l_LED0 => LED0, l_LED1 => LED1, l_LED2 => LED2, l_LED3 => LED3,
l_LED4 => LED4, l_LED5 => LED5, l_LED6 => LED6, l_LED7 => LED7);
label_prom: Prom PORT MAP (addr => p_addr, data => p_data);
label_mas: mastrovito_V2_multiplication PORT MAP( a => mas_a, b => mas_b, c => mas_c );
label_fifo: fifo_generator_0 port map(rst => fifo_rst, wr_clk => SBUS_3V3_CLK, rd_clk => fxclk_in,
din => fifo_din, wr_en => fifo_wr_en, rd_en => fifo_rd_en,
dout => fifo_dout, full => fifo_full, empty => fifo_empty);
-- label_clk_wiz: clk_wiz_0 port map(clk_out1 => uart_clk, clk_in1 => fxclk_in);
label_uart : uart_tx
generic map (
g_CLKS_PER_BIT => c_CLKS_PER_BIT
)
port map (
i_clk => fxclk_in,
i_tx_dv => r_TX_DV,
i_tx_byte => r_TX_BYTE,
o_tx_active => open,
o_tx_serial => TX,
o_tx_done => w_TX_DONE
);
PROCESS (SBUS_3V3_CLK, SBUS_3V3_RSTs)
variable do_gcm : boolean := false;
variable last_pa : std_logic_vector(27 downto 0) := (others => '0');
variable BURST_COUNTER : integer range 0 to 15 := 0;
variable BURST_LIMIT : integer range 1 to 16 := 1;
variable BURST_INDEX : integer range 0 to 15;
BEGIN
IF (SBUS_3V3_RSTs = '0') THEN
State <= SBus_Start;
fifo_rst <= '1';
ELSIF RISING_EDGE(SBUS_3V3_CLK) THEN
fifo_rst <= '0';
fifo_wr_en <= '0';
LIFE_COUNTER25 <= LIFE_COUNTER25 - 1;
CASE State IS
WHEN SBus_Idle =>
IF (LIFE_COUNTER25 <= 200000) THEN
LIFE_COUNTER25 <= 25000000;
fifo_wr_en <= '1';
-- fifo_din <= x"40"; -- "@"
fifo_din <= b"01" & SBUS_3V3_SELs & SBUS_3V3_ASs & SBUS_3V3_PPRD & SBUS_3V3_SIZ;
State <= SBus_Slave_Heartbeat;
-- Anything pointing to SBus_Idle should SBus_Set_Default
-- SBus_Set_Default(SBUS_3V3_ACKs, SBUS_3V3_ERRs, SBUS_3V3_INT1s, SBUS_3V3_INT7s,
-- SBUS_DATA_OE_LED, SBUS_DATA_OE_LED_2,
-- p_addr, DATA_T, LED_RESET);
-- READ READ READ --
ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND SIZ_IS_WORD(SBUS_3V3_SIZ) AND SBUS_3V3_PPRD='1' THEN
fifo_wr_en <= '1'; fifo_din <= x"41"; -- "A"
last_pa := SBUS_3V3_PA;
SBUS_DATA_OE_LED <= '1';
BURST_COUNTER := 0;
BURST_LIMIT := SIZ_TO_BURSTSIZE(SBUS_3V3_SIZ);
IF ((last_pa(27 downto 9) = ROM_ADDR_PFX) AND (last_pa(1 downto 0) = "00")) then
-- 32 bits read from aligned memory IN PROM space ------------------------------------
SBUS_3V3_ACKs <= ACK_WORD;
SBUS_3V3_ERRs <= '1'; -- no late error
-- word address goes to the p_addr lines
p_addr <= last_pa(8 downto 2);
State <= SBus_Slave_Ack_Read_Prom_Burst;
ELSIF ((last_pa(27 downto 9) = REG_ADDR_PFX) AND REG_OFFSET_IS_ANYGCM(last_pa(8 downto 0))) then
-- 32 bits read from aligned memory IN REG space ------------------------------------
SBUS_3V3_ACKs <= ACK_WORD;
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Ack_Read_Reg_Burst;
ELSE
SBUS_3V3_ACKs <= ACK_ERR;
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Error;
END IF;
ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND SBUS_3V3_SIZ = SIZ_BYTE AND SBUS_3V3_PPRD='1' THEN
fifo_wr_en <= '1'; fifo_din <= x"42"; -- "B"
last_pa := SBUS_3V3_PA;
SBUS_DATA_OE_LED <= '1';
IF (last_pa(27 downto 9) = ROM_ADDR_PFX) then
-- 8 bits read from memory IN PROM space ------------------------------------
SBUS_3V3_ACKs <= ACK_BYTE;
SBUS_3V3_ERRs <= '1'; -- no late error
-- word address goes to the p_addr lines
p_addr <= last_pa(8 downto 2);
State <= SBus_Slave_Ack_Read_Prom_Byte;
ELSE
SBUS_3V3_ACKs <= ACK_ERR;
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Error;
END IF;
ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND SBUS_3V3_SIZ = SIZ_HWORD AND SBUS_3V3_PPRD='1' THEN
fifo_wr_en <= '1'; fifo_din <= x"43"; -- "C"
last_pa := SBUS_3V3_PA;
SBUS_DATA_OE_LED <= '1';
IF ((last_pa(27 downto 9) = ROM_ADDR_PFX) and (last_pa(0) = '0')) then
-- 16 bits read from memory IN PROM space ------------------------------------
SBUS_3V3_ACKs <= ACK_HWORD;
SBUS_3V3_ERRs <= '1'; -- no late error
-- word address goes to the p_addr lines
p_addr <= last_pa(8 downto 2);
State <= SBus_Slave_Ack_Read_Prom_HWord;
ELSE
SBUS_3V3_ACKs <= ACK_ERR;
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Error;
END IF;
-- WRITE WRITE WRITE --
ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND SIZ_IS_WORD(SBUS_3V3_SIZ) AND SBUS_3V3_PPRD='0' THEN
fifo_wr_en <= '1'; fifo_din <= x"44"; -- "D"
last_pa := SBUS_3V3_PA;
SBUS_DATA_OE_LED_2 <= '1';
BURST_COUNTER := 0;
BURST_LIMIT := SIZ_TO_BURSTSIZE(SBUS_3V3_SIZ);
IF ((last_pa(27 downto 9) = REG_ADDR_PFX) and (last_pa(8 downto 0) = REG_OFFSET_LED)) then
-- 32 bits write to LED register ------------------------------------
if (SBUS_3V3_SIZ = SIZ_WORD) THEN
LED_RESET <= '1'; -- reset led cycle
--DATA_T <= '1'; -- set buffer as input
LED_DATA <= BUF_DATA_I; -- display data
SBUS_3V3_ACKs <= ACK_WORD; -- acknowledge the Word
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Ack_Reg_Write;
ELSE
SBUS_3V3_ACKs <= ACK_ERR;
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Error;
END IF;
ELSIF ((last_pa(27 downto 9) = REG_ADDR_PFX) and REG_OFFSET_IS_ANYGCM(last_pa(8 downto 0))) then
-- 32 bits write to GCM register ------------------------------------
SBUS_3V3_ACKs <= ACK_WORD; -- acknowledge the Word
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Ack_Reg_Write_Burst;
ELSE
SBUS_3V3_ACKs <= ACK_ERR; -- unsupported address, signal error
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Error;
END IF;
ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND SBUS_3V3_SIZ = SIZ_BYTE AND SBUS_3V3_PPRD='0' THEN
fifo_wr_en <= '1'; fifo_din <= x"45"; -- "E"
last_pa := SBUS_3V3_PA;
SBUS_DATA_OE_LED_2 <= '1';
IF ((last_pa(27 downto 9) = REG_ADDR_PFX) and (last_pa(8 downto 2) = REG_OFFSET_LED(8 downto 2))) then
-- 8 bits write to LED register ------------------------------------
LED_RESET <= '1'; -- reset led cycle
--DATA_T <= '1'; -- set buffer as input
CASE last_pa(1 downto 0) IS
WHEN "00" =>
LED_DATA(31 downto 24) <= BUF_DATA_I(31 downto 24);
WHEN "01" =>
LED_DATA(23 downto 16) <= BUF_DATA_I(31 downto 24);
WHEN "10" =>
LED_DATA(15 downto 8) <= BUF_DATA_I(31 downto 24);
WHEN "11" =>
LED_DATA(7 downto 0) <= BUF_DATA_I(31 downto 24);
WHEN OTHERS =>
-- TODO: FIXME, probably should generate an error
END CASE;
SBUS_3V3_ACKs <= ACK_BYTE; -- acknowledge the Byte
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Ack_Reg_Write;
ELSE
SBUS_3V3_ACKs <= ACK_ERR; -- unsupported address, signal error
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Error;
END IF;
-- ERROR ERROR ERROR
ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND SBUS_3V3_SIZ /= SIZ_WORD THEN
fifo_wr_en <= '1'; fifo_din <= x"58"; -- "X"
SBUS_3V3_ACKs <= ACK_ERR; -- unsupported config, signal error
SBUS_3V3_ERRs <= '1'; -- no late error
State <= SBus_Slave_Error;
END IF;
-- -- -- --
WHEN SBus_Slave_Ack_Reg_Write =>
fifo_wr_en <= '1'; fifo_din <= x"45"; -- "E"
SBUS_3V3_ACKs <= ACK_IDLE; -- need one cycle of idle
IF (do_gcm) THEN
mas_a(31 downto 0) <= reverse_bit_in_byte(GCM_REGISTERS(8) xor GCM_REGISTERS(4));
mas_a(63 downto 32) <= reverse_bit_in_byte(GCM_REGISTERS(9) xor GCM_REGISTERS(5));
mas_a(95 downto 64) <= reverse_bit_in_byte(GCM_REGISTERS(10) xor GCM_REGISTERS(6));
mas_a(127 downto 96) <= reverse_bit_in_byte(GCM_REGISTERS(11) xor GCM_REGISTERS(7));
mas_b(31 downto 0) <= reverse_bit_in_byte(GCM_REGISTERS(0));
mas_b(63 downto 32) <= reverse_bit_in_byte(GCM_REGISTERS(1));
mas_b(95 downto 64) <= reverse_bit_in_byte(GCM_REGISTERS(2));
mas_b(127 downto 96) <= reverse_bit_in_byte(GCM_REGISTERS(3));
END IF;
IF (SBUS_3V3_ASs='1') THEN
State <= SBus_Slave_Ack_Reg_Write_Final_Idle;
ELSE
State <= SBus_Slave_Ack_Reg_Write_Final;
END IF;
WHEN SBus_Slave_Ack_Reg_Write_Final =>
fifo_wr_en <= '1'; fifo_din <= x"46"; -- "F"
SBus_Set_Default(SBUS_3V3_ACKs, SBUS_3V3_ERRs, SBUS_3V3_INT1s, SBUS_3V3_INT7s,
SBUS_DATA_OE_LED, SBUS_DATA_OE_LED_2,
p_addr, DATA_T, LED_RESET);
IF (do_gcm) THEN
do_gcm := false;
GCM_REGISTERS(4) <= reverse_bit_in_byte(mas_c(31 downto 0));
GCM_REGISTERS(5) <= reverse_bit_in_byte(mas_c(63 downto 32));
GCM_REGISTERS(6) <= reverse_bit_in_byte(mas_c(95 downto 64));
GCM_REGISTERS(7) <= reverse_bit_in_byte(mas_c(127 downto 96));
END IF;
IF (SBUS_3V3_ASs='1') THEN
State <= SBus_Idle;
END IF;
WHEN SBus_Slave_Ack_Reg_Write_Final_Idle =>
fifo_wr_en <= '1'; fifo_din <= x"47"; -- "G"
SBus_Set_Default(SBUS_3V3_ACKs, SBUS_3V3_ERRs, SBUS_3V3_INT1s, SBUS_3V3_INT7s,
SBUS_DATA_OE_LED, SBUS_DATA_OE_LED_2,
p_addr, DATA_T, LED_RESET);
IF (do_gcm) THEN
do_gcm := false;
GCM_REGISTERS(4) <= reverse_bit_in_byte(mas_c(31 downto 0));
GCM_REGISTERS(5) <= reverse_bit_in_byte(mas_c(63 downto 32));
GCM_REGISTERS(6) <= reverse_bit_in_byte(mas_c(95 downto 64));
GCM_REGISTERS(7) <= reverse_bit_in_byte(mas_c(127 downto 96));
END IF;
State <= SBus_Idle;
WHEN SBus_Slave_Ack_Reg_Write_Burst =>
fifo_wr_en <= '1'; fifo_din <= x"48"; -- "H"
BURST_INDEX := conv_integer(INDEX_WITH_WRAP(BURST_COUNTER, BURST_LIMIT, last_pa(5 downto 2)));
GCM_REGISTERS(BURST_INDEX) <= BUF_DATA_I;
SBUS_3V3_ACKs <= ACK_WORD; -- acknowledge the Word
IF (BURST_INDEX = REG_INDEX_GCM_INPUT4) THEN
do_gcm := true;
END IF;
if (BURST_COUNTER = (BURST_LIMIT-1)) THEN
State <= SBus_Slave_Ack_Reg_Write;
ELSE
BURST_COUNTER := BURST_COUNTER + 1;
END IF;
WHEN SBus_Slave_Ack_Read_Prom_Burst =>
fifo_wr_en <= '1'; fifo_din <= x"49"; -- "I"
DATA_T <= '0'; -- set buffer as output
-- put data from PROM on the bus
BUF_DATA_O <= p_data; -- address set in previous cycle
BURST_INDEX := conv_integer(INDEX_WITH_WRAP((BURST_COUNTER + 1), BURST_LIMIT, last_pa(5 downto 2)));
p_addr <= last_pa(8 downto 6) & conv_std_logic_vector(BURST_INDEX,4); -- for next cycle
if (BURST_COUNTER = (BURST_LIMIT-1)) then
SBUS_3V3_ACKs <= ACK_IDLE;
State <= SBus_Slave_Do_Read;
else
SBUS_3V3_ACKs <= ACK_WORD;
BURST_COUNTER := BURST_COUNTER + 1;
end if;
WHEN SBus_Slave_Ack_Read_Reg_Burst =>
fifo_wr_en <= '1'; fifo_din <= x"4A"; -- "J"
DATA_T <= '0'; -- set buffer as output
BURST_INDEX := conv_integer(INDEX_WITH_WRAP(BURST_COUNTER, BURST_LIMIT, last_pa(5 downto 2)));
BUF_DATA_O <= GCM_REGISTERS(BURST_INDEX);
if (BURST_COUNTER = (BURST_LIMIT-1)) then
SBUS_3V3_ACKs <= ACK_IDLE;
State <= SBus_Slave_Do_Read;
else
SBUS_3V3_ACKs <= ACK_WORD;
BURST_COUNTER := BURST_COUNTER + 1;
end if;
WHEN SBus_Slave_Do_Read => -- this is the (last) cycle IN which the master read
fifo_wr_en <= '1'; fifo_din <= x"4B"; -- "K"
SBus_Set_Default(SBUS_3V3_ACKs, SBUS_3V3_ERRs, SBUS_3V3_INT1s, SBUS_3V3_INT7s,
SBUS_DATA_OE_LED, SBUS_DATA_OE_LED_2,
p_addr, DATA_T, LED_RESET);
IF (SBUS_3V3_ASs='1') THEN
State <= SBus_Idle;
END IF;
WHEN SBus_Slave_Ack_Read_Prom_Byte =>
fifo_wr_en <= '1'; fifo_din <= x"4C"; -- "L"
IF (last_pa(27 downto 9) = ROM_ADDR_PFX) then -- do we need to re-test ?
SBUS_3V3_ACKs <= ACK_IDLE;
-- put data from PROM on the bus
DATA_T <= '0'; -- set buffer as output
CASE last_pa(1 downto 0) IS
WHEN "00" =>
BUF_DATA_O(31 downto 24) <= p_data(31 downto 24);
BUF_DATA_O(23 downto 0) <= (others => '0');
WHEN "01" =>
BUF_DATA_O(31 downto 24) <= p_data(23 downto 16);
BUF_DATA_O(23 downto 0) <= (others => '0');
WHEN "10" =>
BUF_DATA_O(31 downto 24) <= p_data(15 downto 8);
BUF_DATA_O(23 downto 0) <= (others => '0');
WHEN "11" =>
BUF_DATA_O(31 downto 24) <= p_data(7 downto 0);
BUF_DATA_O(23 downto 0) <= (others => '0');
WHEN OTHERS =>
BUF_DATA_O(31 downto 0) <= (others => '0'); -- TODO: FIXME, probably should generate an error
END CASE;
State <= SBus_Slave_Do_Read;
ELSE
SBUS_3V3_ACKs <= ACK_IDLE;
State <= SBus_Slave_Delay_Error;
END IF;
WHEN SBus_Slave_Ack_Read_Prom_HWord =>
fifo_wr_en <= '1'; fifo_din <= x"4D"; -- "M"
IF ((last_pa(27 downto 9) = ROM_ADDR_PFX) and (last_pa(0) = '0'))then -- do we need to re-test ?
SBUS_3V3_ACKs <= ACK_IDLE;
-- put data from PROM on the bus
DATA_T <= '0'; -- set buffer as output
CASE last_pa(1) IS
WHEN '0' =>
BUF_DATA_O(31 downto 16) <= p_data(31 downto 16);
BUF_DATA_O(15 downto 0) <= (others => '0');
WHEN '1' =>
BUF_DATA_O(31 downto 16) <= p_data(15 downto 0);
BUF_DATA_O(15 downto 0) <= (others => '0');
WHEN OTHERS =>
BUF_DATA_O(31 downto 0) <= (others => '0'); -- TODO: FIXME, probably should generate an error
END CASE;
State <= SBus_Slave_Do_Read;
ELSE
SBUS_3V3_ACKs <= ACK_IDLE;
State <= SBus_Slave_Delay_Error;
END IF;
WHEN SBus_Slave_Error =>
fifo_wr_en <= '1'; fifo_din <= x"59"; -- "Y"
SBus_Set_Default(SBUS_3V3_ACKs, SBUS_3V3_ERRs, SBUS_3V3_INT1s, SBUS_3V3_INT7s,
SBUS_DATA_OE_LED, SBUS_DATA_OE_LED_2,
p_addr, DATA_T, LED_RESET);
IF (SBUS_3V3_ASs='1') THEN
State <= SBus_Idle;
END IF;
WHEN SBus_Slave_Delay_Error =>
fifo_wr_en <= '1'; fifo_din <= x"5A"; -- "Z"
SBUS_3V3_ERRs <= '0'; -- two cycles after ACK
State <= SBus_Slave_Error;
WHEN SBus_Slave_Heartbeat =>
State <= SBus_Idle;
WHEN OTHERS => -- include SBus_Start
SBus_Set_Default(SBUS_3V3_ACKs, SBUS_3V3_ERRs, SBUS_3V3_INT1s, SBUS_3V3_INT7s,
SBUS_DATA_OE_LED, SBUS_DATA_OE_LED_2,
p_addr, DATA_T, LED_RESET);
-- SBUS_OE <= '0'; -- enable all signals
if SBUS_3V3_RSTs = '1' then
IF (RES_COUNTER = 0) THEN
fifo_wr_en <= '1'; fifo_din <= x"2A"; -- "*"
State <= SBus_Idle;
ELSE
RES_COUNTER <= RES_COUNTER - 1;
END IF;
else
RES_COUNTER <= 5;
END IF;
END CASE;
END IF;
END PROCESS;
process(fxclk_in, fifo_rst)
BEGIN
if (fifo_rst = '1') THEN
Uart_State <= UART_IDLE;
ELSIF RISING_EDGE(fxclk_in) THEN
r_TX_DV <= '0';
fifo_rd_en <= '0';
-- LIFE_COUNTER48 <= LIFE_COUNTER48 - 1;
CASE Uart_State IS
WHEN UART_IDLE =>
IF (fifo_empty = '0') THEN
r_TX_DV <= '1';
fifo_rd_en <= '1';
r_TX_BYTE <= fifo_dout;
Uart_State <= UART_WAITING;
-- ELSIF (LIFE_COUNTER48 <= 500000) THEN
-- LIFE_COUNTER48 <= 48000000;
-- r_TX_DV <= '1';
-- CASE State IS
-- When SBus_Start => r_TX_BYTE <= x"61"; -- "a"
-- When SBus_Idle => r_TX_BYTE <= x"62"; -- "b"
-- When SBus_Slave_Ack_Reg_Write => r_TX_BYTE <= x"63"; -- "c"
-- When SBus_Slave_Ack_Reg_Write_Final => r_TX_BYTE <= x"64"; -- "d"
-- When SBus_Slave_Ack_Reg_Write_Final_Idle => r_TX_BYTE <= x"65"; -- "d"
-- When SBus_Slave_Ack_Reg_Write_Burst => r_TX_BYTE <= x"66"; -- "f"
-- When SBus_Slave_Ack_Read_Prom_Byte => r_TX_BYTE <= x"67"; -- "g"
-- When SBus_Slave_Ack_Read_Prom_HWord => r_TX_BYTE <= x"68"; -- "h"
-- When SBus_Slave_Ack_Read_Prom_Burst => r_TX_BYTE <= x"69"; -- "i"
-- When SBus_Slave_Ack_Read_Reg_Byte => r_TX_BYTE <= x"6a"; -- "j"
-- When SBus_Slave_Ack_Read_Reg_HWord => r_TX_BYTE <= x"6b"; -- "k"
-- When SBus_Slave_Ack_Read_Reg_Burst => r_TX_BYTE <= x"6c"; -- "l"
-- When SBus_Slave_Do_Read => r_TX_BYTE <= x"6d"; -- "m"
-- When SBus_Slave_Delay_Error => r_TX_BYTE <= x"6e"; -- "n"
-- When SBus_Slave_Error => r_TX_BYTE <= x"6f"; -- "o"
-- When others => r_TX_BYTE <= x"7a"; -- "z"
-- END CASE;
END IF;
WHEN UART_WAITING =>
if (w_TX_DONE = '1') then
Uart_State <= UART_IDLE;
END IF;
END CASE;
END IF;
END PROCESS;
-- process to enable signal after a while
process(fxclk_in)
BEGIN
IF RISING_EDGE(fxclk_in) THEN
IF (OE_COUNTER = 0) THEN
SBUS_OE <= '0';
ELSE
OE_COUNTER <= OE_COUNTER - 1;
END IF;
END IF;
END PROCESS;
END rtl;

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sbus-to-ztex-gateware/sbus_fsm_TB.vhd.cpp Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.numeric_std.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
entity SBusFSM_TB is
-- SIZ[2..0] is positive true
CONSTANT SIZ_WORD : std_logic_vector(2 downto 0):= "000";
CONSTANT SIZ_BYTE : std_logic_vector(2 downto 0):= "001";
CONSTANT SIZ_HWORD : std_logic_vector(2 downto 0):= "010";
CONSTANT SIZ_EXT : std_logic_vector(2 downto 0):= "011";
CONSTANT SIZ_BURST4 : std_logic_vector(2 downto 0):= "100";
CONSTANT SIZ_BURST8 : std_logic_vector(2 downto 0):= "101";
CONSTANT SIZ_BURST16 : std_logic_vector(2 downto 0):= "110";
CONSTANT SIZ_BURST2 : std_logic_vector(2 downto 0):= "111";
-- ACKs[2-0] is negative true
CONSTANT ACK_DISABLED : std_logic_vector(2 downto 0):= "ZZZ";
CONSTANT ACK_IDLE : std_logic_vector(2 downto 0):= "111";
CONSTANT ACK_ERR : std_logic_vector(2 downto 0):= "110";
CONSTANT ACK_BYTE : std_logic_vector(2 downto 0):= "101";
CONSTANT ACK_RERUN : std_logic_vector(2 downto 0):= "100";
CONSTANT ACK_WORD : std_logic_vector(2 downto 0):= "011";
CONSTANT ACK_DWORD : std_logic_vector(2 downto 0):= "010";
CONSTANT ACK_HWORD : std_logic_vector(2 downto 0):= "001";
CONSTANT ACK_RESV : std_logic_vector(2 downto 0):= "000";
-- ADDR RANGES ; (27 downto 9) so 19 bits
CONSTANT ROM_ADDR_PFX : std_logic_vector(18 downto 0) := "0000000000000000000";
CONSTANT REG_ADDR_PFX : std_logic_vector(18 downto 0) := "0000000000000000001";
-- OFFSET to REGS; (8 downto 0) so 9 bits
CONSTANT REG_OFFSET_LED : std_logic_vector(8 downto 0) := conv_std_logic_vector( 0, 9);
-- starts at 64 so we can do 64 bytes burst (see address wrapping)
CONSTANT REG_INDEX_GCM_H1 : integer := 0;
CONSTANT REG_INDEX_GCM_H2 : integer := 1;
CONSTANT REG_INDEX_GCM_H3 : integer := 2;
CONSTANT REG_INDEX_GCM_H4 : integer := 3;
CONSTANT REG_INDEX_GCM_C1 : integer := 4;
CONSTANT REG_INDEX_GCM_C2 : integer := 5;
CONSTANT REG_INDEX_GCM_C3 : integer := 6;
CONSTANT REG_INDEX_GCM_C4 : integer := 7;
CONSTANT REG_INDEX_GCM_INPUT1 : integer := 8;
CONSTANT REG_INDEX_GCM_INPUT2 : integer := 9;
CONSTANT REG_INDEX_GCM_INPUT3 : integer := 10;
CONSTANT REG_INDEX_GCM_INPUT4 : integer := 11;
CONSTANT REG_INDEX_GCM_INPUT5 : integer := 12; -- placeholder
CONSTANT REG_INDEX_GCM_INPUT6 : integer := 13; -- placeholder
CONSTANT REG_INDEX_GCM_INPUT7 : integer := 14; -- placeholder
CONSTANT REG_INDEX_GCM_INPUT8 : integer := 15; -- placeholder
CONSTANT REG_OFFSET_GCM_H1 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H1*4, 9);
CONSTANT REG_OFFSET_GCM_H2 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H2*4, 9);
CONSTANT REG_OFFSET_GCM_H3 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H3*4, 9);
CONSTANT REG_OFFSET_GCM_H4 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_H4*4, 9);
CONSTANT REG_OFFSET_GCM_C1 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C1*4, 9);
CONSTANT REG_OFFSET_GCM_C2 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C2*4, 9);
CONSTANT REG_OFFSET_GCM_C3 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C3*4, 9);
CONSTANT REG_OFFSET_GCM_C4 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_C4*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT1 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT1*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT2 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT2*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT3 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT3*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT4 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT4*4, 9);
CONSTANT REG_OFFSET_GCM_INPUT5 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT5*4, 9); -- placeholder
CONSTANT REG_OFFSET_GCM_INPUT6 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT6*4, 9); -- placeholder
CONSTANT REG_OFFSET_GCM_INPUT7 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT7*4, 9); -- placeholder
CONSTANT REG_OFFSET_GCM_INPUT8 : std_logic_vector(8 downto 0) := conv_std_logic_vector(64 + REG_INDEX_GCM_INPUT8*4, 9); -- placeholder
end entity;
architecture sim of SBusFSM_TB is
COMPONENT SBusFSM is
PORT (
fxclk_in: IN std_logic; -- 48 MHz interface clock
-- true SBus signals
SBUS_3V3_CLK : IN STD_LOGIC; -- 16.67..25 MHz SBus Clock
SBUS_3V3_RSTs : IN STD_LOGIC;
SBUS_3V3_SELs : IN STD_LOGIC;
SBUS_3V3_ASs : IN STD_LOGIC;
SBUS_3V3_PPRD : IN STD_LOGIC;
SBUS_3V3_SIZ : IN std_logic_vector(2 downto 0);
SBUS_3V3_ACKs : OUT std_logic_vector(2 downto 0);
SBUS_3V3_PA : IN std_logic_vector(27 downto 0);
SBUS_3V3_ERRs : OUT STD_LOGIC;
SBUS_3V3_D : INOUT std_logic_vector(31 downto 0);
SBUS_3V3_INT1s : OUT STD_LOGIC;
SBUS_3V3_INT7s : OUT STD_LOGIC;
-- master-only signals
SBUS_3V3_BGs : IN STD_LOGIC; -- bus granted
SBUS_3V3_BRs : OUT STD_LOGIC := 'Z'; -- bus request
-- support signals
SBUS_OE : OUT STD_LOGIC := '0';
-- support leds
SBUS_DATA_OE_LED : OUT std_logic; -- light during read cycle
SBUS_DATA_OE_LED_2 : OUT std_logic; -- light during write cycle
-- data leds
LED0 : OUT std_logic := '0';
LED1 : OUT std_logic := '0';
LED2 : OUT std_logic := '0';
LED3 : OUT std_logic := '0';
LED4 : OUT std_logic := '0';
LED5 : OUT std_logic := '0';
LED6 : OUT std_logic := '0';
LED7 : OUT std_logic := '0'
);
END COMPONENT;
signal fxclk_in: std_logic;
signal SBUS_3V3_CLK : std_logic;
signal SBUS_3V3_RSTs : std_logic;
signal SBUS_3V3_SELs : STD_LOGIC;
signal SBUS_3V3_ASs : STD_LOGIC;
signal SBUS_3V3_PPRD : STD_LOGIC;
signal SBUS_3V3_SIZ : std_logic_vector(2 downto 0);
signal SBUS_3V3_ACKs : std_logic_vector(2 downto 0);
signal SBUS_3V3_PA : std_logic_vector(27 downto 0);
signal SBUS_3V3_ERRs : STD_LOGIC;
signal SBUS_3V3_D : std_logic_vector(31 downto 0);
signal SBUS_3V3_INT1s : STD_LOGIC;
signal SBUS_3V3_INT7s : STD_LOGIC;
signal SBUS_3V3_BGs : STD_LOGIC; -- bus granted
signal SBUS_3V3_BRs : STD_LOGIC; -- bus request
-- support signals
signal SBUS_OE : STD_LOGIC;
-- support leds
signal SBUS_DATA_OE_LED : std_logic; -- light during read cycle
signal SBUS_DATA_OE_LED_2 : std_logic; -- light during write cycle
-- data leds
signal LED0 : std_logic;
signal LED1 : std_logic;
signal LED2 : std_logic;
signal LED3 : std_logic;
signal LED4 : std_logic;
signal LED5 : std_logic;
signal LED6 : std_logic;
signal LED7 : std_logic;
CONSTANT PROM_SIZE : natural := 25;
SIGNAL PROM_COUNTER : natural range 0 to PROM_SIZE*4 := 0;
SIGNAL LED_COUNTER : natural range 0 to 4 := 0;
-- Procedure for clock generation
procedure clk_gen(signal clk : OUT std_logic; constant FREQ : real) is
constant PERIOD : time := 1 sec / FREQ; -- Full period
constant HIGH_TIME : time := PERIOD / 2; -- High time
constant LOW_TIME : time := PERIOD - HIGH_TIME; -- Low time; always >= HIGH_TIME
begin
-- Check the arguments
assert (HIGH_TIME /= 0 fs) report "clk_plain: High time is zero; time resolution to large for frequency" severity FAILURE;
-- Generate a clock cycle
loop
clk <= '1';
wait for HIGH_TIME;
clk <= '0';
wait for LOW_TIME;
end loop;
end procedure;
PROCEDURE MasterRequestRead (
signal SBUS_3V3_CLK : in std_logic;
SIGNAL SBUS_3V3_SELs : out std_logic;
SIGNAL SBUS_3V3_ASs : out std_logic;
SIGNAL SBUS_3V3_PPRD : out std_logic;
SIGNAL SBUS_3V3_PA : out std_logic_vector(27 downto 0);
SIGNAL SBUS_3V3_SIZ : out std_logic_vector(2 downto 0);
constant phys_addr : in std_logic_vector(27 downto 0);
constant size : in std_logic_vector(2 downto 0)
) is
begin
-- should be called on a rising edge of clock +0.1 ns
wait for 24 ns;
SBUS_3V3_SELs <= '0';
SBUS_3V3_ASs <= '0';
SBUS_3V3_PPRD <= '1';
SBUS_3V3_PA <= phys_addr;
SBUS_3V3_SIZ <= size;
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
END PROCEDURE;
PROCEDURE MasterRequestWrite (
signal SBUS_3V3_CLK : in std_logic;
SIGNAL SBUS_3V3_SELs : out std_logic;
SIGNAL SBUS_3V3_ASs : out std_logic;
SIGNAL SBUS_3V3_PPRD : out std_logic;
SIGNAL SBUS_3V3_PA : out std_logic_vector(27 downto 0);
SIGNAL SBUS_3V3_SIZ : out std_logic_vector(2 downto 0);
SIGNAL SBUS_3V3_D : out std_logic_vector(31 downto 0);
constant phys_addr : in std_logic_vector(27 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant data : in std_logic_vector(31 downto 0)
) is
begin
-- should be called on a rising edge of clock +0.1 ns
wait for 24 ns;
SBUS_3V3_SELs <= '0';
SBUS_3V3_ASs <= '0';
SBUS_3V3_PPRD <= '0';
SBUS_3V3_PA <= phys_addr;
SBUS_3V3_SIZ <= size;
SBUS_3V3_D <= data;
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
END PROCEDURE;
PROCEDURE MasterRequestWriteBurst4 (
signal SBUS_3V3_CLK : in std_logic;
SIGNAL SBUS_3V3_SELs : out std_logic;
SIGNAL SBUS_3V3_ASs : out std_logic;
SIGNAL SBUS_3V3_PPRD : out std_logic;
SIGNAL SBUS_3V3_PA : out std_logic_vector(27 downto 0);
SIGNAL SBUS_3V3_SIZ : out std_logic_vector(2 downto 0);
SIGNAL SBUS_3V3_D : out std_logic_vector(31 downto 0);
constant phys_addr : in std_logic_vector(27 downto 0);
constant data1 : in std_logic_vector(31 downto 0);
constant data2 : in std_logic_vector(31 downto 0);
constant data3 : in std_logic_vector(31 downto 0);
constant data4 : in std_logic_vector(31 downto 0)
) is
begin
-- should be called on a rising edge of clock +0.1 ns
wait for 24 ns;
SBUS_3V3_SELs <= '0';
SBUS_3V3_ASs <= '0';
SBUS_3V3_PPRD <= '0';
SBUS_3V3_PA <= phys_addr;
SBUS_3V3_SIZ <= SIZ_BURST4;
SBUS_3V3_D <= data1;
wait until rising_edge(SBUS_3V3_CLK) and (SBUS_3V3_ACKs = ACK_WORD);
-- wait for 2.5 ns;
-- SBUS_3V3_D <= (others => '0');
wait for 20 ns;
SBUS_3V3_D <= data2;
wait until rising_edge(SBUS_3V3_CLK) and (SBUS_3V3_ACKs = ACK_WORD);
-- wait for 2.5 ns;
-- SBUS_3V3_D <= (others => '0');
wait for 20 ns;
SBUS_3V3_D <= data3;
wait until rising_edge(SBUS_3V3_CLK) and (SBUS_3V3_ACKs = ACK_WORD);
-- wait for 2.5 ns;
-- SBUS_3V3_D <= (others => '0');
wait for 20 ns;
SBUS_3V3_D <= data4;
END PROCEDURE;
procedure MasterWaitAck (
signal SBUS_3V3_CLK : in std_logic;
signal SBUS_3V3_ACKs : in std_logic_vector(2 downto 0);
constant ack : in std_logic_vector(2 downto 0)
) is
begin
-- should be called on a rising edge of clock +0.1 ns
wait until (rising_edge(SBUS_3V3_CLK) and (SBUS_3V3_ACKs = ack or SBUS_3V3_ACKs = "110" ));
wait for 0.1 ns;
-- "110" is an error ack
end PROCEDURE;
PROCEDURE MasterEndRequest (
signal SBUS_3V3_CLK : in std_logic;
SIGNAL SBUS_3V3_SELs : out std_logic;
SIGNAL SBUS_3V3_ASs : out std_logic;
SIGNAL SBUS_3V3_PPRD : out std_logic;
SIGNAL SBUS_3V3_PA : out std_logic_vector(27 downto 0);
SIGNAL SBUS_3V3_SIZ : out std_logic_vector(2 downto 0);
SIGNAL SBUS_3V3_D : out std_logic_vector(31 downto 0)
) is
begin
-- should be called on a rising edge of clock +0.1 ns
wait for 24 ns;
SBUS_3V3_SELs <= '1';
SBUS_3V3_ASs <= '1';
SBUS_3V3_PPRD <= 'Z';
SBUS_3V3_PA <= (others => 'Z');
SBUS_3V3_D <= (others => 'Z');
SBUS_3V3_SIZ <= (others => 'Z');
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
end PROCEDURE;
begin
uut: SBusFSM PORT MAP (fxclk_in => fxclk_in, SBUS_3V3_CLK => SBUS_3V3_CLK, SBUS_3V3_RSTs => SBUS_3V3_RSTs, SBUS_3V3_SELs => SBUS_3V3_SELs, SBUS_3V3_ASs => SBUS_3V3_ASs, SBUS_3V3_PPRD => SBUS_3V3_PPRD, SBUS_3V3_SIZ => SBUS_3V3_SIZ, SBUS_3V3_ACKs => SBUS_3V3_ACKs, SBUS_3V3_PA => SBUS_3V3_PA, SBUS_3V3_ERRs => SBUS_3V3_ERRs, SBUS_3V3_D => SBUS_3V3_D, SBUS_3V3_INT1s => SBUS_3V3_INT1s, SBUS_3V3_INT7s => SBUS_3V3_INT7s, SBUS_3V3_BGs => SBUS_3V3_BGs, SBUS_3V3_BRs => SBUS_3V3_BRs, SBUS_OE => SBUS_OE, SBUS_DATA_OE_LED => SBUS_DATA_OE_LED, SBUS_DATA_OE_LED_2 => SBUS_DATA_OE_LED_2,
LED0 => LED0, LED1 => LED1, LED2 => LED2, LED3 => LED3, LED4 => LED4, LED5 => LED5, LED6 => LED6, LED7 => LED7
);
process begin
-- Clock generation with concurrent procedure call
clk_gen(SBUS_3V3_CLK, 25.0E6); -- 25 MHz clock
end process;
process begin
clk_gen(fxclk_in, 48.0E6); -- 48 MHz clock
end process;
process begin
SBUS_3V3_RSTs <= '0';
wait for 115 ns; -- 3 clocks minus 5ns
SBUS_3V3_RSTs <= '1';
wait;
end process;
process
variable s : line;
begin
SBUS_3V3_SELs <= '1'; -- unselect slave
SBUS_3V3_ASs <= '1';
SBUS_3V3_D <= (others => 'Z');
SBUS_3V3_PA <= (others => 'Z');
SBUS_3V3_SIZ <= (others => 'Z');
SBUS_3V3_BGs <= 'Z';
wait for 220 ns; -- wait for reset to be done
#ifdef WRITE_LEDS_WORD
-- test 32 bits write to leds
wait for 115 ns; -- 3 clocks minus 5ns
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_LED, -- 0x200
SIZ_WORD, -- word
"11111000110001001010001000110001");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
wait;
#endif // WRITE_LEDS_WORD
#ifdef WRITE_LEDS_BYTE
-- test 8 bits write to leds
wait for 115 ns; -- 3 clocks minus 5ns
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
case LED_COUNTER is
WHEN 0 =>
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_LED, -- 0x200
SIZ_BYTE, -- byte
"11111000" & "ZZZZZZZZZZZZZZZZZZZZZZZZ");
WHEN 1 =>
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & (REG_OFFSET_LED+1), -- 0x201
SIZ_BYTE, -- byte
"11000100" & "ZZZZZZZZZZZZZZZZZZZZZZZZ");
WHEN 2 =>
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & (REG_OFFSET_LED+2), -- 0x202
SIZ_BYTE, -- byte
"10100010" & "ZZZZZZZZZZZZZZZZZZZZZZZZ");
WHEN 3 =>
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & (REG_OFFSET_LED+3), -- 0x203
SIZ_BYTE, -- byte
"00110001" & "ZZZZZZZZZZZZZZZZZZZZZZZZ");
WHEN others =>
end case;
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_BYTE); -- byte
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
LED_COUNTER <= LED_COUNTER + 1;
if (LED_COUNTER = 4) then
wait;
else
end if;
#endif // WRITE_LEDS_BYTE
#ifdef READ_PROM_WORD
-- test read from PROM as Word
wait for 115 ns; -- 3 clocks minus 5ns
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
conv_std_logic_vector(PROM_COUNTER, 28),
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
PROM_COUNTER <= PROM_COUNTER + 4;
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
if (PROM_COUNTER = PROM_SIZE*4) then
wait;
else
end if;
#endif // READ_PROM_WORD
#ifdef READ_PROM_BURST4
-- test read from PROM as Burst4 Word
wait for 115 ns; -- 3 clocks minus 5ns
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
conv_std_logic_vector(PROM_COUNTER, 28),
SIZ_BURST4); -- burst4
-- this next sequence only works for 1 word/cycle burst
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_D);
writeline(output, s); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_D);
writeline(output, s); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_D);
writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
PROM_COUNTER <= PROM_COUNTER + 16;
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
if (PROM_COUNTER >= PROM_SIZE*4) then
wait;
else
end if;
#endif // READ_PROM_BURST4
#ifdef READ_PROM_BYTE
-- test read from PROM as Byte
wait for 115 ns; -- 3 clocks minus 5ns
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
conv_std_logic_vector(PROM_COUNTER, 28),
SIZ_BYTE); -- byte
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_BYTE); -- byte
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D(31 downto 24));
wait for 0.1 ns;
writeline(output, s);
PROM_COUNTER <= PROM_COUNTER + 1;
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
if (PROM_COUNTER = PROM_SIZE*4) then
wait;
else
end if;
#endif // READ_PROM_BYTE
#ifdef READ_PROM_HWORD
-- test read from PROM as HWord
wait for 115 ns; -- 3 clocks minus 5ns
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
conv_std_logic_vector(PROM_COUNTER, 28),
SIZ_HWORD); -- byte
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_HWORD); -- byte
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D(31 downto 16));
wait for 0.1 ns;
writeline(output, s);
PROM_COUNTER <= PROM_COUNTER + 2;
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
if (PROM_COUNTER = PROM_SIZE*4) then
wait;
else
end if;
#endif // READ_PROM_HWORD
#ifdef DO_GCM
-- test 32 bits GCM
wait for 115 ns; -- 3 clocks minus 5ns
wait until rising_edge(SBUS_3V3_CLK);
wait for 0.1 ns;
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_H1,
SIZ_WORD, -- word
x"6b8b4567");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_H2,
SIZ_WORD, -- word
x"66334873");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_H3,
SIZ_WORD, -- word
x"2ae8944a");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_H4,
SIZ_WORD, -- word
x"46e87ccd");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_H4,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_C1,
SIZ_WORD, -- word
x"327b23c6");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_C2,
SIZ_WORD, -- word
x"74b0dc51");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_C3,
SIZ_WORD, -- word
x"625558ec");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_C4,
SIZ_WORD, -- word
x"3d1b58ba");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_C4,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT1,
SIZ_WORD, -- word
x"643c9869");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT2,
SIZ_WORD, -- word
x"19495cff");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT3,
SIZ_WORD, -- word
x"238e1f29");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT4,
SIZ_WORD, -- word
x"507ed7ab");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_C1,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_C2,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_C3,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_C4,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
-- expect 0x1f1554d6 0x82e930b8 0xdbd891cc 0x91f3f7c9 from the write above
-- MasterRequestWrite(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
-- REG_ADDR_PFX & REG_OFFSET_GCM_INPUT4,
-- SIZ_WORD, -- word
-- x"507ed7ab");
-- MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
-- ACK_WORD); -- word
--hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
-- MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
-- 0x11265233 0x1b6d90f3 0x53b8d61b 0x40e13340
-- MasterRequestWriteBurst4(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
-- REG_ADDR_PFX & REG_OFFSET_GCM_INPUT1,
-- x"11265233",
-- x"1b6d90f3",
-- x"53b8d61b",
-- x"40e13340");
-- next with address wrap
MasterRequestWriteBurst4(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT2,
x"1b6d90f3",
x"53b8d61b",
x"40e13340",
x"11265233");
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT1,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT2,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT3,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_INPUT4,
SIZ_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_ACKs); writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
-- try reading again, burst
wait for 40 ns; -- 1 cycle
wait for 40 ns; -- 1 cycle
wait for 40 ns; -- 1 cycle
MasterRequestRead(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ,
REG_ADDR_PFX & REG_OFFSET_GCM_C1,
SIZ_BURST4); -- word
-- this next sequence only works for 1 word/cycle burst
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_D);
writeline(output, s); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_D);
writeline(output, s); -- word
MasterWaitAck(SBUS_3V3_CLK, SBUS_3V3_ACKs,
ACK_WORD); -- word
hwrite(s, SBUS_3V3_D);
writeline(output, s);
wait until rising_edge(SBUS_3V3_CLK);
hwrite(s, SBUS_3V3_D);
wait for 0.1 ns;
writeline(output, s);
MasterEndRequest(SBUS_3V3_CLK, SBUS_3V3_SELs, SBUS_3V3_ASs, SBUS_3V3_PPRD, SBUS_3V3_PA, SBUS_3V3_SIZ, SBUS_3V3_D);
-- expect 0x420f015c 0x7dc538f1 0xa6badb5f 0x0676df7b from the additional burst on input
wait;
#endif // DO_GCM
END PROCESS;
end architecture;