github.com/rdolbeau.SBusFPGA
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fix broken timeout, some (disabled, for testing) stat stuff

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This commit is contained in:
Romain Dolbeau
2021-10-30 10:02:33 +02:00
parent 06bff62901
commit f5a1067806
3 changed files with 63 additions and 27 deletions
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4
NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_stat.c
View File

@@ -211,11 +211,13 @@ static void sbusfpga_stat_display(void *args) {
if ((c2 == c) || (c2 == 0)){
device_printf(sc->sc_dev, "Statistics didn't update\n");
} else {
device_printf(sc->sc_dev, "%u: slave %u %u %u %u\n",
device_printf(sc->sc_dev, "%u: slave %u %u %u %u\n", // [0x%08x @ 0x%08x]
c2,
sbus_bus_stat_stat_slave_start_counter_read(sc),
sbus_bus_stat_stat_slave_done_counter_read(sc),
sbus_bus_stat_stat_slave_rerun_counter_read(sc),
//sbus_bus_stat_stat_slave_rerun_last_pa_read(sc),
//sbus_bus_stat_stat_slave_rerun_last_state_read(sc),
sbus_bus_stat_stat_slave_early_error_counter_read(sc));
device_printf(sc->sc_dev, "%u: master %u %u %u %u (0x%08x)\n",
c2,

75
sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
View File

@@ -47,7 +47,7 @@ CG3_PIXELS_ADDR2_BIGPFX = Signal(8, reset = 0x09) # cg3_pixels, remapped, second
CG3_PIXELS_ADDR2_BIGVAL = 0x09
wishbone_default_timeout = 120 ##
sbus_default_timeout = 50 ## must be below 255
sbus_default_timeout = 50 ## must be below 255/2 (two waits)
sbus_default_master_throttle = 3
def siz_is_word(siz):
@@ -319,8 +319,10 @@ class SBusFPGABus(Module):
wishbone_master_timeout = Signal(log2_int(wishbone_default_timeout, False))
wishbone_slave_timeout = Signal(log2_int(wishbone_default_timeout, False))
sbus_slave_timeout = Signal(log2_int(sbus_default_timeout, False))
self.sync += If(sbus_slave_timeout != 0, sbus_slave_timeout.eq(sbus_slave_timeout - 1))
sbus_master_throttle = Signal(log2_int(sbus_default_master_throttle, False))
self.sync += If(sbus_master_throttle != 0, sbus_master_throttle .eq(sbus_master_throttle - 1))
#self.submodules.led_display = LedDisplay(platform.request_all("user_led"))
@@ -414,6 +416,8 @@ class SBusFPGABus(Module):
stat_slave_done_counter = Signal(32)
stat_slave_rerun_counter = Signal(32)
stat_slave_early_error_counter = Signal(32)
#self.stat_slave_rerun_last_pa = stat_slave_rerun_last_pa = Signal(32)
#self.stat_slave_rerun_last_state = stat_slave_rerun_last_state = Signal(32)
stat_master_start_counter = Signal(32)
stat_master_done_counter = Signal(32)
@@ -1114,6 +1118,8 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WORD | LED_RERUN_LATE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000001),
NextState("Slave_Error")
)
)
@@ -1126,12 +1132,15 @@ class SBusFPGABus(Module):
NextValue(self.wishbone_master.we, 0),
NextValue(self.wishbone_master.adr, sbus_last_pa[2:32]),
NextValue(wishbone_master_timeout, wishbone_default_timeout),
NextValue(sbus_slave_timeout, sbus_default_timeout),
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 0))),
NextState("Slave_Ack_Read_Reg_Burst_Wait_For_Data")
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WORD),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000002),
NextState("Slave_Error")
)
)
@@ -1175,6 +1184,8 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_LATE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000003),
NextState("Slave_Error")
)
)
@@ -1187,12 +1198,15 @@ class SBusFPGABus(Module):
NextValue(self.wishbone_master.we, 0),
NextValue(self.wishbone_master.adr, sbus_last_pa[2:32]),
NextValue(wishbone_master_timeout, wishbone_default_timeout),
NextValue(sbus_slave_timeout, sbus_default_timeout),
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 0))),
NextState("Slave_Ack_Read_Reg_HWord_Wait_For_Data")
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000004),
NextState("Slave_Error")
)
)
@@ -1234,6 +1248,8 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_LATE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000005),
NextState("Slave_Error")
)
)
@@ -1246,12 +1262,15 @@ class SBusFPGABus(Module):
NextValue(self.wishbone_master.we, 0),
NextValue(self.wishbone_master.adr, sbus_last_pa[2:32]),
NextValue(wishbone_master_timeout, wishbone_default_timeout),
NextValue(sbus_slave_timeout, sbus_default_timeout),
#NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0), SBUS_3V3_PA_i, Signal(4, reset = 0))),
NextState("Slave_Ack_Read_Reg_Byte_Wait_For_Data")
).Elif(sbus_slave_timeout == 0, ### this is taking too long
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000006),
NextState("Slave_Error")
)
)
@@ -1305,6 +1324,8 @@ class SBusFPGABus(Module):
#NextValue(self.led_display.value, Cat(Signal(8, reset = LED_RERUN | LED_RERUN_WRITE | LED_RERUN_WORD), sbus_last_pa)),
#NextValue(led0123, LED_RERUN | LED_RERUN_WRITE | LED_RERUN_WORD),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000007),
NextState("Slave_Error")
)
)
@@ -1348,6 +1369,8 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WRITE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000008),
NextState("Slave_Error")
)
)
@@ -1391,6 +1414,8 @@ class SBusFPGABus(Module):
NextValue(SBUS_3V3_ACKs_o, ACK_RERUN),
#NextValue(led0123, LED_RERUN | LED_RERUN_WRITE),
NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1),
#NextValue(stat_slave_rerun_last_pa, sbus_last_pa),
#NextValue(stat_slave_rerun_last_state, 0x00000009),
NextState("Slave_Error")
)
)
@@ -1764,45 +1789,45 @@ class SBusFPGABus(Module):
NextValue(wishbone_slave_timeout, wishbone_slave_timeout -1)
),
If(self.wishbone_slave.ack & self.wishbone_slave.we,
If((~self.wishbone_slave.stb), # | (wishbone_slave_timeout == 0), #~self.wishbone_slave.cyc &
#If((~self.wishbone_slave.stb), # | (wishbone_slave_timeout == 0), #~self.wishbone_slave.cyc &
NextValue(self.wishbone_slave.ack, 0),
NextValue(wishbone_slave_timeout, 0)
)
#)
),
If(self.wishbone_slave.ack & ~self.wishbone_slave.we,
If((~self.wishbone_slave.stb), # | (wishbone_slave_timeout == 0), #~self.wishbone_slave.cyc &
#If((~self.wishbone_slave.stb), # | (wishbone_slave_timeout == 0), #~self.wishbone_slave.cyc &
NextValue(self.wishbone_slave.ack, 0),
NextValue(wishbone_slave_timeout, 0)
)
#)
),
If(self.wishbone_slave.err,
If((~self.wishbone_slave.stb), # | (wishbone_slave_timeout == 0), #~self.wishbone_slave.cyc &
#If((~self.wishbone_slave.stb), # | (wishbone_slave_timeout == 0), #~self.wishbone_slave.cyc &
NextValue(self.wishbone_slave.err, 0),
NextValue(wishbone_slave_timeout, 0)
)
#)
)
)
self.submodules.sbus_slave_wait_fsm = sbus_slave_wait_fsm = FSM(reset_state="Reset")
sbus_slave_wait_fsm.act("Reset",
NextState("Idle")
)
sbus_slave_wait_fsm.act("Idle",
If(sbus_slave_timeout != 0,
NextValue(sbus_slave_timeout, sbus_slave_timeout -1)
),
)
#self.submodules.sbus_slave_wait_fsm = sbus_slave_wait_fsm = FSM(reset_state="Reset")
#sbus_slave_wait_fsm.act("Reset",
# NextState("Idle")
#)
#sbus_slave_wait_fsm.act("Idle",
# If(sbus_slave_timeout != 0,
# NextValue(sbus_slave_timeout, sbus_slave_timeout -1)
# ),
#)
# ##### FIXME: debug only?
self.submodules.sbus_master_throttle_fsm = sbus_master_throttle_fsm = FSM(reset_state="Reset")
sbus_master_throttle_fsm.act("Reset",
NextState("Idle")
)
sbus_master_throttle_fsm.act("Idle",
If(sbus_master_throttle != 0,
NextValue(sbus_master_throttle, sbus_master_throttle -1)
),
)
#self.submodules.sbus_master_throttle_fsm = sbus_master_throttle_fsm = FSM(reset_state="Reset")
#sbus_master_throttle_fsm.act("Reset",
# NextState("Idle")
#)
#sbus_master_throttle_fsm.act("Idle",
# If(sbus_master_throttle != 0,
# NextValue(sbus_master_throttle, sbus_master_throttle -1)
# ),
#)
# ##### Slave read buffering FSM ####
last_read_word_idx = Signal(2)

11
sbus-to-ztex-gateware-migen/sbus_to_fpga_fsmstat.py
View File

@@ -4,7 +4,7 @@ from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone
class SBusFPGABusStat(Module, AutoCSR):
def __init__(self, sbus_bus):
def __init__(self, soc, sbus_bus):
self.stat_ctrl = CSRStorage(fields = [CSRField("update", 1, description = "update")])
self.submodules.sync_update = BusSynchronizer(width = 1, idomain="sys", odomain="sbus")
self.comb += self.sync_update.i.eq(self.stat_ctrl.fields.update)
@@ -15,6 +15,8 @@ class SBusFPGABusStat(Module, AutoCSR):
self.stat_slave_start_counter = CSRStatus(32, description="stat_slave_start_counter")
self.stat_slave_done_counter = CSRStatus(32, description="stat_slave_done_counter")
self.stat_slave_rerun_counter = CSRStatus(32, description="stat_slave_rerun_counter")
#self.stat_slave_rerun_last_pa = CSRStatus(32, description="stat_slave_rerun_last_pa")
#self.stat_slave_rerun_last_state = CSRStatus(32, description="stat_slave_rerun_last_state")
self.stat_slave_early_error_counter = CSRStatus(32, description="stat_slave_early_error_counter")
self.stat_master_start_counter = CSRStatus(32, description="stat_master_start_counter")
self.stat_master_done_counter = CSRStatus(32, description="stat_master_done_counter")
@@ -39,6 +41,13 @@ class SBusFPGABusStat(Module, AutoCSR):
self.submodules.sync_stat_slave_rerun_counter = BusSynchronizer(width = 32, idomain="sbus", odomain="sys");
self.comb += self.sync_stat_slave_rerun_counter.i.eq(sbus_bus.buf_stat_slave_rerun_counter)
self.comb += self.stat_slave_rerun_counter.status.eq(self.sync_stat_slave_rerun_counter.o)
#self.submodules.sync_stat_slave_rerun_last_pa = BusSynchronizer(width = 32, idomain="sbus", odomain="sys");
#self.comb += self.sync_stat_slave_rerun_last_pa.i.eq(sbus_bus.stat_slave_rerun_last_pa) # no 'buf_'
#self.comb += self.stat_slave_rerun_last_pa.status.eq(self.sync_stat_slave_rerun_last_pa.o)
#self.submodules.sync_stat_slave_rerun_last_state = BusSynchronizer(width = 32, idomain="sbus", odomain="sys");
#self.comb += self.sync_stat_slave_rerun_last_state.i.eq(sbus_bus.stat_slave_rerun_last_state) # no 'buf_'
#self.comb += self.stat_slave_rerun_last_state.status.eq(self.sync_stat_slave_rerun_last_state.o)
self.submodules.sync_stat_slave_early_error_counter = BusSynchronizer(width = 32, idomain="sbus", odomain="sys");
self.comb += self.sync_stat_slave_early_error_counter.i.eq(sbus_bus.buf_stat_slave_early_error_counter)
self.comb += self.stat_slave_early_error_counter.status.eq(self.sync_stat_slave_early_error_counter.o)