144 lines
4.2 KiB
VHDL
144 lines
4.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity aes_wrapper is
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port (
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aes_wrapper_rst : in std_logic;
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aes_wrapper_clk : in std_logic;
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-- iskey?, keylen, encdec, cbc, internal cbc, data (256 or 128 + 128)
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input_fifo_out : in std_logic_vector(260 downto 0);
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input_fifo_empty: in std_logic;
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input_fifo_rd_en : out std_logic;
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-- data (128)
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output_fifo_in : out std_logic_vector(127 downto 0);
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output_fifo_full : in std_logic;
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output_fifo_wr_en : out std_logic
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);
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TYPE AES_States IS ( AES_IDLE, AES_INIT1, AES_INIT2, AES_CRYPT1, AES_CRYPT2 );
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SIGNAL AES_State : AES_States := AES_IDLE;
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signal aes_reset_n : std_logic;
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signal aes_encdec : std_logic;
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signal aes_init : std_logic;
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signal aes_next : std_logic;
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signal aes_ready : std_logic;
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signal aes_key : std_logic_vector(255 downto 0);
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signal aes_keylen : std_logic;
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signal aes_block : std_logic_vector(127 downto 0);
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signal aes_result : std_logic_vector(127 downto 0);
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signal aes_result_valid : std_logic;
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signal aes_last : std_logic_vector(127 downto 0);
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constant iskey_idx : integer := 260;
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constant keylen_idx : integer := 259;
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constant encdec_idx : integer := 258;
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constant cbc_idx : integer := 257;
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constant intcbc_idx : integer := 256;
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end aes_wrapper;
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architecture RTL of aes_wrapper is
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component aes_core is
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port (
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clk : in std_logic;
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reset_n: in std_logic;
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encdec: in std_logic;
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init: in std_logic;
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xnext: in std_logic;
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ready: out std_logic;
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key: in std_logic_vector(255 downto 0);
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keylen: in std_logic;
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xblock: in std_logic_vector(127 downto 0);
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result: out std_logic_vector(127 downto 0);
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result_valid: out std_logic
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);
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end component aes_core;
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begin
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label_aes_core: aes_core port map(
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clk => aes_wrapper_clk,
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reset_n => aes_reset_n,
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encdec => aes_encdec,
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init => aes_init,
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xnext => aes_next,
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ready => aes_ready,
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key => aes_key,
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keylen => aes_keylen,
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xblock => aes_block,
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result => aes_result,
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result_valid => aes_result_valid
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);
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aes_wrapper: process (aes_wrapper_rst, aes_wrapper_clk)
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begin -- process aes_wrapper
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IF (aes_wrapper_rst = '0') THEN
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aes_reset_n <= '0';
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AES_State <= AES_IDLE;
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ELSIF RISING_EDGE(aes_wrapper_clk) then
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aes_reset_n <= '1';
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input_fifo_rd_en <= '0';
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output_fifo_wr_en <= '0';
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CASE AES_State IS
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WHEN AES_IDLE =>
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IF ((input_fifo_empty = '0') AND
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(output_fifo_full = '0') AND
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(aes_ready = '1')
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) then
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input_fifo_rd_en <= '1';
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IF (input_fifo_out(iskey_idx) = '1') THEN
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aes_key <= input_fifo_out(255 downto 0);
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aes_keylen <= input_fifo_out(keylen_idx);
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aes_init <= '1';
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aes_encdec <= input_fifo_out(encdec_idx);
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AES_State <= AES_INIT1;
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ELSE
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aes_next <= '1';
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aes_encdec <= input_fifo_out(encdec_idx);
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IF (input_fifo_out(cbc_idx) = '1') THEN
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-- cbc mode
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aes_block <= input_fifo_out(127 downto 0) XOR input_fifo_out(255 downto 128);
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ELSIF (input_fifo_out(intcbc_idx) = '1') THEN
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-- internal cbc mode
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aes_block <= input_fifo_out(127 downto 0) XOR aes_last;
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ELSE
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-- normal mode
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aes_block <= input_fifo_out(127 downto 0);
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END IF;
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AES_State <= AES_CRYPT1;
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END IF;
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END IF;
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WHEN AES_INIT1 =>
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AES_State <= AES_INIT2;
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WHEN AES_INIT2 =>
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aes_init <= '0';
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IF (aes_ready = '1') THEN
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AES_State <= AES_IDLE;
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END IF;
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WHEN AES_CRYPT1 =>
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AES_State <= AES_CRYPT2;
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WHEN AES_CRYPT2 =>
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aes_next <= '0';
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IF (aes_result_valid = '1') then
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output_fifo_wr_en <= '1';
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output_fifo_in <= aes_result;
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aes_last <= aes_result;
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AES_State <= AES_IDLE;
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END IF;
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END CASE;
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end IF;
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end process aes_wrapper;
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end RTL;
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