117 lines
3.4 KiB
VHDL
117 lines
3.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity trivium_wrapper is
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port (
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trivium_wrapper_rst : in std_logic;
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trivium_wrapper_clk : in std_logic;
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output_fifo_in : out std_logic_vector(31 downto 0);
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output_fifo_full : in std_logic;
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output_fifo_wr_en : out std_logic
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);
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end trivium_wrapper;
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architecture RTL of trivium_wrapper is
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component rng_trivium is
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generic (
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num_bits: integer range 1 to 64;
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init_key: std_logic_vector(79 downto 0);
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init_iv: std_logic_vector(79 downto 0) );
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port (
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clk: in std_logic;
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rst: in std_logic;
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reseed: in std_logic;
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newkey: in std_logic_vector(79 downto 0);
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newiv: in std_logic_vector(79 downto 0);
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out_ready: in std_logic;
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out_valid: out std_logic;
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out_data: out std_logic_vector(num_bits-1 downto 0) );
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end component;
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TYPE TRIVIUM_States IS ( TRIVIUM_IDLE, TRIVIUM_BYTE, TRIVIUM_OUT );
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SIGNAL TRIVIUM_State : TRIVIUM_States := TRIVIUM_IDLE;
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signal trivium_data : std_logic_vector(7 downto 0);
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signal trivium_rst : std_logic;
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signal trivium_out_ready : std_logic;
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signal trivium_out_valid : std_logic;
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begin
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label_trivium_core: rng_trivium
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generic map(
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num_bits => 8,
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init_key => x"01234657890123465789", -- ouch
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init_iv => x"98765432109876543210" -- ouch
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)
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port map(
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clk => trivium_wrapper_clk,
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rst => trivium_rst,
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reseed => '0', -- ouch
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newkey => (others => '0'), -- ouch
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newiv => (others => '0'), -- ouch
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out_ready => trivium_out_ready,
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out_valid => trivium_out_valid,
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out_data => trivium_data
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);
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trivium_wrapper: process (trivium_wrapper_rst, trivium_wrapper_clk)
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variable byte_index : integer range 0 to 3;
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variable buf : std_logic_vector(31 downto 0);
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begin -- process trivium_wrapper
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IF (trivium_wrapper_rst = '0') THEN
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trivium_rst <= '1';
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TRIVIUM_State <= TRIVIUM_IDLE;
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byte_index := 0;
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ELSIF RISING_EDGE(trivium_wrapper_clk) then
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trivium_rst <= '0';
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output_fifo_wr_en <= '0';
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CASE TRIVIUM_State IS
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WHEN TRIVIUM_IDLE =>
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IF (trivium_out_valid = '1') THEN
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TRIVIUM_State <= TRIVIUM_BYTE;
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trivium_out_ready <= '1';
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END IF;
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-- one byte every cycle, plus 1 cycle for out and 1 idle
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-- 6 cycles for 32 bits in the FIFO at most
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WHEN TRIVIUM_BYTE =>
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case byte_index IS
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WHEN 0 =>
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trivium_out_ready <= '1';
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buf(7 downto 0) := trivium_data;
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byte_index := 1;
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WHEN 1 =>
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trivium_out_ready <= '1';
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buf(15 downto 8) := trivium_data;
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byte_index := 2;
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WHEN 2 =>
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trivium_out_ready <= '1';
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buf(23 downto 16) := trivium_data;
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byte_index := 3;
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WHEN 3 =>
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trivium_out_ready <= '0';
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buf(31 downto 24) := trivium_data;
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TRIVIUM_State <= TRIVIUM_OUT;
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byte_index := 0;
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END CASE;
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when TRIVIUM_OUT =>
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trivium_out_ready <= '0';
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IF (output_fifo_full = '0') THEN
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output_fifo_in <= buf;
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output_fifo_wr_en <= '1';
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TRIVIUM_State <= TRIVIUM_IDLE;
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END IF;
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END CASE;
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end IF;
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end process trivium_wrapper;
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end RTL;
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