304 lines
19 KiB
Tcl
304 lines
19 KiB
Tcl
# keep those for which timings are irrelevant
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# timing doesn't matter for LEDs
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set_false_path -from * -to [get_ports { SBUS_DATA_OE_LED } ]
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set_false_path -from * -to [get_ports { SBUS_DATA_OE_LED_2 } ]
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set_false_path -from * -to [get_ports { LED0 } ]
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set_false_path -from * -to [get_ports { LED1 } ]
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set_false_path -from * -to [get_ports { LED2 } ]
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set_false_path -from * -to [get_ports { LED3 } ]
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set_false_path -from * -to [get_ports { LED4 } ]
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set_false_path -from * -to [get_ports { LED5 } ]
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set_false_path -from * -to [get_ports { LED6 } ]
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set_false_path -from * -to [get_ports { LED7 } ]
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# timing doesn't matter for INTs, slow and async
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set_false_path -from * -to [get_ports { SBUS_3V3_INT1s } ]
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set_false_path -from * -to [get_ports { SBUS_3V3_INT7s } ]
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# slow
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set_false_path -from * -to [get_ports { TX } ]
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# unrelated
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set_clock_groups -asynchronous -group [get_clocks SBUS_3V3_CLK] -group [get_clocks fxclk_in]
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# timing doesn't matter for RST, very long hold
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set_false_path -from [get_ports { SBUS_3V3_RSTs } ] -to *
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# shut up the warning for the LEDs (the set_false_path already lower severity)
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { SBUS_DATA_OE_LED } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { SBUS_DATA_OE_LED_2 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED0 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED1 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED2 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED3 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED4 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED5 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED6 } ]
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set_output_delay -clock SBUS_3V3_CLK -min 0 [get_ports { LED7 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { SBUS_DATA_OE_LED } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { SBUS_DATA_OE_LED_2 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED0 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED1 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED2 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED3 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED4 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED5 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED6 } ]
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set_output_delay -clock SBUS_3V3_CLK -max 1 [get_ports { LED7 } ]
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# COPY/PASTE here, same fixes needed as in the other XDC file
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set_input_delay -clock SBUS_3V3_CLK -min 0.838 [get_ports {SBUS_3V3_D[1]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.368 [get_ports {SBUS_3V3_D[1]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.738 [get_ports {SBUS_3V3_D[1]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.516 [get_ports {SBUS_3V3_D[1]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.874 [get_ports {SBUS_3V3_D[0]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.415 [get_ports {SBUS_3V3_D[0]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.702 [get_ports {SBUS_3V3_D[0]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.564 [get_ports {SBUS_3V3_D[0]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.841 [get_ports {SBUS_3V3_D[3]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.371 [get_ports {SBUS_3V3_D[3]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.736 [get_ports {SBUS_3V3_D[3]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.519 [get_ports {SBUS_3V3_D[3]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.838 [get_ports {SBUS_3V3_D[2]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.368 [get_ports {SBUS_3V3_D[2]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.738 [get_ports {SBUS_3V3_D[2]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.516 [get_ports {SBUS_3V3_D[2]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.842 [get_ports {SBUS_3V3_D[5]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.373 [get_ports {SBUS_3V3_D[5]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.734 [get_ports {SBUS_3V3_D[5]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.522 [get_ports {SBUS_3V3_D[5]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.882 [get_ports {SBUS_3V3_D[4]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.426 [get_ports {SBUS_3V3_D[4]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.694 [get_ports {SBUS_3V3_D[4]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.575 [get_ports {SBUS_3V3_D[4]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.839 [get_ports {SBUS_3V3_D[6]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.369 [get_ports {SBUS_3V3_D[6]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.737 [get_ports {SBUS_3V3_D[6]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.517 [get_ports {SBUS_3V3_D[6]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.810 [get_ports {SBUS_3V3_D[7]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.330 [get_ports {SBUS_3V3_D[7]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.766 [get_ports {SBUS_3V3_D[7]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.478 [get_ports {SBUS_3V3_D[7]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.810 [get_ports {SBUS_3V3_D[8]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.330 [get_ports {SBUS_3V3_D[8]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.766 [get_ports {SBUS_3V3_D[8]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.479 [get_ports {SBUS_3V3_D[8]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.751 [get_ports {SBUS_3V3_D[9]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.251 [get_ports {SBUS_3V3_D[9]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.825 [get_ports {SBUS_3V3_D[9]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.400 [get_ports {SBUS_3V3_D[9]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.804 [get_ports {SBUS_3V3_D[10]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.322 [get_ports {SBUS_3V3_D[10]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.772 [get_ports {SBUS_3V3_D[10]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.470 [get_ports {SBUS_3V3_D[10]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.756 [get_ports {SBUS_3V3_D[11]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.258 [get_ports {SBUS_3V3_D[11]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.820 [get_ports {SBUS_3V3_D[11]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.407 [get_ports {SBUS_3V3_D[11]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.778 [get_ports {SBUS_3V3_D[12]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.287 [get_ports {SBUS_3V3_D[12]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.798 [get_ports {SBUS_3V3_D[12]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.436 [get_ports {SBUS_3V3_D[12]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.729 [get_ports {SBUS_3V3_D[13]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.222 [get_ports {SBUS_3V3_D[13]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.847 [get_ports {SBUS_3V3_D[13]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.371 [get_ports {SBUS_3V3_D[13]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.750 [get_ports {SBUS_3V3_D[14]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.250 [get_ports {SBUS_3V3_D[14]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.826 [get_ports {SBUS_3V3_D[14]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.398 [get_ports {SBUS_3V3_D[14]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.708 [get_ports {SBUS_3V3_D[15]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.193 [get_ports {SBUS_3V3_D[15]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.869 [get_ports {SBUS_3V3_D[15]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.342 [get_ports {SBUS_3V3_D[15]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.817 [get_ports {SBUS_3V3_D[16]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.339 [get_ports {SBUS_3V3_D[16]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.759 [get_ports {SBUS_3V3_D[16]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.488 [get_ports {SBUS_3V3_D[16]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.707 [get_ports {SBUS_3V3_D[17]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.192 [get_ports {SBUS_3V3_D[17]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.870 [get_ports {SBUS_3V3_D[17]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.341 [get_ports {SBUS_3V3_D[17]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.724 [get_ports {SBUS_3V3_D[18]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.215 [get_ports {SBUS_3V3_D[18]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.852 [get_ports {SBUS_3V3_D[18]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.364 [get_ports {SBUS_3V3_D[18]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.711 [get_ports {SBUS_3V3_D[19]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.198 [get_ports {SBUS_3V3_D[19]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.865 [get_ports {SBUS_3V3_D[19]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.347 [get_ports {SBUS_3V3_D[19]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.708 [get_ports {SBUS_3V3_D[20]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.194 [get_ports {SBUS_3V3_D[20]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.868 [get_ports {SBUS_3V3_D[20]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.342 [get_ports {SBUS_3V3_D[20]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.758 [get_ports {SBUS_3V3_D[21]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.261 [get_ports {SBUS_3V3_D[21]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.818 [get_ports {SBUS_3V3_D[21]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.410 [get_ports {SBUS_3V3_D[21]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.707 [get_ports {SBUS_3V3_D[22]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.192 [get_ports {SBUS_3V3_D[22]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.870 [get_ports {SBUS_3V3_D[22]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.341 [get_ports {SBUS_3V3_D[22]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.695 [get_ports {SBUS_3V3_D[23]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.177 [get_ports {SBUS_3V3_D[23]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.881 [get_ports {SBUS_3V3_D[23]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.325 [get_ports {SBUS_3V3_D[23]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.654 [get_ports {SBUS_3V3_D[24]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.122 [get_ports {SBUS_3V3_D[24]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.922 [get_ports {SBUS_3V3_D[24]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.271 [get_ports {SBUS_3V3_D[24]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.682 [get_ports {SBUS_3V3_D[25]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.159 [get_ports {SBUS_3V3_D[25]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.894 [get_ports {SBUS_3V3_D[25]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.308 [get_ports {SBUS_3V3_D[25]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.633 [get_ports {SBUS_3V3_D[26]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.094 [get_ports {SBUS_3V3_D[26]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.943 [get_ports {SBUS_3V3_D[26]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.243 [get_ports {SBUS_3V3_D[26]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.655 [get_ports {SBUS_3V3_D[27]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.123 [get_ports {SBUS_3V3_D[27]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.921 [get_ports {SBUS_3V3_D[27]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.272 [get_ports {SBUS_3V3_D[27]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.632 [get_ports {SBUS_3V3_D[28]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.093 [get_ports {SBUS_3V3_D[28]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.944 [get_ports {SBUS_3V3_D[28]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.241 [get_ports {SBUS_3V3_D[28]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.662 [get_ports {SBUS_3V3_D[29]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.133 [get_ports {SBUS_3V3_D[29]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.914 [get_ports {SBUS_3V3_D[29]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.281 [get_ports {SBUS_3V3_D[29]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.618 [get_ports {SBUS_3V3_D[30]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.074 [get_ports {SBUS_3V3_D[30]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.958 [get_ports {SBUS_3V3_D[30]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.222 [get_ports {SBUS_3V3_D[30]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.688 [get_ports {SBUS_3V3_D[31]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.168 [get_ports {SBUS_3V3_D[31]}]
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set_output_delay -clock SBUS_3V3_CLK -min -1.888 [get_ports {SBUS_3V3_D[31]}]
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set_output_delay -clock SBUS_3V3_CLK -max 21.316 [get_ports {SBUS_3V3_D[31]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.645 [get_ports {SBUS_3V3_PA[1]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.109 [get_ports {SBUS_3V3_PA[1]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.649 [get_ports {SBUS_3V3_PA[0]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.116 [get_ports {SBUS_3V3_PA[0]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.658 [get_ports {SBUS_3V3_PA[3]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.127 [get_ports {SBUS_3V3_PA[3]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.656 [get_ports {SBUS_3V3_PA[2]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.125 [get_ports {SBUS_3V3_PA[2]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.679 [get_ports {SBUS_3V3_PA[4]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.155 [get_ports {SBUS_3V3_PA[4]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.666 [get_ports {SBUS_3V3_PA[5]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.138 [get_ports {SBUS_3V3_PA[5]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.680 [get_ports {SBUS_3V3_PA[6]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.157 [get_ports {SBUS_3V3_PA[6]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.682 [get_ports {SBUS_3V3_PA[7]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.160 [get_ports {SBUS_3V3_PA[7]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.685 [get_ports {SBUS_3V3_PA[8]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.164 [get_ports {SBUS_3V3_PA[8]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.714 [get_ports {SBUS_3V3_PA[9]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.202 [get_ports {SBUS_3V3_PA[9]}]
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set_input_delay -clock SBUS_3V3_CLK -min 0.703 [get_ports {SBUS_3V3_PA[10]}]
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set_input_delay -clock SBUS_3V3_CLK -max 25.188 [get_ports {SBUS_3V3_PA[10]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.714 [get_ports {SBUS_3V3_PA[11]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.201 [get_ports {SBUS_3V3_PA[11]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.715 [get_ports {SBUS_3V3_PA[12]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.203 [get_ports {SBUS_3V3_PA[12]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.733 [get_ports {SBUS_3V3_PA[13]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.227 [get_ports {SBUS_3V3_PA[13]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.729 [get_ports {SBUS_3V3_PA[14]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.221 [get_ports {SBUS_3V3_PA[14]}]
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.996 [get_ports {SBUS_3V3_SIZ[0]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.578 [get_ports {SBUS_3V3_SIZ[0]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.936 [get_ports {SBUS_3V3_ASs}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.497 [get_ports {SBUS_3V3_ASs}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 1.025 [get_ports {SBUS_3V3_BGs}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.617 [get_ports {SBUS_3V3_BGs}]
|
||
|
||
set_output_delay -clock SBUS_3V3_CLK -min -1.625 [get_ports {SBUS_3V3_BRs}]
|
||
set_output_delay -clock SBUS_3V3_CLK -max 21.667 [get_ports {SBUS_3V3_BRs}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.921 [get_ports {SBUS_3V3_SIZ[1]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.478 [get_ports {SBUS_3V3_SIZ[1]}]
|
||
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.932 [get_ports {SBUS_3V3_SIZ[2]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.493 [get_ports {SBUS_3V3_SIZ[2]}]
|
||
set_output_delay -clock SBUS_3V3_CLK -min -1.649 [get_ports {SBUS_3V3_ERRs}]
|
||
set_output_delay -clock SBUS_3V3_CLK -max 21.634 [get_ports {SBUS_3V3_ERRs}]
|
||
|
||
set_input_delay -clock SBUS_3V3_CLK -min 1.100 [get_ports {SBUS_3V3_RSTs}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.717 [get_ports {SBUS_3V3_RSTs}]
|
||
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.931 [get_ports {SBUS_3V3_SELs}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.491 [get_ports {SBUS_3V3_SELs}]
|
||
set_output_delay -clock SBUS_3V3_CLK -min -1.443 [get_ports {SBUS_3V3_INT1s}]
|
||
set_output_delay -clock SBUS_3V3_CLK -max 21.909 [get_ports {SBUS_3V3_INT1s}]
|
||
|
||
|
||
|
||
|
||
|
||
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.831 [get_ports {SBUS_3V3_PPRD}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.358 [get_ports {SBUS_3V3_PPRD}]
|
||
|
||
set_output_delay -clock SBUS_3V3_CLK -min -1.743 [get_ports {SBUS_3V3_ACKs[0]}]
|
||
set_output_delay -clock SBUS_3V3_CLK -max 21.510 [get_ports {SBUS_3V3_ACKs[0]}]
|
||
set_output_delay -clock SBUS_3V3_CLK -min -1.678 [get_ports {SBUS_3V3_INT7s}]
|
||
set_output_delay -clock SBUS_3V3_CLK -max 21.597 [get_ports {SBUS_3V3_INT7s}]
|
||
set_output_delay -clock SBUS_3V3_CLK -min -1.747 [get_ports {SBUS_3V3_ACKs[1]}]
|
||
set_output_delay -clock SBUS_3V3_CLK -max 21.504 [get_ports {SBUS_3V3_ACKs[1]}]
|
||
|
||
|
||
|
||
set_output_delay -clock SBUS_3V3_CLK -min -1.778 [get_ports {SBUS_3V3_ACKs[2]}]
|
||
set_output_delay -clock SBUS_3V3_CLK -max 21.463 [get_ports {SBUS_3V3_ACKs[2]}]
|
||
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.788 [get_ports {SBUS_3V3_PA[15]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.301 [get_ports {SBUS_3V3_PA[15]}]
|
||
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.797 [get_ports {SBUS_3V3_PA[17]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.313 [get_ports {SBUS_3V3_PA[17]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.855 [get_ports {SBUS_3V3_PA[16]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.389 [get_ports {SBUS_3V3_PA[16]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.811 [get_ports {SBUS_3V3_PA[19]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.332 [get_ports {SBUS_3V3_PA[19]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.852 [get_ports {SBUS_3V3_PA[18]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.386 [get_ports {SBUS_3V3_PA[18]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.812 [get_ports {SBUS_3V3_PA[21]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.332 [get_ports {SBUS_3V3_PA[21]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.849 [get_ports {SBUS_3V3_PA[20]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.382 [get_ports {SBUS_3V3_PA[20]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.818 [get_ports {SBUS_3V3_PA[23]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.340 [get_ports {SBUS_3V3_PA[23]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.859 [get_ports {SBUS_3V3_PA[22]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.395 [get_ports {SBUS_3V3_PA[22]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.827 [get_ports {SBUS_3V3_PA[25]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.352 [get_ports {SBUS_3V3_PA[25]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.863 [get_ports {SBUS_3V3_PA[24]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.401 [get_ports {SBUS_3V3_PA[24]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.824 [get_ports {SBUS_3V3_PA[27]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.348 [get_ports {SBUS_3V3_PA[27]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -min 0.871 [get_ports {SBUS_3V3_PA[26]}]
|
||
set_input_delay -clock SBUS_3V3_CLK -max 25.412 [get_ports {SBUS_3V3_PA[26]}]
|