Romain Dolbeau df88e17e9d upd

2021-06-21 11:40:17 -04:00

..

sbus_to_fpga_fsm.py

upd

2021-06-21 11:40:17 -04:00

sbus_to_fpga_slave.py

read/write registers in Wishbone space (burst untested)

2021-06-15 12:03:04 -04:00

sbus_to_fpga_soc.py

upd

2021-06-21 11:40:17 -04:00

sbus_to_fpga_wishbone.py

not working, the DMA seems to fails at frame 3...

2021-06-19 11:40:36 -04:00

sbus-to-fpga.py

read/write registers in Wishbone space (burst untested)

2021-06-15 12:03:04 -04:00