github.com/rdolbeau.VintageBusFPGA_Common
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Romain Dolbeau
2023-11-18 11:50:55 +01:00
parent 34b47e8df1
commit 765d99169d
1 changed files with 1 additions and 1 deletions
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MacPeriphSoC.py
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@@ -162,7 +162,7 @@ class MacPeriphSoC(SoCCore):
self.avail_sdram = self.bus.regions["main_ram"].size
if (hwinit):
from sdram_init import DDR3FBInit
from VintageBusFPGA_Common.sdram_init import DDR3FBInit
self.submodules.sdram_init = DDR3FBInit(sys_clk_freq = self.sys_clk_freq,
bitslip = 1, delay = 25, # CHECKME / FIXME: parameters
sdram_dfii_base = sdram_dfii_base, ddrphy_base = ddrphy_base)