github.com/rdolbeau.VintageBusFPGA_Common
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common sdram_init

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Romain Dolbeau
2023-11-18 11:54:09 +01:00
parent 31ed3afcba
commit 9266948658
1 changed files with 1 additions and 1 deletions
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sdram_init.py
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@@ -109,7 +109,7 @@ def startfb():
class DDR3Addr(WishboneMaster):
def __init__(self, sdram_dfii_base, ddrphy_base):
# /!\ keep up to date with csr /!\
self.sdram_dfii_base = sdram_dfii_base
self.sdram_dfii_base = sdram_dfii_base
self.sdram_dfii_control = self.sdram_dfii_base + 0x000
self.sdram_dfii_pi0_command = self.sdram_dfii_base + 0x004
self.sdram_dfii_pi0_command_issue = self.sdram_dfii_base + 0x008