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https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Added 'onerror' command
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@@ -189,6 +189,8 @@ class TestCPU(object):
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# cmpmem file
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# trace <range>[:<range>:...]
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# where <range> ::= <addr>,<addr>
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# onerror ('ignore'|'abort')
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# initially, "onerror abort" assumed
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def setreg(self, name, value):
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"""Set register to a value.
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@@ -280,6 +282,8 @@ class TestCPU(object):
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"""Execute one or more instructions.
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num_instructions number of instructions to execute
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Also sets self.abort to False.
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"""
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if num_instructions is None:
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@@ -299,7 +303,7 @@ class TestCPU(object):
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self.ptrptp.ptp_tick(cycles)
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self.used_cycles += cycles
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number -= 1
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self.abort = False
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def rununtil(self, address, ignore):
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"""Execute instructions until PC == address.
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@@ -311,6 +315,8 @@ class TestCPU(object):
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stop address.
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We also stop if the CPU executes the HLT instruction.
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Also sets self.abort to False.
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"""
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new_address = self.str2int(address)
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@@ -330,6 +336,7 @@ class TestCPU(object):
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self.used_cycles += cycles
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if self.cpu.PC == new_address:
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break
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self.abort = False
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def checkcycles(self, cycles, ignore):
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"""Check that opcode cycles used is correct.
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@@ -556,7 +563,20 @@ class TestCPU(object):
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trace_map[addr] = True
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trace.set_trace_map(trace_map)
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def onerror(self, state, ignore):
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"""Set the action upon an error.
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state either 'ignore' or 'error'
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"""
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if state == 'ignore':
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self.abort = False
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elif state == 'error':
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self.abort = True
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else:
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return 'onerror: bad action name: %s' % state
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# end of DSL primitives
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def check_all_mem(self):
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@@ -645,13 +665,15 @@ class TestCPU(object):
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self.ttyout = TtyOut.TtyOut()
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self.cpu = MainCPU.MainCPU(self.memory, None, None,
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None, self.ttyin, self.ttyout, self.ptrptp)
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# turn yrace OFF, initially
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# turn trace OFF, initially
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trace_map = collections.defaultdict(bool)
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trace.set_trace_map(trace_map)
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self.cpu.running = True
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self.display_state = False
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self.abort = True # abort on errors if True
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# prepare the trace
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trace.add_maincpu(self.cpu)
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@@ -722,20 +744,24 @@ class TestCPU(object):
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r = self.cmpmem(fld1, fld2)
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elif opcode == 'trace':
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r = self.trace(fld1, fld2)
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elif opcode == 'onerror':
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r = self.onerror(fld1, fld2)
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else:
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print("Unrecognized opcode '%s' in: %s" % (opcode, test))
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raise Exception("Unrecognized opcode '%s' in: %s" % (opcode, test))
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if r is not None:
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result.append(r)
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if self.abort:
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break
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# now check all memory and regs for changes
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r = self.check_all_mem()
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if r:
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if r is not None:
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result.append(r)
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r = self.check_all_regs()
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if r:
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if r is not None:
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result.extend(r)
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if result:
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