mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Removed obsolete test code
This commit is contained in:
Ross Wilson
@@ -1,704 +0,0 @@
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#!/usr/bin/env python
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# -*- coding: utf-8 -*-
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"""
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Test pymlac CPU opcodes DIRECTLY.
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Put opcodes into memory along with required memory values.
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Put L and AC values into registers.
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Execute opcode, test result.
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We DON'T try to load from papertape, use core files, etc.
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"""
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# We implement a small interpreter to test the CPU. The test code is read in
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# from a file:
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#
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# # LAW
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# setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LAW 0]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
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# setreg ac 012345; setreg l 0; setreg pc 0100; setmem 0100 [LAW 0]; RUN
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# checkcycles 1; checkreg pc 0101; checkreg ac 0
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#
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# The instructions are delimited by ';' characters. A line beginning with a
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# TAB character is a continuation of the previous. Lines with '#' in column
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# 1 are comments
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#
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# The test instructions are:
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#
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# setreg <name> <value>
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# where <name> is one of AC, L or PC, value is any value
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# (all registers are set to 0 initially)
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#
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# setmem <addr> <value>
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# where <addr> is an address and value is any value OR
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# [<instruction>] where the value is the assembled opcode
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#
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# run [<addr>]
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# starts execution, optional <addr> is used PC := addr before
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#
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# checkcycles <number>
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# check number of executed cycles is <number>
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#
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# checkreg <name> <value>
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# check register (AC, L or PC) has value <value>
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#
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# checkmem <addr> <value>
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# check that memory at <addr> has <value>
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#
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# memset <value>
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# sets all of memory to <value>
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# a "memset 0" is assumed before each test
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#
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# In addition, all of memory is checked for changed values after execution
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# except where an explicit "checkmem <addr> <value>" has been performed.
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# Additionally, registers that aren't explicitly checked are tested to make
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# sure they didn't change.
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#
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import unittest
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import MainCPU
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import Memory
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import Trace
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class TestPymlac(unittest.TestCase):
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def test_LAW(self):
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Trace.init('test_LAW.trace')
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Trace.settrace(True)
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Memory.init()
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# test "LAW 0"
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Memory.memory[0100] = 004000 # LAW 0
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0" left AC containing %07o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"LAW 0" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LAW 0" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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Memory.memory[0100] = 004000 # LAW 0
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0" left AC containing %07o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"LAW 0" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LAW 0" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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# test "LAW 0377"
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Memory.memory[0100] = 004377 # LAW 0377
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0377" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0377" left AC containing %07o, should be 0377' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0377, msg)
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msg = '"LAW 0377" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LAW 0377" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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Memory.memory[0100] = 004377 # LAW 0377
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0377" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0377" left AC containing %07o, should be 0377' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0377, msg)
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msg = '"LAW 0377" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LAW 0377" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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def test_LWC(self):
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Trace.init('test_LWC.trace')
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Trace.settrace(True)
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Memory.init()
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# test "LWC 0"
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Memory.memory[0100] = 0104000 # LWC 0
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 0" left AC containing %07o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"LWC 0" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LWC 0" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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Memory.memory[0100] = 0104000 # LWC 0
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 0" left AC containing %07o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"LWC 0" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LWC 0" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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# test "LWC 1"
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Memory.memory[0100] = 0104001 # LWC 1
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 1" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 1" left AC containing %07o, should be 0177776' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177776, msg)
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msg = '"LWC 1" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LWC 1" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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Memory.memory[0100] = 0104001 # LWC 1
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 1" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 1" left AC containing %07o, should be 0177776' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177776, msg)
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msg = '"LWC 1" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LWC 1" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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def test_JMP(self):
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Trace.init('test_JMP.trace')
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Trace.settrace(True)
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Memory.init()
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# test "JMP 0200"
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Memory.memory[0100] = 0010200 # JMP 0200
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"JMP 0200" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"JMP 0200" left AC containing %07o, should be 012345' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 012345, msg)
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msg = '"JMP 0200" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"JMP 0200" modified PC to %07o, should be 0200' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0200, msg)
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# test "JMP 0110"
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Memory.memory[0100] = 0010110 # JMP 0110
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"JMP 0110" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"JMP 0110" left AC containing %07o, should be 012345' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 012345, msg)
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msg = '"JMP 0110" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"JMP 0110" modified PC to %07o, should be 0110' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0110, msg)
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# test "JMP *0110"
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Memory.memory[0100] = 0110110 # JMP *0110
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Memory.memory[0110] = 0120 # where next PC should be
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"JMP *0110" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"JMP *0110" left AC containing %07o, should be 012345' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 012345, msg)
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msg = '"JMP *0110" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"JMP *0110" modified PC to %07o, should be 0120' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0120, msg)
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def test_DAC(self):
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Trace.init('test_DAC.trace')
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Trace.settrace(True)
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Memory.init()
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# test "DAC 0101"
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Memory.memory[0100] = 0020101 # DAC 0101
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Memory.memory[0101] = 0 # value we are storing over
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MainCPU.init()
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MainCPU.AC = 1
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"DAC 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"DAC 0101" left AC containing %07o, should be 1' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 1, msg)
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msg = '"DAC 0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"DAC 0101" modified memory[0101] to %07o, should be 1' % Memory.memory[0101]
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self.assertTrue(Memory.memory[0101] == 1, msg)
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msg = '"DAC 0101" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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# test "DAC *0101"
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Memory.memory[0100] = 0120101 # DAC *0101
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Memory.memory[0101] = 0102 # address of cell we are storing into
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Memory.memory[0102] = 0
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MainCPU.init()
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MainCPU.AC = 0177777
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"DAC *0101" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"DAC *0101" left AC containing %07o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"DAC *0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"DAC *0101" modified memory[0102] to %07o, should be 0177777' % Memory.memory[0102]
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self.assertTrue(Memory.memory[0102] == 0177777, msg)
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msg = '"DAC *0101" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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# test "DAC *010"
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Memory.memory[0100] = 0120010 # DAC *010
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Memory.memory[010] = 0102 # address of cell we are storing into
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Memory.memory[0102] = 0
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Memory.memory[0103] = 0
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MainCPU.init()
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MainCPU.AC = 0177777
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"DAC *010" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"DAC *010" left AC containing %07o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"DAC *010" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"DAC *010" modified memory[0102] to %07o, should be 0' % Memory.memory[0102]
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self.assertTrue(Memory.memory[0102] == 0, msg)
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msg = '"DAC *010" modified memory[0103] to %07o, should be 0177777' % Memory.memory[0103]
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self.assertTrue(Memory.memory[0103] == 0177777, msg)
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msg = '"DAC *010" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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def test_XAM(self):
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Trace.init('test_XAM.trace')
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Trace.settrace(True)
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Memory.init()
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# test "XAM 0101"
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Memory.memory[0100] = 0024101 # XAM 0101
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Memory.memory[0101] = 0 # value we are exchanging
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MainCPU.init()
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MainCPU.AC = 2
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"XAM 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"XAM 0101" left AC containing %07o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"XAM 0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"XAM 0101" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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msg = '"XAM 0101" modified memory[0101] to %07o, should be 2' % Memory.memory[0101]
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self.assertTrue(Memory.memory[0101] == 2, msg)
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# test "XAM *0101"
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Memory.memory[0100] = 0124101 # XAM *0101
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Memory.memory[0101] = 0102 # address of cell we are storing into
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Memory.memory[0102] = 0
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MainCPU.init()
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MainCPU.AC = 0177777
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"XAM *0101" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"XAM *0101" left AC containing %07o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"XAM *0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"XAM *0101" modified PC to %07o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC == 0101, msg)
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msg = '"XAM *0101" modified memory[0102] to %07o, should be 0177777' % Memory.memory[0102]
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self.assertTrue(Memory.memory[0102] == 0177777, msg)
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def test_ISZ(self):
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Trace.init('test_ISZ.trace')
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Trace.settrace(True)
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Memory.init()
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# test "ISZ 0101"
|
||||
Memory.memory[0100] = 0030101 # ISZ 0101
|
||||
Memory.memory[0101] = 0 # value we are incrementing/testing
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 2
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ISZ 0101" used %d cycles, should be 2' % cycles
|
||||
self.assertTrue(cycles == 2, msg)
|
||||
msg = '"ISZ 0101" left AC containing %07o, should be 2' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 2, msg)
|
||||
msg = '"ISZ 0101" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ISZ 0101" modified PC to %07o, should be 0101' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0101, msg)
|
||||
msg = '"ISZ 0101" modified memory[0101] to %07o, should be 1' % Memory.memory[0101]
|
||||
self.assertTrue(Memory.memory[0101] == 1, msg)
|
||||
|
||||
# test "ISZ *0101"
|
||||
Memory.memory[0100] = 0130101 # ISZ *0101
|
||||
Memory.memory[0101] = 0102 # address of cell we are storing into
|
||||
Memory.memory[0102] = 0
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 0177777
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ISZ *0101" used %d cycles, should be 3' % cycles
|
||||
self.assertTrue(cycles == 3, msg)
|
||||
msg = '"ISZ *0101" left AC containing %07o, should be 0177777' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 0177777, msg)
|
||||
msg = '"ISZ *0101" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ISZ *0101" modified PC to %07o, should be 0101' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0101, msg)
|
||||
msg = '"ISZ *0101" modified memory[0102] to %07o, should be 1' % Memory.memory[0102]
|
||||
self.assertTrue(Memory.memory[0102] == 1, msg)
|
||||
|
||||
# test "ISZ 0101"
|
||||
Memory.memory[0100] = 0030101 # ISZ 0101
|
||||
Memory.memory[0101] = 0177777 # value we are incrementing/testing
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 2
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ISZ 0101" used %d cycles, should be 2' % cycles
|
||||
self.assertTrue(cycles == 2, msg)
|
||||
msg = '"ISZ 0101" left AC containing %07o, should be 2' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 2, msg)
|
||||
msg = '"ISZ 0101" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ISZ 0101" modified PC to %07o, should be 0102' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0102, msg)
|
||||
msg = '"ISZ 0101" modified memory[0101] to %07o, should be 0' % Memory.memory[0101]
|
||||
self.assertTrue(Memory.memory[0101] == 0, msg)
|
||||
|
||||
# test "ISZ *0200"
|
||||
Memory.memory[0100] = 0130200 # ISZ *0200
|
||||
Memory.memory[0200] = 0201 # address of cell we are storing into
|
||||
Memory.memory[0201] = 0177777
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 0177776
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ISZ *0200" used %d cycles, should be 3' % cycles
|
||||
self.assertTrue(cycles == 3, msg)
|
||||
msg = '"ISZ *0200" left AC containing %07o, should be 0177776' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 0177776, msg)
|
||||
msg = '"ISZ *0200" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ISZ *0200" modified memory[0201] to %07o, should be 0' % Memory.memory[0201]
|
||||
self.assertTrue(Memory.memory[0201] == 0, msg)
|
||||
msg = '"ISZ *0200" modified PC to %07o, should be 0102' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0102, msg)
|
||||
|
||||
# test "ISZ 010" check auto-increment locations
|
||||
Memory.memory[0100] = 0030010 # ISZ 010
|
||||
Memory.memory[010] = 0 # value we are incrementing/testing
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 2
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ISZ 010" used %d cycles, should be 2' % cycles
|
||||
self.assertTrue(cycles == 2, msg)
|
||||
msg = '"ISZ 010" left AC containing %07o, should be 2' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 2, msg)
|
||||
msg = '"ISZ 010" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ISZ 010" modified PC to %07o, should be 0101' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0101, msg)
|
||||
msg = '"ISZ 010" modified memory[010] to %07o, should be 1' % Memory.memory[010]
|
||||
self.assertTrue(Memory.memory[010] == 1, msg)
|
||||
|
||||
# test "ISZ *010" no skip
|
||||
Memory.memory[0100] = 0130010 # ISZ *010
|
||||
Memory.memory[010] = 0102 # address of cell we are storing into
|
||||
Memory.memory[0102] = 0
|
||||
Memory.memory[0103] = 1
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 0177777
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ISZ *010" used %d cycles, should be 3' % cycles
|
||||
self.assertTrue(cycles == 3, msg)
|
||||
msg = '"ISZ *010" left AC containing %07o, should be 0177777' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 0177777, msg)
|
||||
msg = '"ISZ *010" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ISZ *010" modified PC to %07o, should be 0101' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0101, msg)
|
||||
msg = '"ISZ *010" modified memory[010] to %07o, should be 0103' % Memory.memory[010]
|
||||
self.assertTrue(Memory.memory[010] == 0103, msg)
|
||||
msg = '"ISZ *010" modified memory[0102] to %07o, should be 0' % Memory.memory[0102]
|
||||
self.assertTrue(Memory.memory[0102] == 0, msg)
|
||||
msg = '"ISZ *010" modified memory[0103] to %07o, should be 2' % Memory.memory[0103]
|
||||
self.assertTrue(Memory.memory[0103] == 2, msg)
|
||||
|
||||
# test "ISZ *010" should skip
|
||||
Memory.memory[0100] = 0130010 # ISZ *010
|
||||
Memory.memory[010] = 0102 # address of cell we are storing into
|
||||
Memory.memory[0102] = 0
|
||||
Memory.memory[0103] = 0177777
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 0177777
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ISZ *010" used %d cycles, should be 3' % cycles
|
||||
self.assertTrue(cycles == 3, msg)
|
||||
msg = '"ISZ *010" left AC containing %07o, should be 0177777' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 0177777, msg)
|
||||
msg = '"ISZ *010" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ISZ *010" modified PC to %07o, should be 0102' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0102, msg)
|
||||
msg = '"ISZ *010" modified memory[010] to %07o, should be 0103' % Memory.memory[010]
|
||||
self.assertTrue(Memory.memory[010] == 0103, msg)
|
||||
msg = '"ISZ *010" modified memory[0102] to %07o, should be 0' % Memory.memory[0102]
|
||||
self.assertTrue(Memory.memory[0102] == 0, msg)
|
||||
msg = '"ISZ *010" modified memory[0103] to %07o, should be 0' % Memory.memory[0103]
|
||||
self.assertTrue(Memory.memory[0103] == 0, msg)
|
||||
|
||||
def test_JMS(self):
|
||||
Trace.init('test_JMS.trace')
|
||||
Trace.settrace(True)
|
||||
Memory.init()
|
||||
|
||||
# test "JMS 0101"
|
||||
Memory.memory[0100] = 0034101 # JMS 0101
|
||||
Memory.memory[0101] = 0 # location we are storing PC into
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 2
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"JMS 0101" used %d cycles, should be 2' % cycles
|
||||
self.assertTrue(cycles == 2, msg)
|
||||
msg = '"JMS 0101" left AC containing %07o, should be 2' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 2, msg)
|
||||
msg = '"JMS 0101" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"JMS 0101" modified PC to %07o, should be 0102' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0102, msg)
|
||||
msg = '"JMS 0101" modified memory[0101] to %07o, should be 0101' % Memory.memory[0101]
|
||||
self.assertTrue(Memory.memory[0101] == 0101, msg)
|
||||
|
||||
# test "JMS *0101"
|
||||
Memory.memory[0100] = 0134101 # JMS *0101
|
||||
Memory.memory[0101] = 0200
|
||||
Memory.memory[0200] = 1 # location we are storing PC into
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 2
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"JMS *0101" used %d cycles, should be 3' % cycles
|
||||
self.assertTrue(cycles == 3, msg)
|
||||
msg = '"JMS *0101" left AC containing %07o, should be 2' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 2, msg)
|
||||
msg = '"JMS *0101" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"JMS *0101" modified memory[0200] to %07o, should be 0101' % Memory.memory[0200]
|
||||
self.assertTrue(Memory.memory[0200] == 0101, msg)
|
||||
msg = '"JMS *0101" modified PC to %07o, should be 0201' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0201, msg)
|
||||
|
||||
# test "JMS *010
|
||||
Memory.memory[0100] = 0134010 # JMS *010
|
||||
Memory.memory[010] = 0200
|
||||
Memory.memory[0201] = 0 # location we are storing PC into
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 2
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"JMS *010" used %d cycles, should be 3' % cycles
|
||||
self.assertTrue(cycles == 3, msg)
|
||||
msg = '"JMS *010" left AC containing %07o, should be 2' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 2, msg)
|
||||
msg = '"JMS *010" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"JMS *010" modified PC to %07o, should be 0202' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0202, msg)
|
||||
msg = '"JMS *010" modified memory[010] to %07o, should be 0201' % Memory.memory[010]
|
||||
self.assertTrue(Memory.memory[010] == 0201, msg)
|
||||
msg = '"JMS *010" modified memory[0201] to %07o, should be 0101' % Memory.memory[0201]
|
||||
self.assertTrue(Memory.memory[0201] == 0101, msg)
|
||||
|
||||
def test_ADD(self):
|
||||
Trace.init('test_ADD.trace')
|
||||
Trace.settrace(True)
|
||||
Memory.init()
|
||||
|
||||
# test "ADD 0101"
|
||||
Memory.memory[0100] = 0064101 # ADD 0101
|
||||
Memory.memory[0101] = 0 # value we are adding to PC
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 0
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ADD 0101" used %d cycles, should be 2' % cycles
|
||||
self.assertTrue(cycles == 2, msg)
|
||||
msg = '"ADD 0101" left AC containing %07o, should be 0' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 0, msg)
|
||||
msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ADD 0101" modified PC to %07o, should be 0101' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0101, msg)
|
||||
|
||||
# test "ADD 0101" add 1 to 0
|
||||
Memory.memory[0100] = 0064101 # ADD 0101
|
||||
Memory.memory[0101] = 1 # value we are adding to PC
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 0
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ADD 0101" used %d cycles, should be 2' % cycles
|
||||
self.assertTrue(cycles == 2, msg)
|
||||
msg = '"ADD 0101" left AC containing %07o, should be 1' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 1, msg)
|
||||
msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 1, msg)
|
||||
msg = '"ADD 0101" modified PC to %07o, should be 0101' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0101, msg)
|
||||
|
||||
# test "ADD 0101" add 1 to 0177777, L=1 before
|
||||
Memory.memory[0100] = 0064101 # ADD 0101
|
||||
Memory.memory[0101] = 1 # value we are adding to PC
|
||||
MainCPU.init()
|
||||
MainCPU.AC = 0177777
|
||||
MainCPU.L = 1
|
||||
MainCPU.PC = 0100
|
||||
MainCPU.running = True
|
||||
cycles = MainCPU.execute_one_instruction()
|
||||
Trace.itraceend(False)
|
||||
msg = '"ADD 0101" used %d cycles, should be 2' % cycles
|
||||
self.assertTrue(cycles == 2, msg)
|
||||
msg = '"ADD 0101" left AC containing %07o, should be 0' % MainCPU.AC
|
||||
self.assertTrue(MainCPU.AC == 0, msg)
|
||||
msg = '"ADD 0101" modified L to %01o, should be 0' % MainCPU.L
|
||||
self.assertTrue(MainCPU.L == 0, msg)
|
||||
msg = '"ADD 0101" modified PC to %07o, should be 0101' % MainCPU.PC
|
||||
self.assertTrue(MainCPU.PC == 0101, msg)
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
|
||||
if __name__ == '__main__':
|
||||
suite = unittest.makeSuite(TestPymlac, 'test')
|
||||
#suite = unittest.makeSuite(TestPymlac, 'test_JMS')
|
||||
runner = unittest.TextTestRunner()
|
||||
runner.run(suite)
|
||||
|
||||
Reference in New Issue
Block a user