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mirror of https://github.com/rzzzwilson/pymlac.git synced 2025-06-10 09:32:41 +00:00

Removed debug, better trace

This commit is contained in:
Ross Wilson
2015-07-26 10:58:48 +07:00
parent c3e010f530
commit 2cf82e2d7c
5 changed files with 14 additions and 21 deletions

View File

@@ -60,7 +60,6 @@ class DisplayCPU(object):
return result
def doDEIMByte(self, byte):
print('doDEIMByte')
if byte & 0x80: # increment?
prevDX = self.DX
prevDY = self.DY

View File

@@ -8,13 +8,6 @@ The Imlac main CPU.
import sys
from Globals import *
#import DisplayCPU
#import Memory
#import Ptr
#import Ptp
#import TtyIn
#import TtyOut
#import Kbd
import Trace
@@ -228,7 +221,6 @@ class MainCPU(object):
def i_DAC(self, indirect, address, instruction):
address = self.memory.eff_address(address, indirect)
self.memory.put(self.AC, address, False)
print('DAC: stored %07o at address %07o' % (self.AC, address))
Trace.itrace('DAC', indirect, address)
return 3 if indirect else 2

View File

@@ -185,7 +185,6 @@ class Memory(object):
self.using_rom = True
i = self.ROM_START
for ptr_value in self.PTR_ROM_IMAGE:
print('Storing %07o at address %07o' % (ptr_value, i))
self.memory[i] = ptr_value
i += 1
elif romtype == 'tty':
@@ -265,8 +264,6 @@ class Memory(object):
Trace.comment('Attempt to write to ROM')
return
print('Storing value %07o at address %07o' % (MASK_16(value), address))
try:
self.memory[address] = MASK_16(value)
except IndexError:

View File

@@ -83,7 +83,6 @@ class Ptr(object):
def read(self):
"""Read papertape value."""
print('Ptr: value=%04o' % self.value)
return self.value
def eof(self):

View File

@@ -403,7 +403,6 @@ class PymlacFrame(wx.Frame):
# now perform operations
for (operation, args) in ops:
print('%s: operation=%s, args=%s' % ('*'*60, operation, str(args)))
if operation == 'boot':
self.memory.set_ROM(args)
Trace.comment('Bootstrap ROM set to %s' % args.upper())
@@ -517,27 +516,34 @@ class PymlacFrame(wx.Frame):
Trace.tracing = False
def execute_once(self):
# decide if trace should be on/off
if self.traceend is None:
if self.cpu.PC == self.tracestart:
Trace.settrace(True)
else:
Trace.settrace(self.cpu.PC >= self.tracestart and
self.cpu.PC <= traceend)
self.cpu.PC <= self.traceend)
# execute and trace the Display CPU
if self.display_cpu.ison():
Trace.trace('%6.6o' % self.display_cpu.DPC)
Trace.trace('\t')
instruction_cycles = self.display_cpu.execute_one_instruction()
Trace.trace('%6.6o\t' % self.cpu.PC)
instruction_cycles += self.cpu.execute_one_instruction()
if instruction_cycles > 0:
Trace.itraceend(self.display_cpu.ison())
# execute and trace the Main CPU
if self.cpu.running:
Trace.trace('%6.6o\t' % self.cpu.PC)
else:
Trace.trace('\t')
cpu_cycles = self.cpu.execute_one_instruction()
instruction_cycles += cpu_cycles
if cpu_cycles < 1:
Trace.trace('\t\t')
Trace.itraceend(self.display_cpu.ison())
self.__tick_all(instruction_cycles)